TPA3250D2DDW

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPA3250 SLASE99A – DECEMBER 2015 – REVISED APRIL 2016 TPA3250 70-W Stereo, 130-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier 1 Features • • 1 • • • • • • • • Differential Analog Inputs Total Output Power at 10%THD+N – 70-W Stereo Continuous into 8 Ω in BTL Configuration at 32 V – 130-W Stereo Peak into 4 Ω in BTL Configuration at 32 V Total Output Power at 1%THD+N – 60-W Stereo Continuous into 8 Ω in BTL Configuration at 32 V – 105-W Stereo Peak into 4 Ω in BTL Configuration at 32 V Advanced Integrated Feedback Design with Highspeed Gate Driver Error Correction (PurePath™ Ultra-HD) – Signal Bandwidth up to 100 kHz for High Frequency Content From HD Sources – Ultra Low 0.005% THD+N at 1 W into 4 Ω and 400ms /RESET AVDD tAVDD ramp C 100µs /FAULT tPrecharge C 220ms VIN_X OUT_X VOUT_X tStartup ramp Figure 25. Startup Timing When RESET is released to turn on TPA3250, FAULT signal will turn low and AVDD voltage regulator will be enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). After a precharge time to stabilize the DC voltage across the input AC coupling capacitors, before the ramp up sequence starts. 11.3 Powering Down The TPA3250 does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks by initiating a controlled ramp down sequence of the output voltage. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPA3250 29 TPA3250 SLASE99A – DECEMBER 2015 – REVISED APRIL 2016 www.ti.com 11.4 Thermal Design 11.4.1 Thermal Performance TPA3250 thermal performance is dependent on the thermal design of the PCB. As a result, the maximum continuous output power attainable will be influenced by the PCB design. The continuous power rating is lower than the peak output power capability of the device. TPA3250 peak power rating is based on the burst capability of the device. The peak to average power ratio of TPA3250 is well suited to handle even demanding audio playback without thermal shutdown. Thermal performance with typical audio content (burst) versus sine wave content (continuous) should be considered when defining the thermal test requirements for the end product. 11.4.2 Thermal Performance with Continuous Output Power It is recommended to operate TPA3250 below the OTW threshold, which in most systems will require the average output power to be below the maximum peak output power. The maximum continuous power TPA3250 will deliver depends directly on the thermal design of the PCB and for the entire system (closed box with no air flow, or a fanned system etc.). Thermal performance is also impacted by PVDD voltage and switching frequency. The best configuration for a given application will often depend on the continuous output power requirements. Table 12. Device and PCB Temperatures with 8-Ω Load, TA = 40°C TA = 40°C, TPA3250 EVM, No Airflow. Steady State Temperatures. (1) PVDD Switching Frequency Device Top Temperature Maximum PCB Temperature 32V 450kHz 73W 32V 450kHz 18W 10% THD 114°C 89°C 1/4 of 10% THD power 87°C 32V 450kHz 71°C 9W 1/8 of 10% THD power 77°C 32V 65°C 600kHz 72W 10% THD 128°C 98°C 32V 600kHz 18W 1/4 of 10% THD power 105°C 84°C 32V 600kHz 9W 1/8 of 10% THD power 85°C 70°C 36V 450kHz 92W 10% THD 150°C 113°C 36V 450kHz 23W 1/4 of 10% THD power 111°C 87°C 36V 450kHz 11.5W 1/8 of 10% THD power 79°C 71°C 36V 600kHz 91W 36V 600kHz 22.5W 1/4 of 10% THD power 144°C 109°C 36V 600kHz 11.5W 1/8 of 10% THD power 115°C 90°C Continuous Power [W] OTW after 236 seconds OTW after 95 seconds OTW after 3 seconds. Not recommended. OTE (1) 10% THD Comment OTW after 152 seconds Steady state data is not available because device heats up to OTE in this condition. Table 13. Device and PCB Temperatures with 4-Ω Load, TA = 40°C TA = 40°C, TPA3250 EVM, No Airflow. Steady State Temperatures. (1) 30 PVDD Switching Frequency 32V 450kHz 130W 10% THD 32V 450kHz 32.5W 1/4 of 10% THD power 147°C 111°C 32V 450kHz 16W 1/8 of 10% THD power 107°C 85°C 32V 600kHz 130W 10% THD OTE (1) OTW after 1 second. Not recommended. 32V 600kHz 32.5W 1/4 of 10% THD power OTE (1) OTW after 29 seconds. Not recommended. 32V 600kHz 16W 1/8 of 10% THD power 36V 450kHz 165W 10% THD OTE (1) OTW after 0 seconds. Not recommended. 36V 450kHz 41W 1/4 of 10% THD power OTE (1) OTW after 11 seconds. Not recommended. Continuous Power [W] Device Top Temperature Maximum PCB Temperature OTW after 1 second.Not recommended. OTE 147°C Comment 99°C OTW after 92 seconds. Not recommended. OTW after 92 seconds. Not recommended. Steady state data is not available because device heats up to OTE in this condition. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPA3250 TPA3250 www.ti.com SLASE99A – DECEMBER 2015 – REVISED APRIL 2016 Table 13. Device and PCB Temperatures with 4-Ω Load, TA = 40°C (continued) TA = 40°C, TPA3250 EVM, No Airflow. Steady State Temperatures. 36V 450kHz 36V 600kHz 21W 1/8 of 10% THD power 142°C 108°C OTW after 134 seconds. Not recommended. Not recommended 11.4.3 Thermal Performance with Non-Continuous Output Power As audio signals often have a peak to average ratio larger than one (average level below maximum peak output), the thermal performance for audio signals can be illustrated using burst signals with different burst ratios. Figure 26. Example of audio signal A burst signal is characterized by the high-level to low-level ratio as well as the duration of the high level and low level, e.g. a burst 1:4 stimuli is a single period of high level followed by 4 cycles of low level. High level Low level 1cycle : 4cycles Figure 27. Example of 1:4 Burst Signal The following analysis of thermal performance for TPA3250 is made with the TPA3250 EVM surrounded by still air (no airflow) with a controlled air temperature of 40°C. For 32-V operation the system is not thermally limited with 8Ω load, but depending on the burst stimuli for operation at 36V some thermal limitations may occur, depending on switching frequency and average to maximum power ratio. Low to maximum power ratio of the burst stimuli is given in the plots as for example P1:8 which equals 1 cycle of full power followed by 8 cycles of low power. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPA3250 31 TPA3250 www.ti.com 130 130 120 120 110 110 Temperature (qC) Temperature (qC) SLASE99A – DECEMBER 2015 – REVISED APRIL 2016 100 90 80 80 70 60 60 Device Top P1:8 PCB Max P1:8 Device Top P1:4 PCB Max P1:4 Device Top P1:2 PCB Max P1:2 Device Top P1:8 PCB Max P1:8 Device Top P1:4 PCB Max P1:4 50 1:8 1:4 1:2 1 Burst Ratio (High:Low) PVDD = 32V, fs = 450kHz 1:8 TA = 40°C PVDD = 32V, fs = 600kHz 120 120 110 110 Temperature (qC) 130 90 80 70 1 D021 RL = 8Ω TA = 40°C 100 90 80 70 Device Top P1:8 PCB Max P1:8 Device Top P1:4 PCB Max P1:4 60 1:2 Figure 29. Device and PCB Temperatures vs. Burst Ratio 130 100 1:4 Burst Ratio (High:Low) D022 RL = 8Ω Figure 28. Device and PCB Temperatures vs. Burst Ratio Temperature (qC) 90 70 50 60 50 Device Top P1:8 PCB Max P1:8 50 1:8 1:4 1:2 Burst Ratio (High:Low) PVDD = 36V, fs = 450kHz RL = 8Ω 1 1:8 1:4 1:2 Burst Ratio (High:Low) D023 TA = 40°C Figure 30. Device and PCB Temperatures vs. Burst Ratio 32 100 PVDD = 36V, fs = 600kHz RL = 8Ω 1 D024 TA = 40°C Figure 31. Device and PCB Temperatures vs. Burst Ratio Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPA3250 TPA3250 www.ti.com SLASE99A – DECEMBER 2015 – REVISED APRIL 2016 12 Layout 12.1 Layout Guidelines • • • • • • • • • Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for power and audio signals. Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible, since the ground pins are the best conductors of heat in the package. PCB layout, audio performance and EMI are linked closely together. Routing the audio input should be kept short and together with the accompanied audio source ground. The small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins as possible. A local ground area underneath the device is important to keep solid to minimize ground bounce. Orient the passive component so that the narrow end of the passive component is facing the TPA3250 device, unless the area between two pads of a passive component is large enough to allow copper to flow in between the two pads. Avoid placing other heat producing components or structures near the TPA3250 device. Avoid cutting off the flow of heat from the TPA3250 device to the surrounding ground areas with traces or via strings, especially on output side of device. Netlist for this printed circuit board is generated from the schematic in Figure 32. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPA3250 33 TPA3250 SLASE99A – DECEMBER 2015 – REVISED APRIL 2016 www.ti.com 12.2 Layout Examples 12.2.1 BTL Application Printed Circuit Board Layout Example Pad to top layer ground pour Top Layer Signal Traces Bottom Layer Signal Traces Bottom to top layer connection via System Processor 10k 22k 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 T1 T2 T2 T1 A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image) B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces should be blocking the current path. C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors placed close to the pins. D. Note T3: PowerPad™ needs to be soldered to PCB GND copper pour Figure 32. BTL Application Printed Circuit Board - Composite 34 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPA3250 TPA3250 www.ti.com SLASE99A – DECEMBER 2015 – REVISED APRIL 2016 Layout Examples (continued) 12.2.2 SE Application Printed Circuit Board Layout Example Pad to top layer ground pour Top Layer Signal Traces Bottom Layer Signal Traces Bottom to top layer connection via System Processor 10k 22k 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 T1 T2 T2 T1 A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image) B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces should be blocking the current path. C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed close to the pins. D. Note T3: PowerPad™ needs to be soldered to PCB GND copper pour Figure 33. SE Application Printed Circuit Board - Composite Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPA3250 35 TPA3250 SLASE99A – DECEMBER 2015 – REVISED APRIL 2016 www.ti.com Layout Examples (continued) 12.2.3 PBTL Application Printed Circuit Board Layout Example Pad to top layer ground pour Top Layer Signal Traces Bottom Layer Signal Traces Bottom to top layer connection via System Processor Grounded for PBTL Grounded for PBTL 10k 22k 1 44 23 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 14 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 T1 T2 T2 T1 A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image) B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces should be blocking the current path. C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed close to the pins. D. ote T3: PowerPad™ needs to be soldered to PCB GND copper pour Figure 34. PBTL Application Printed Circuit Board - Composite 36 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPA3250 TPA3250 www.ti.com SLASE99A – DECEMBER 2015 – REVISED APRIL 2016 13 Device and Documentation Support 13.1 Documentation Support TPA3250D2EVM User's Guide, SLVUAG8 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks PurePath, PowerPAD, E2E are trademarks of Texas Instruments. Blu-ray Disk is a trademark of Blu-ray Disc Association. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPA3250 37 PACKAGE OUTLINE DDW0044D PowerPAD TM TSSOP - 1.2 mm max height SCALE 1.250 PLASTIC SMALL OUTLINE 8.3 TYP 7.9 PIN 1 ID AREA A 42X 0.635 44 1 14.1 13.9 NOTE 3 2X 13.335 22 23 B 44X 6.2 6.0 0.27 0.17 0.08 0.1 C C A B SEATING PLANE C (0.15) TYP SEE DETAIL A 23 22 4.43 3.85 EXPOSED THERMAL PAD 7.30 6.72 0.25 GAGE PLANE 45 0 -8 2X (0.6) NOTE 5 2X (0.13) NOTE 5 1 1.2 MAX 0.75 0.50 0.15 0.05 DETAIL A TYPICAL 44 4223171/A 07/2016 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may differ or may not be present. www.ti.com EXAMPLE BOARD LAYOUT DDW0044D PowerPAD TM TSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE (5.2) NOTE 9 SOLDER MASK DEFINED PAD (4.43) SEE DETAILS SYMM 44X (1.45) 1 44 44X (0.4) 42X (0.635) (1.3) TYP 45 SYMM (7.3) (14) NOTE 9 (R0.05) TYP ( 0.2) TYP VIA 23 22 METAL COVERED BY SOLDER MASK (0.65) TYP (1.3 TYP) (7.5) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.05 MIN AROUND 0.05 MAX AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4223171/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN DDW0044D PowerPAD TM TSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE (4.43) BASED ON 0.125 THICK STENCIL 44X (1.45) 1 44 44X (0.4) 42X (0.635) 45 SYMM (7.3) BASED ON 0.125 THICK STENCIL 22 23 METAL COVERED BY SOLDER MASK SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SYMM (7.5) SOLDER PASTE EXAMPLE PAD 45: 100% PRINTED SOLDER COVERAGE BY AREA SCALE:6X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.125 0.15 0.175 4.95 X 8.16 4.43 X 7.30 (SHOWN) 4.04 X 6.66 3.74 X 6.17 4223171/A 07/2016 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPA3250D2DDW ACTIVE HTSSOP DDW 44 35 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 3250 TPA3250D2DDWR ACTIVE HTSSOP DDW 44 2000 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 3250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of