TPA5052RSAR

2 05 A5 TP TPA5052 www.ti.com SLOS500A – JUNE 2006 – REVISED AUGUST 2006 STEREO DIGITAL AUDIO LIP-SYNC DELAY FEATURES APPLICATIONS • • • • • • • • • • • • • Digital Audio Format: 16-24-bit I2S Single Serial Input Port Delay Time: 170 ms/ch at fs = 48 kHz Delay Resolution: 256 samples Delay Memory Cleared on Power-Up or After Delay Changes – Eliminates Erroneous Data From Being Output 3.3 V Operation With 5 V Tolerant I/O Supports Audio Bit Clock Rates of 32 to 64 fs with fs = 32 kHz–192 kHz No External Crystal or Oscillator Required – All Internal Clocks Generated From the Audio Clock Surface Mount 4mm × 4mm, 16-pin QFN Package High Definition TV Lip-Sync Delay Flat Panel TV Lip-Sync Delay Home Theater Rear-Channel Effects Wireless Speaker Front-Channel Synchronization Camcorders • DESCRIPTION The TPA5052 accepts a single serial audio input, buffers the data for a selectable period of time, and outputs the delayed audio data on a single serial output. In systems with complex video processing algorithms, one device allows delay of up to 170 ms/ch (fs = 48 kHz) to synchronize the audio stream to the video stream. If more delay is needed, the devices can be connected in series. SIMPLIFIED APPLICATION DIAGRAM Audio Processor Digital Amplifier SCLK TAS3103A or ATSC Processor 3.3 V TAS5504A +TAS5122 LRCLK BCLK LRCLK DATA DATA_OUT SCLK BCLK LRCLK DATA DELx (4:0) DATA VDD BCLK GND TPA5052 5 Fixed Delay Control Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPA5052 www.ti.com SLOS500A – JUNE 2006 – REVISED AUGUST 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN DESCRIPTIONS BCLK DATA_OUT VDD VDD 16 15 14 13 RSA (QFN) PACKAGE (TOP VIEW) DEL3 3 10 DEL0 DEL4 4 9 GND 8 DEL1 GND 11 7 2 GND DATA 6 DEL2 GND 12 5 1 GND LRCLK TERMINAL FUNCTIONS TERMINAL DESCRIPTION NO. DEL0 10 I Delay select pin – LSB. 5V tolerant input. DEL1 11 I Delay select pin. 5V tolerant input. DEL2 12 I Delay select pin. 5V tolerant input. DEL3 3 I Delay select pin. 5V tolerant input. DEL4 4 I Delay select pin - MSB. 5V tolerant input. BCLK 16 I Audio data bit clock input for serial input. 5V tolerant input. DATA 2 I Audio serial data input for serial input. 5V tolerant input. DATA_OUT 15 O Delayed audio serial data output. GND 5–9 P Ground – All ground terminals must be tied to GND for proper operation 1 I Left and Right serial audio sampling rate clock (fs). 5V tolerant input. 13, 14 P Power supply interface. Both pins must be tied to power supply. - Connect to ground. Must be soldered down in all applications to properly secure device on the PCB. LRCLK VDD Thermal Pad 2 I/O NAME Submit Documentation Feedback TPA5052 www.ti.com SLOS500A – JUNE 2006 – REVISED AUGUST 2006 FUNCTIONAL BLOCK DIAGRAM DATA BCLK DELAY MEMORY INPUT BUFFER OUTPUT BUFFER DATA_OUT LRCLK DELx (4:0) CONTROL 5 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted) VDD Supply voltage VI Input voltage (1) DATA, LRCLK, BCLK, DEL[4:0] Continuous total power dissipation VALUE UNIT –0.3 to 3.6 V –0.3 to 5.5 V See Dissipation Rating Table TA Operating free-air temperature range –40 to 85 °C TJ Operating junction temperature range –40 to 125 °C Tstg Storage temperature range –65 to 125 °C 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS (1) (1) PACKAGE TA≤ 25°C POWER RATING DERATING FACTOR TA = 70°C POWER RATING TA = 85°C POWER RATING RSA 2.5 W 25 mW/°C 1.375 W 1W This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. RECOMMENDED OPERATING CONDITIONS MIN MAX VDD Supply voltage VDD 3 3.6 VIH High-level input voltage DATA, LRCLK, BCLK, DEL[4:0] 2 VIL Low-level input voltage DATA, LRCLK, BCLK, DEL[4:0] TA Operating free-air temperature –40 Submit Documentation Feedback UNIT V V 0.8 V 85 °C 3 TPA5052 www.ti.com SLOS500A – JUNE 2006 – REVISED AUGUST 2006 DC CHARACTERISTICS TA = 25°C, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS IDD Supply current VDD = 3.3 V, fs = 48 kHz, BCLK = 32 × fs IOH High-level output current DATA_OUT = 2.6 V IOL Low-level output current IIH High-level input current IIL Low-level input current MIN DATA_OUT = 0.4 V TYP MAX 1.8 3 mA 5 13 mA 5 13 mA DATA, LRCLK, BCLK, VI = 5.5V, VDD = 3V UNIT 20 DEL[4:0], VI = 3.6V, VDD = 3.6V 5 DATA, LRCLK, BCLK, DEL[4:0], VI = 0V, VDD = 3.6V 1 µA µA Serial Audio Input Ports over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS fSCLKIN Frequency, BCLK 32 × fs, 48 × fs, 64 × fs MIN TYP 1.024 UNIT MHz tsu1 Setup time, LRCLK to BCLK rising edge 10 ns th1 Hold time, LRCLK from BCLK rising edge 10 ns tsu2 Setup time, DATA to BCLK rising edge 10 ns th2 Hold time, DATA from BCLK rising edge 10 LRCLK frequency 32 BCLK duty cycle ns 48 192 kHz 64 BCLK edges 50% LRCLK duty cycle 50% BCLK rising edges between LRCLK rising edges LRCLK duty cycle = 50% 32 BCLK (Input) th1 tsu1 LRCLK (Input) th2 tsu2 DATA Figure 1. Serial Data Interface Timing 4 MAX 12.288 Submit Documentation Feedback TPA5052 www.ti.com SLOS500A – JUNE 2006 – REVISED AUGUST 2006 APPLICATION INFORMATION AUDIO SERIAL INTERFACE The audio serial interface for the TPA5052 consists of a 3-wire synchronous serial port. It includes LRCLK, BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the TPA5052 on the rising edge of BCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers of the serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64 times the sampling frequency for I2S formats. A system clock is not necessary for the operation of the TPA5052. I2S TIMING The I2S data format diagram is shown in Figure 2. 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) 1 DATA 2 3 N–2 N–1 MSB 1 N LSB 2 3 N–2 N–1 MSB LSB 1 N 2 Figure 2. I2S Data Format; L-Channel = LOW, R-Channel = HIGH GENERAL DELAY OPERATION The delay of the TPA5052 is set using the 5 delay pins (DEL4, DEL3, DEL2, DEL1, DEL0). The minimum delay is 255 samples, and occurs when all five pins are at logic 0. The maximum delay is 8191 samples, and occurs when all five pins are at logic 1. The delay can be increased by changing the values on each pin from a 0 to a 1. See Table 1. Delay pin DEL4 is the MSB, and DEL0 is the LSB. The delay is calculated with the following forumula: Audio Delay (in samples) = 4096 x (DEL4) + 2048 x (DEL3) + 1024 x (DEL2) + 512 x (DEL1) + 256 x (DEL0) + 255 Audio Delay (ms) = Audio Delay (in samples) x (1/fs) Both channels have the same amount of delay. They cannot be controlled individually. Table 1. Delay Settings DEL4 DEL3 DEL2 DEL1 DEL0 Delay in Samples 0 0 0 0 0 255 0 0 0 0 1 511 0 0 0 1 0 767 0 0 0 1 1 1023 ↓ ↓ ↓ ↓ ↓ ↓ 1 1 1 1 1 8191 Submit Documentation Feedback 5 TPA5052 www.ti.com SLOS500A – JUNE 2006 – REVISED AUGUST 2006 TPA5052 Operation Only a single decoupling capacitor (0.1 µF–1 µF) is required across VDD and GND. The DELx terminals can be directly connected to VDD or GND. Table 1 describes the delay settings selectable via the DELx terminals. A schematic implementation of the TPA5052 is shown in Figure 3. 3.3 V 0.1 mF VDD Digital Audio Word Clock Bit Clock DATA_OUT Delayed Audio DATA LRCLK BCLK GND DEL0 DEL1 DEL2 DEL3 Fixed Delay Select DEL4 GND Figure 3. TPA5052 Schematic COMPLETE UPDATE To avoid pops and clicks in the audio stream when the delay is changed, the TPA5052 holds each channel in an internal mute mode until all the set number of samples have passed. For example, if the delay is set to 511 samples, the TPA5052 holds each channel in mute until all 511 samples of audio data have passed. 6 Submit Documentation Feedback TPA5052 www.ti.com SLOS500A – JUNE 2006 – REVISED AUGUST 2006 APPLICATION EXAMPLES Connecting Two Devices in Series to Increase the Delay It is sometimes desirable to increase the delay time beyond the limit which one device provides. In such cases, the TPA5052 device can be placed in a series to increase the delay. See Figure 4 for an example. Audio Processor BCLK LRCLK DATA Audio Amplifier BCLK LRCLK DATA BCLK BCLK LRCLK LRCLK DATA DATA_OUT DEL4 DEL3 DEL2 DEL4 DEL3 DEL2 VDD 0.1 mF DEL1 DATA_OUT VDD 0.1 mF DEL1 GND DEL0 DATA GND DEL0 SCLK SCLK Figure 4. Two Devices in Series DEVICE CURRENT CONSUMPTION The TPA5052 draws different amounts of supply current depending upon the conditions under which it is operated. As VDD increases, so too does IDD. Likewise, as VDD decreases, IDD decreases. The same is true of the sampling frequency, fs. An increase in fs causes an increase in IDD. Figure 5 illustrates the relationship between operating condition and typical supply current. SUPPLY CURRENT vs SAMPLE FREQUENCY 5 IDD - Supply Current - mA 4.5 BCLK = 64 fs Data = 24 bit VDD = 3.6 V 4 3.5 3 2.5 VDD = 3.3 V 2 VDD = 3 V 1.5 1 0.5 0 32 52 72 92 112 132 152 172 192 fs - Sampling Frequency - kHz Figure 5. Typical Supply Current Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPA5052RSAR ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPA 5052 TPA5052RSAT ACTIVE QFN RSA 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPA 5052 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of