TPA6102A2DGKR

   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 D D D D D D D D D D D or DGK PACKAGE (TOP VIEW) 50-mW Stereo Output Low Supply Current . . . 0.75 mA Low Shutdown Current . . . 50 nA Minimal External Components Required Gain Set Internally to 14 dB Pop Reduction Circuitry Internal Mid-Rail Generation Thermal and Short-Circuit Protection Surface-Mount Packaging − MSOP − SOIC 1.6-V to 3.6-V Supply Voltage Range BYPASS GND SHUTDOWN IN2− 1 8 2 7 3 6 4 5 IN1− VO 1 VDD VO 2 description The TPA6102A2 is a stereo audio power amplifier packaged in either an 8-pin SOIC package or an 8-pin MOSP package capable of delivering 50 mW of continuous RMS power per channel into 16-Ω loads. Amplifier gain is internally set to 14 dB (inverting) to save board space by eliminating six external resistors. The TPA6102A2 is optimized for battery applications because of its low-supply current, shutdown current, and THD+N. To obtain the low-supply voltage range, the TPA6102A2 biases BYPASS to VDD/4. When driving a 16-Ω load with 40-mW output power from 3.3 V, THD+N is 0.08% at 1 kHz, and less than 0.2% across the audio band of 20 Hz to 20 kHz. For 30 mW into 32-Ω loads, the THD+N is reduced to less than 0.06% at 1 kHz, and is less than 0.3% across the audio band of 20 Hz to 20 kHz. typical application circuit VDD 6 100 kΩ Audio Input VDD/4 8 IN 1− 20 kΩ CI 100 kΩ − + VO1 7 − + VO2 5 VDD CS CC 1 BYPASS CB Audio Input 4 IN 2− 20 kΩ CI From Shutdown Control Circuit CC 100 kΩ 3 SHUTDOWN Bias Control 2 100 kΩ Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated 
 
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      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 AVAILABLE OPTIONS PACKAGED DEVICE TA SMALL OUTLINE (D) MSOP (DGK) MSOP SYMBOLIZATION −40°C to 85°C TPA6102A2D TPA6102A2DGK AJN Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BYPASS 1 I Tap to voltage divider for internal mid-supply bias supply. BYPASS is set at VDD/4. Connect to a 0.1-µF to 1-µF low ESR capacitor for best performance. GND 2 I GND is the ground connection. IN1− 8 I IN1− is the inverting input for channel 1. IN2− 4 I IN2− is the inverting input for channel 2. SHUTDOWN 3 I Active-low input. When held low, the device is placed in a low supply current mode. VDD VO1 6 I 7 O VDD is the supply voltage terminal. VO1 is the audio output for channel 1. VO2 5 O VO2 is the audio output for channel 2. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 710 mW 5.68 mW/°C 454 mW 369 mW DGK 469 mW 3.75 mW/°C 300 mW 244 mW ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ recommended operating conditions Supply voltage, VDD MIN MAX 1.6 3.6 60% x VDD High-level input voltage, VIH (SHUTDOWN) Low-level input voltage, VIL (SHUTDOWN) Operating free-air temperature, TA 2 −40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 25% x VDD V 85 °C 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 dc electrical characteristics at TA = 25°C, VDD = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS VOO PSRR Output offset voltage Power supply rejection ratio AV = 14 dB VDD = 3 V to 3.6 V IDD Supply current SHUTDOWN = 3.6 V IDD(SD) Supply current in SHUTDOWN mode SHUTDOWN = 0 V |IIH| High-level input current (SHUTDOWN) |IIL| Low-level input current (SHUTDOWN) VDD = 3.6 V, VI= VDD VDD = 3.6 V, VI= 0 V ZI Input impedance MIN TYP MAX 5 40 72 UNIT mV dB 0.75 1.5 mA 50 250 nA 1 µA 1 20 µA kΩ ac operating characteristics, VDD = 3.3 V, TA = 25°C, RL = 16 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 14 dB PO THD+N Output power (each channel) THD ≤ 0.1%, f = 1 kHz Total harmonic distortion + noise 20−20 kHz BOM kSVR Maximum output power BW PO = 45 mW, THD < 0.5% 50 mW > 20 kHz Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 50 mW 86 dB Vn Noise output voltage (no noise weighting filter) 45 µV(rms) 0.4% ac operating characteristics, VDD = 3.3 V, TA = 25°C, RL = 32 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain PO THD+N Output power (each channel) THD ≤ 0.1%, f = 1 kHz Total harmonic distortion + noise Maximum output power BW PO = 30 mW, THD < 0.4% 20−20 kHz BOM kSVR > 20 kHz Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 30 mW 86 dB Vn Noise output voltage (no noise weighting filter) 50 µV(rms) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14 dB 35 mW 0.4% 3 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 dc electrical characteristics at TA = 25°C, VDD = 1.6 V (unless otherwise noted) PARAMETER VOO PSRR Output offset voltage TEST CONDITIONS MIN TYP MAX 5 40 UNIT Power supply rejection ratio AV = 14 dB VDD = 1.4 V to 1.8 V 80 mV IDD Supply current SHUTDOWN = 1.6 V 0.65 1.2 mA IDD(SD) Supply current in SHUTDOWN mode SHUTDOWN = 0 V 50 250 nA |IIH| High-level input current (SHUTDOWN) µA Low-level input current (SHUTDOWN) VDD = 1.6 V, VI = VDD VDD = 1.6 V, VI = 0 V 1 |IIL| ZI Input impedance dB 1 20 µA kΩ ac operating characteristics, VDD = 1.6 V, TA = 25°C, RL = 16 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 14 dB PO THD+N Output power (each channel) THD ≤ 0.5%, f = 1 kHz Total harmonic distortion + noise 20−20 kHz BOM kSVR Maximum output power BW PO = 9.5 mW, THD < 1% 10 mW > 20 kHz Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 10 mW 82 dB Vn Noise output voltage (no noise weighting filter) 32 µV(rms) 0.06% ac operating characteristics, VDD = 1.6 V, TA = 25°C, RL = 32 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain PO THD+N Output power (each channel) THD ≤ 0.5%, f = 1 kHz 14 dB 7.5 mW Total harmonic distortion + noise Maximum output power BW PO = 6.5 mW, THD < 1% 20−20 kHz BOM kSVR > 20 kHz Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 7.5 mW 84 dB Vn Noise output voltage (no noise weighting filter) 32 µV(rms) 0.05% TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Frequency THD+N 1, 3, 5, 7, 9, 11 vs Output power 2, 4, 6, 8, 10, 12 vs Output voltage 13, 14 PO kSVR Output power vs Load resistance 15, 16 Supply ripple rejection ratio vs Frequency 17, 18 Vn Output noise voltage vs Frequency 19, 20 Crosstalk vs Frequency 21, 22 Closed−loop gain and phase vs Frequency 23, 24, 25, 26 Supply current vs Supply voltage 27 Power dissipation vs Output power 28 IDD PD 4 Total harmonic distortion plus noise POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER 10 1 THD+N − Total Harmonic Distortion Plus Noise − % THD+N − Total Harmonic Distortion Plus Noise − % TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY VDD = 1.6 V PO = 9.5 mW CB = 1 µF RL = 16 Ω 0.1 0.01 0.001 0.0001 20 100 1k f − Frequency − Hz 10 k 10 VDD = 1.6 V CB = 1 µF RL = 16 Ω f = 1 kHz 1 0.1 0.01 0.001 1 20 k 10 PO − Output Power − mW Figure 1 Figure 2 10 VDD = 1.6 V PO = 6.5 mW CB = 1 µF RL = 32 Ω 0.1 0.01 0.001 0.0001 20 100 TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion Plus Noise − % THD+N − Total Harmonic Distortion Plus Noise − % TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 1 1k f − Frequency − Hz 100 10 k 20 k 10 VDD = 1.6 V CB = 1 µF RL = 32 Ω f = 1 kHz 1 0.1 0.01 0.001 1 Figure 3 10 PO − Output Power − mW 100 Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS 10 VDD = 1.6 V PO = 4.5 mW CB = 1 µF RL = 50 Ω 1 0.1 0.01 0.001 0.0001 20 100 TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion Plus Noise − % THD+N − Total Harmonic Distortion Plus Noise − % TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 1k f − Frequency − Hz 10 k 20 k 10 VDD = 1.6 V CB = 1 µF RL = 50 Ω f = 1 kHz 1 0.1 0.01 0.001 1 10 PO − Output Power − mW Figure 5 Figure 6 10 VDD = 3.3 V PO = 45 mW CB = 1 µF RL = 16 Ω 0.1 0.01 0.001 0.0001 20 100 TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion Plus Noise − % THD+N − Total Harmonic Distortion Plus Noise − % TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 1 1k f − Frequency − Hz 10 k 20 k 10 1 VDD = 3.3 V CB = 1 µF RL = 16 Ω f = 1 kHz 0.1 0.01 0.001 0.0001 20 Figure 7 6 100 100 1k PO − Output Power − mW Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 k 20 k 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS 10 1 VDD = 3.3 V PO = 30 mW CB = 1 µF RL = 32 Ω 0.1 0.01 0.001 0.0001 20 100 TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion Plus Noise − % THD+N − Total Harmonic Distortion Plus Noise − % TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 1k f − Frequency − Hz 10 VDD = 3.3 V CB = 1 µF RL = 32 Ω f = 1 kHz 1 0.1 0.01 0.001 10 k 20 k 1 10 PO − Output Power − mW Figure 9 VDD = 3.3 V PO = 20 mW CB = 1 µF RL = 50 Ω 0.1 0.01 0.001 100 TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion Plus Noise − % THD+N − Total Harmonic Distortion Plus Noise − % 10 0.0001 20 1k f − Frequency − Hz 200 Figure 10 TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 1 100 10 k 20 k 10 VDD = 3.3 V CB = 1 µF RL = 50 Ω f = 1 kHz 1 0.1 0.01 0.001 1 Figure 11 10 PO − Output Power − mW 100 200 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT VOLTAGE 10 THD+N − Total Harmonic Distortion Plus Noise − % THD+N − Total Harmonic Distortion Plus Noise − % TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT VOLTAGE VDD = 1.6 V RL = 10 kΩ Frequency = 20 Hz 1 0.1 0.01 0.001 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 VDD = 3.3 V RL = 10 kΩ Frequency = 20 Hz 1 0.1 0.01 0.001 1 0 0.2 VO − Output Voltage − V Figure 13 150 VDD = 1.6 V THD+N = 1% Mode = Stereo VDD = 3.6 V THD+N = 1% Mode = Stereo 125 PO − Output Power − mW 12 PO − Output Power − mW 1.4 OUTPUT POWER vs LOAD RESISTANCE 15 9 6 3 100 75 50 25 20 24 28 32 36 40 44 48 50 0 16 20 RL − Load Resistance − Ω Figure 15 8 1.2 Figure 14 OUTPUT POWER vs LOAD RESISTANCE 0 16 0.4 0.6 0.8 1 VO − Output Voltage − V 24 28 32 36 40 RL − Load Resistance − Ω Figure 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 44 48 50 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY 0 VDD = 1.6 V CB = 1 µF RL = 32 Ω −10 −20 k SVR− Supply Ripple Rejection Ratio − dB k SVR− Supply Ripple Rejection Ratio − dB 0 −30 −40 −50 −60 −70 −80 −90 −100 −110 VDD = 3.3 V CB = 1 µF RL = 32 Ω −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −120 10 100 1k 10 10 k 20 k 100 1k f − Frequency − Hz f − Frequency − Hz Figure 17 Figure 18 OUTPUT NOISE VOLTAGE vs FREQUENCY OUTPUT NOISE VOLTAGE vs FREQUENCY 100 V n − Output Noise Voltage − µ V(rms) 100 V n − Output Noise Voltage − µ V(rms) 10 k 20 k 10 VDD = 1.6 V CB = 1 µF RL = 16 Ω 10 VDD = 3.3 V CB = 1 µF RL = 16 Ω 1 1 20 100 1k f − Frequency − Hz 10 k 20 k 20 Figure 19 100 1k f − Frequency − Hz 10 k 20 k Figure 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 0 −10 −20 −20 −30 −40 −40 −50 −50 −60 −70 −80 −90 −60 −70 −80 −90 −100 −100 −110 −110 −120 −120 −130 −130 −140 20 VDD = 3.3 V PO = 20 mW RL = 50 Ω −10 Crosstalk − dB Crosstalk − dB −30 VDD = 1.6 V PO = 4.5 mW RL = 50 Ω −140 100 1k 10 k 20 k 20 100 f − Frequency − Hz Figure 21 1k f − Frequency − Hz Figure 22 CLOSED-LOOP GAIN AND PHASE vs FREQUENCY 40 180° Phase 30 150° 120° 90° 10 Gain 60° 0 30° −10 0° −20 −30° −30 −40 −60° VDD = 1.6 V RL = 16 Ω TA = 25°C −90° −120° −50 −60 10 −150° 100 1k 10 k 100 k 1M 10 M f − Frequency − Hz Figure 23 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 −180° 100 M Phase Closed-Loop Gain − dB 20 10 k 20 k 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS CLOSED-LOOP GAIN AND PHASE vs FREQUENCY 40 180° Phase 30 150° 120° 90° 10 Gain 60° 0 30° −10 0° −20 −30° −30 −40 −60° VDD = 1.6 V RL = 32 Ω TA = 25°C −90° −120° −50 −60 10 Phase Closed-Loop Gain − dB 20 −150° 100 1k 10 k 100 k 1M 10 M −180° 100 M f − Frequency − Hz Figure 24 CLOSED-LOOP GAIN AND PHASE vs FREQUENCY 40 180° Phase 30 150° 120° 90° 10 Gain 60° 0 30° −10 0° −20 −30° −30 −40 −60° VDD = 3.3 V RL = 16 Ω TA = 25°C −90° −120° −50 −60 10 Phase Closed-Loop Gain − dB 20 −150° 100 1k 10 k 100 k 1M 10 M −180° 100 M f − Frequency − Hz Figure 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS CLOSED-LOOP GAIN AND PHASE vs FREQUENCY 40 180° Phase 30 150° 120° 90° 10 Gain 60° 0 30° −10 0° −20 −30° −30 −40 Phase Closed-Loop Gain − dB 20 −60° VDD = 3.3 V RL = 32 Ω TA = 25°C −90° −120° −50 −150° −60 10 100 1k 10 k 100 k 1M 10 M −180° 100 M f − Frequency − Hz Figure 26 SUPPLY CURRENT vs SUPPLY VOLTAGE POWER DISSIPATION vs OUTPUT POWER 40 1 VDD = 3.3 V VDD Low-to-High 35 PD − Power Dissipation − mW I DD − Supply Current − mA 0.8 0.6 0.4 0.2 30 25 20 15 10 0 5 −0.2 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 0 0 10 VDD − Supply Voltage − V Figure 27 12 20 30 Figure 28 POST OFFICE BOX 655303 40 50 PO − Output Power − mW • DALLAS, TEXAS 75265 60 70 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input capacitor, CI In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, CI and RI form a high-pass filter with the corner frequency determined in equation 1. RI is set internally and is fixed at 20 kΩ. fc + 1 2p R I C I (1) The value of CI is important to consider, as it directly affects the bass (low frequency) performance of the circuit. Consider the example where the specification calls for a flat bass response down to 20 Hz. Equation 1 is reconfigured as equation 2. CI + 1 2p R I f c (2) In this example, CI is 0.40 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. A further consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and the feedback resistor (RF) to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at VDD/4, which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application. power supply decoupling, CS The TPA6102A2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF, placed as close as possible to the device VDD lead, works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the power amplifier is recommended. midrail bypass capacitor, CB The midrail bypass capacitor (CB) serves several important functions. During start-up, CB determines the rate at which the amplifier starts up. This helps to push the start-up pop noise into the subaudible range (so low it can not be heard). The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier. The capacitor is fed from a 55-kΩ source inside the amplifier. To keep the start-up pop as low as possible, the relationship shown in equation 3 should be maintained. ǒC B 1 v 1 ǒCI RIǓ 55 kΩǓ (3) As an example, consider a circuit where CB is 1 µF, CI is 1 µF, and RI is 20 kΩ. Inserting these values into the equation 3 results in: 18.18 ≤ 50 which satisfies the rule. Bypass capacitor (CB) with values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 
   
  
   
      SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION output coupling capacitor, CC In the typical single-supply single-ended (SE) configuration, an output coupling capacitor (CC) is required to block the dc bias at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation 4. fc + 1 2p R L C C (4) The main disadvantage, from a performance standpoint, is that the typically small load impedances drive the low-frequency corner higher. Large values of CC are required to pass low-frequencies into the load. Consider the example where a CC of 68 µF is chosen and loads vary from 32 Ω to 47 kΩ. Table 1 summarizes the frequency response characteristics of each configuration. Table 1. Common-Load Impedances vs Low-Frequency Output Characteristics in SE Mode RL CC Lowest Frequency 32 Ω 68 µF Ą73 Hz 10,000 Ω 68 µF 0.23 Hz 47,000 Ω 68 µF 0.05 Hz As Table 1 indicates, headphone response is adequate and drive into line level inputs (a home stereo for example) is very good. The output-coupling capacitor required in single-supply SE mode also places additional constraints on the selection of other components in the amplifier circuit. With the rules described earlier still valid, add the following relationship: ǒC B 1 v 1 Ơ 1 ǒCI RIǓ RLCC 55 kΩǓ (5) using low-ESR capacitors Low-ESR capacitors are recommended throughout this application. A real capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. 3.3-V versus 1.6-V operation The TPA6102A2 was designed for operation over a supply range of 1.6 V to 3.6 V. There are no special considerations for 1.6-V versus 3.3-V operation as far as supply bypassing, gain setting, or stability. Supply current is slightly reduced from 0.75 mA (typical) to 0.65 mA (typical). The most important consideration is that of output power. Each amplifier can produce a maxium output voltage swing within a few hundred millivolts of the rails with a 10-kΩ load. However, this voltage swing decreases as the load resistance decreases and the rDS(on) as the output stage transistors becomes more significant. For example, for a 32-Ω load, the maximum peak output voltage with VDD = 1.6 V is approximately 0.7 V with no clipping distortion. This reduced voltage swing effectively reduces the maximum undistorted output power. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPA6102A2D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 6102A2 TPA6102A2DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AJN TPA6102A2DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AJN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of