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TPA6111A2
SLOS313C – DECEMBER 2000 – REVISED MARCH 2016
TPA6111A2 150-mW Stereo Audio Power Amplifier
1 Features
3 Description
•
•
The TPA6111A2 is a stereo audio power amplifier
packaged in either an 8-pin SOIC or an 8-pin
PowerPAD MSOP package capable of delivering 150
mW of continuous RMS power per channel into 16-Ω
loads. Amplifier gain is externally configured by
means of two resistors per input channel and does
not require external compensation for settings of 0 to
20 dB.
1
•
•
•
•
•
150-mW Stereo Output
PC Power Supply Compatible
– Fully Specified for 3.3-V and
5-V Operation
– Operation to 2.5 V
Pop Reduction Circuitry
Internal Midrail Generation
Thermal and Short-Circuit Protection
Surface-Mount Packaging
– PowerPAD™ MSOP
– SOIC
Pin Compatible With TPA122, LM4880, and
LM4881 (SOIC)
THD+N, when driving a 16-Ω load from 5 V, is 0.03%
at 1 kHz, and less than 1% across the audio band of
20 Hz to 20 kHz. For 32-Ω loads, the THD+N is
reduced to less than 0.02% at 1 kHz, and is less than
1% across the audio band of 20 Hz to 20 kHz. For
10-kΩ loads, the THD+N performance is 0.005% at 1
kHz, and less than 0.5% across the audio band of 20
Hz to 20 kHz.
Device Information(1)
2 Applications
•
•
•
PART NUMBER
Smart Phones and Wireless Handsets
Portable Tablets
Notebook PCs and Docking Stations
TPA6111A2
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
MSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
VDD 8
RF
Audio
Input
VDD
C(S)
VDD/2
RI
2
IN 1−
3
BYPASS
6
IN 2−
CI
VO1 1
−
+
C(C)
C(BYP)
Audio
Input
RI
From Shutdown
Control Circuit
5
VO2 7
−
+
CI
SHUTDOWN
C(C)
Bias
Control
4
RF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA6111A2
SLOS313C – DECEMBER 2000 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
3
4
4
4
4
4
5
5
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
DC Electrical Characteristics, VDD = 3.3 V ...............
AC Operating Characteristics, VDD = 3.3 V ..............
DC Electrical Characteristics, VDD = 5.5 V ...............
AC Operating Characteristics, VDD = 5.5 V ..............
AC Operating Characteristics, VDD = 3.3 V...............
AC Operating Characteristics, VDD = 5 V................
Typical Characteristics ............................................
Parameter Measurement Information ................ 11
9
Detailed Description ............................................ 12
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
12
10 Application and Implementation........................ 13
10.1 Application Information.......................................... 13
10.2 Typical Application ............................................... 13
11 Power Supply Recommendations ..................... 16
12 Layout................................................................... 17
12.1 Layout Guidelines ................................................. 17
12.2 Layout Examples................................................... 17
13 Device and Documentation Support ................. 19
13.1
13.2
13.3
13.4
13.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
14 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2014) to Revision C
Page
•
Added Device Comparison table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Removed Dissipation Ratings table ....................................................................................................................................... 1
2
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SLOS313C – DECEMBER 2000 – REVISED MARCH 2016
5 Device Comparison Table
AVAILABLE OPTIONS
TPA6100A2
TPA6110A2
TPA6111A2
TPA6112A2
Headphone Channels
Stereo
Stereo
Stereo
Stereo
Output Power (W)
0.05
0.15
0.15
0.15
PSRR (dB)
72
83
83
83
Pin/Package
8-pin SOIC, 8-Pin
VSSOP
8-pin MSOP
8-pin MSOP, 8-Pin
SOIC
10-pin MSOP
6 Pin Configuration and Functions
D or DGN Package
8-Pin SOIC or MSOP
Top View
VO1
IN1−
BYPASS
GND
1
8
2
7
3
6
4
5
VDD
VO2
IN2−
SHUTDOWN
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BYPASS
3
I
Tap to voltage divider for internal mid-supply bias supply. Connect to a 0.1-µF to 1-µF low ESR capacitor
for best performance.
GND
4
I
GND is the ground connection.
IN1–
2
I
IN1– is the inverting input for channel 1.
IN2–
6
I
IN2– is the inverting input for channel 2.
SHUTDO
WN
5
I
VDD
8
I
VDD is the supply voltage terminal.
VO1
1
O
VO1 is the audio output for channel 1.
VO2
7
O
VO2 is the audio output for channel 2.
Puts the device in a low quiescent current mode when held high
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
VDD
Supply voltage
VI
Input voltage
–0.3
Continuous total power dissipation
TJ
(1)
UNIT
6
V
VDD + 0.3
V
Internally Limited
Operating junction temperature
–40
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Tstg
MAX
Storage temperature
–65
150
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
MAX
VDD
Supply voltage
2.5
5.5
V
TA
Operating free-air temperature
–40
85
°C
VIH
High-level input voltage (SHUTDOWN)
VIL
Low-level input voltage (SHUTDOWN)
60% × VDD
UNIT
V
25% × VDD
V
7.4 Thermal Information
TPA6111A2
THERMAL METRIC (1)
D (SOIC)
DGN (MSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
114.7
55.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
59.0
47.3
°C/W
RθJB
Junction-to-board thermal resistance
54.9
36.4
°C/W
ψJT
Junction-to-top characterization parameter
14.2
2.3
°C/W
ψJB
Junction-to-board characterization parameter
54.4
36.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
9.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 DC Electrical Characteristics, VDD = 3.3 V
at VDD = 3.3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VOO
Output offset voltage
PSRR
Power supply rejection ratio
VDD = 3.2 V to 3.4 V
70
IDD
Supply current
SHUTDOWN (pin 5) = 0 V
IDD(SD)
Supply current in shutdown mode
SHUTDOWN (pin 5) = VDD
Zi
Input impedance
MAX
UNIT
10
mV
1.5
3
mA
1
10
µA
dB
>1
MΩ
7.6 AC Operating Characteristics, VDD = 3.3 V
VDD = 3.3 V, TA = 25°C, RL = 16 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PO
Output power (each channel)
THD ≤ 0.1%, f = 1 kHz
THD+N
Total harmonic distortion + noise
PO = 40 mW, 20 Hz – 20 kHz
0.4%
BOM
Maximum output power BW
G = 20 dB, THD < 5%
> 20
Phase margin
Open-loop
Supply ripple rejection
f = 1 kHz, C(BYP) = 0.47 µF
71
dB
Channel/channel output separation
f = 1 kHz, PO = 40 mW
89
dB
SNR
Signal-to-noise ratio
PO = 50 mW, AV = 1
100
dB
Vn
Noise output voltage
AV = 1
11
µV(rms)
4
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60
mW
kHz
96°
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7.7 DC Electrical Characteristics, VDD = 5.5 V
at VDD = 5.5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
VOO
Output offset voltage
PSRR
Power supply rejection ratio
VDD = 4.9 V to 5.1 V
70
IDD
Supply current
SHUTDOWN (pin 5) = 0 V
IDD(SD)
Supply current in shutdown mode
SHUTDOWN (pin 5) = VDD
|IIH|
High-level input current (SHUTDOWN)
|IIL|
Low-level input current (SHUTDOWN)
Zi
Input impedance
MAX
UNIT
10
mV
1.6
3.2
mA
1
10
µA
VDD = 5.5 V, VI = VDD
1
µA
VDD = 5.5 V, VI = 0 V
1
dB
µA
>1
MΩ
7.8 AC Operating Characteristics, VDD = 5.5 V
VDD = 5 V, TA = 25°C, RL = 6 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
PO
Output power (each channel)
THD ≤ 0.1%, f = 1 kHz
THD+N
Total harmonic distortion + noise
PO = 100 mW, 20 Hz – 20 kHz
0.6%
BOM
Maximum output power BW
G = 20 dB, THD < 5%
> 20
Phase margin
Open-loop
Supply ripple rejection ratio
f = 1 kHz, C(BYP) = 0.47 µF
MAX
UNIT
150
mW
kHz
96°
61
dB
90
dB
Channel/channel output separation
f = 1 kHz, PO = 100 mW
SNR
Signal-to-noise ratio
PO = 100 mW, AV = 1
100
dB
Vn
Noise output voltage
AV = 1
11.7
µV(rms)
7.9 AC Operating Characteristics, VDD = 3.3 V
VDD = 3.3 V, TA = 25°C, RL = 32 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
PO
Output power (each channel)
THD ≤ 0.1%, f = 1 kHz
THD+N
Total harmonic distortion + noise
PO = 40 mW, 20 Hz – 20 kHz
0.4%
BOM
Maximum output power BW
G = 20 dB, THD < 2%
> 20
Phase margin
Open-loop
Supply ripple rejection
f = 1 kHz, C(BYP) = 0.47 µF
Channel/channel output separation
f = 1 kHz, PO = 25 mW
SNR
Signal-to-noise ratio
PO = 90 mW, AV = 1
Vn
Noise output voltage
AV = 1
MAX
UNIT
35
mW
kHz
96°
71
dB
75
dB
100
dB
11
µV(rms)
7.10 AC Operating Characteristics, VDD = 5 V
VDD = 5 V, TA = 25°C, RL = 32 Ω
PARAMETER
TEST CONDITIONS
PO
Output power (each channel)
THD ≤ 0.1%, f = 1 kHz
THD+N
Total harmonic distortion + noise
PO = 20 mW, 20 Hz – 20 kHz
BOM
Maximum output power BW
G = 20 dB, THD < 2%
Phase margin
Open-loop
Supply ripple rejection
f = 1 kHz, C(BYP) = 0.47 µF
MIN
TYP
MAX
UNIT
90
mW
2%
> 20
kHz
97°
61
dB
98
dB
Channel/channel output separation
f = 1 kHz, PO = 65 mW
SNR
Signal-to-noise ratio
PO = 90 mW, AV = 1
104
dB
Vn
Noise output voltage
AV = 1
11.7
µV(rms)
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7.11 Typical Characteristics
Table 1. Table of Graphs
FIGURE
vs Frequency
Figure 1, Figure 3,
Figure 5, Figure 6,
Figure 7, Figure 9,
Figure 11, Figure 13
vs Output power
Figure 2, Figure 4,
Figure 8, Figure 10,
Figure 12, Figure 14
Supply ripple rejection ratio
vs Frequency
Figure 15, Figure 16
Output noise voltage
vs Frequency
Figure 17, Figure 18
Crosstalk
vs Frequency
Figure 19-Figure 24
Shutdown attenuation
vs Frequency
Figure 25, Figure 26
Open-loop gain and phase margin
vs Frequency
Figure 27, Figure 28
Output power
vs Load resistance
Figure 29, Figure 30
IDD
Supply current
vs Supply voltage
Figure 31
SNR
Signal-to-noise ratio
vs Voltage gain
Figure 32
Power dissipation and amplifier
vs Load power
Figure 33, Figure 34
THD+N − Total Harmonic Distortion + Noise − %
10
1
10
VDD = 3.3 V,
PO = 25 mW,
CB = 1 µF,
RL = 32 Ω,
AV = −1 V/V
0.1
0.01
0.001
20
100
1k
20 kHz
20 Hz
0.1
1 kHz
0.01
0.001
10
10k 20k
50
100
PO − Output Power − mW
Figure 1. Total Harmonic Distortion + Noise vs Frequency
Figure 2. Total Harmonic Distortion + Noise vs Output
Power
THD+N − Total Harmonic Distortion + Noise − %
10
1
10
VDD = 5 V,
PO = 60 mW,
CB = 1 µF,
RL = 32 Ω,
AV = −5 V/V
AV = −1 V/V
AV = −10 V/V
0.1
0.05
0.01
0.001
20
100
1k
f − Frequency − Hz
10k 20k
1
VDD = 5 V,
RL = 32 Ω,
AV = −1 V/V,
CB = 1 µF
20 Hz
20 kHz
0.1
1 kHz
0.01
0.001
10
100
500
PO − Output Power − mW
Figure 3. Total Harmonic Distortion + Noise vs Frequency
6
1
VDD = 3.3 V,
RL = 32 Ω,
AV = −1 V/V,
CB = 1 µF
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
Vn
Total harmonic distortion + noise
THD+N − Total Harmonic Distortion + Noise − %
THD+N
Figure 4. Total Harmonic Distortion + Noise vs Output
Power
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1
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VDD = 3.3 V,
PO = 100 mW,
CB = 1 µF,
RL = 10 kΩ,
AV = −1 V/V
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
0.01
100
1k
f − Frequency − Hz
1k
f − Frequency − Hz
10k 20k
1
VDD = 3.3 V,
RL = 8 Ω,
AV = −1 V/V,
CB = 1 µF
20 Hz
20 kHz
0.1
1 kHz
0.01
100
500
Figure 8. Total Harmonic Distortion + Noise vs Output
Power
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
100
10
VDD = 5 V,
PO = 150 mW,
CB = 1 µF,
RL = 8 kΩ
AV = −5 V/V
AV = −1 V/V
0.1
0.001
20
0.01
PO − Output Power − mW
10
0.01
AV = −10 V/V
0.001
10
10k 20k
Figure 7. Total Harmonic Distortion + Noise vs Frequency
1
0.1
10
VDD = 3.3 V,
PO = 60 mW,
CB = 1 µF,
RL = 8 Ω,
AV = −1 V/V
0.1
0.001
20
AV = −1 V/V
Figure 6. Total Harmonic Distortion + Noise vs Frequency
10
1
AV = −5 V/V
0.001
20
10k 20k
Figure 5. Total Harmonic Distortion + Noise vs Frequency
1
VDD = 5 V,
PO = 100 mW,
CB = 1 µF,
RL = 10 kΩ
AV = −10 V/V
100
1k
f − Frequency − Hz
10k 20k
Figure 9. Total Harmonic Distortion + Noise vs Frequency
1
VDD = 5 V,
RL = 8 Ω,
AV = −1 V/V,
CB = 1 µF
1 kHz
20 kHz
0.1
0.01
0.001
10
20 Hz
100
PO − Output Power − mW
500
Figure 10. Total Harmonic Distortion + Noise vs Output
Power
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10
1
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VDD = 3.3 V,
PO = 40 mW,
CB = 1 µF,
RL = 16 Ω,
AV = −1 V/V
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
AV = −5 V/V
0.1
0.001
20
AV = −10 V/V
100
1k
f − Frequency − Hz
10k
100
PO − Output Power − mW
500
VDD = 5 V,
RL = 16 Ω,
AV = −1 V/V,
CB = 1 µF
20 Hz
20 kHz
1 kHz
0.1
0.01
500
100
PO − Output Power − mW
Figure 14. Total Harmonic Distortion + Noise vs Output
Power
0
0.1 µF
−10
VDD = 3.3 V,
RL = 16 Ω,
AV = −1 V/V
0.47 µF
−20
1 µF
−30
−40
−50
−60
−70
−80
Bypass = 1.65 V
−90
−100
−110
−120
K SVR − Supply Ripple Rejection Ratio − dB
0
K SVR − Supply Ripple Rejection Ratio − dB
1
0.001
10
20k
Figure 13. Total Harmonic Distortion + Noise vs Frequency
0.1 µF
−10
VDD = 5 V,
RL = 16 Ω,
AV = −1 V/V
0.47 µF
−20
1 µF
−30
−40
−50
−60
−70
−80
Bypass = 2.5 V
−90
−100
−110
−120
20
100
1k
f − Frequency − Hz
10k 20k
Figure 15. Supply Ripple Rejection Ratio vs Frequency
8
0.01
10
VDD = 5 V,
PO = 100 mW,
CB = 1 µF,
RL = 16 Ω
AV = −1 V/V
0.01
1 kHz
0.1
Figure 12. Total Harmonic Distortion + Noise vs Output
Power
10
1
20 Hz
20 kHz
0.001
10
10k 20k
Figure 11. Total Harmonic Distortion + Noise vs Frequency
1
VDD = 3.3 V,
RL =16 Ω,
AV = −1 V/V,
CB = 1 µF
20
100
1k
f − Frequency − Hz
10k
20k
Figure 16. Supply Ripple Rejection Ratio vs Frequency
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100
VDD = 3.3 V,
BW = 10 Hz to 22 kHz
RL = 16 Ω
AV = −10 V/V
AV = −1 V/V
10
V n − Output Noise Voltage − µ V(RMS)
V n − Output Noise Voltage − µ V(RMS)
100
1
100
1k
f − Frequency − Hz
VDD = 5 V,
BW = 10 Hz to 22 kHz
RL = 16 Ω,
10k 20k
20
Figure 17. Output Noise Voltage vs Frequency
−30
10k 20k
VDD = 3.3 V,
PO = 40 mW,
CB = 1 µF,
RL = 16 Ω,
AV = −1 V/V
−10
−20
−30
Crosstalk − dB
−40
−50
−60
−70
−80
−40
−50
−60
−70
−80
IN2− to VO1
−90
IN2− to VO1
−90
−100
−100
−110
20
100
1k
f − Frequency − Hz
IN1− to VO2
−110
IN1− to VO2
−120
10k 20k
20
Figure 19. Crosstalk vs Frequency
100
1k
f − Frequency − Hz
10k 20k
Figure 20. Crosstalk vs Frequency
0
0
VDD = 3.3 V,
PO = 60 mW,
CB = 1 µF,
RL = 8 Ω,
AV = −1 V/V
−10
−20
−30
−20
−30
−40
−50
−60
−70
IN2− to VO1
−80
VDD = 5 V,
PO = 60 mW,
CB = 1 µF,
RL = 32 Ω,
AV = −1 V/V
−10
Crosstalk − dB
Crosstalk − dB
1k
f − Frequency − Hz
0
VDD = 3.3 V,
PO = 25 mW,
CB = 1 µF,
RL = 32 Ω,
AV = −1 V/V
−20
−40
−50
−60
−70
−80
−90
IN2− to VO1
−90
−100
−100
IN1− to VO2
−110
−120
100
Figure 18. Output Noise Voltage vs Frequency
0
−10
Crosstalk − dB
AV = −1 V/V
10
1
20
−120
AV = −10 V/V
IN1− to VO2
−110
20
100
1k
f − Frequency − Hz
10k 20k
−120
Figure 21. Crosstalk vs Frequency
20
100
1k
f − Frequency − Hz
10k 20k
Figure 22. Crosstalk vs Frequency
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0
0
VDD = 5 V,
PO = 100 mW,
CB = 1 µF,
RL = 16 Ω,
AV = −1 V/V
−20
−30
−20
−30
−40
Crosstalk − dB
Crosstalk − dB
−40
−50
−60
−70
−80
−50
−60
−70
−90
−90
−100
−100
−120
IN1− to VO2
20
100
IN2− to VO1
−80
IN2− to VO1
−110
VDD = 5 V,
PO = 150 mW,
CB = 1 µF,
RL = 8 Ω,
AV = −1 V/V
−10
IN1− to VO2
−110
1k
f − Frequency − Hz
−120
10k 20k
20
Figure 23. Crosstalk vs Frequency
0
−10
VDD = 3.3 V,
RL = 16 Ω,
CB = 1 µF
−10
Shutdown Attenuation − dB
−20
−30
−40
−50
−60
−70
VDD = 5 V,
RL = 16 Ω,
CB = 1 µF
−30
−40
−50
−60
−70
−80
−90
−90
−100
10
−100
10
100
1k
10 k
1M
100
f − Frequency − Hz
VDD = 3.3 V
RL = 10 kΩ
100
150
100
90
Gain
60
30
Gain
0
40
−30
20
−60
−90
0
Open-Loop Gain − dB
60
VDD = 5 V
RL = 10 kΩ
90
60
60
30
Phase
0
40
−30
20
−60
−90
0
−120
−20
−150
10 k
100 k
1M
−180
10 M
−120
−20
−150
−40
1k
f − Frequency − Hz
10 k
100 k
1M
−180
10 M
f − Frequency − Hz
Figure 27. Open-Loop Gain and Phase Margin vs Frequency
10
150
120
80
Φ m − Phase Margin − Deg
80
1M
180
120
120
Phase
10 k
Figure 26. Shutdown Attenuation vs Frequency
180
120
1k
f − Frequency − Hz
Figure 25. Shutdown Attenuation vs Frequency
−40
1k
10k 20k
Figure 24. Crosstalk vs Frequency
−80
Open-Loop Gain − dB
1k
f − Frequency − Hz
0
−20
Shutdown Attenuation − dB
100
Φm − Phase Margin − Deg
−10
Figure 28. Open-Loop Gain and Phase Margin vs Frequency
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100
250
VDD = 3.3 V,
THD+N = 1%,
AV = −1 V/V
VDD = 5 V,
THD+N = 1%,
AV = −1 V/V
200
P − Output Power − mW
O
P − Output Power − mW
O
75
50
25
150
100
50
0
0
8 12 16 20 24 28 32 36 40 44 45 52 56 60 64
8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
RL − Load Resistance − Ω
RL − Load Resistance − Ω
Figure 29. Output Power vs Load Resistance
Figure 30. Output Power vs Load Resistance
120
2.5
SNR − Signal-to-Noise Ratio − dB
VDD = 5 V
I DD − Supply Current − mA
2
1.5
1
0.5
100
80
60
40
20
0
0
0.5
1
1.5 2 2.5 3 3.5 4
VDD − Supply Voltage − V
4.5
5
0
5.5
2
3
4
5
6
7
8
9
10
AV − Voltage Gain − V/V
Figure 31. Supply Current vs Supply Voltage
Figure 32. Signal-to-Noise Ratio vs Voltage Gain
80
180
VDD = 3.3 V
VDD = 5 V
Power Dissipation/Amplifier − mW
8Ω
70
Power Dissipation/Amplifier − mW
1
60
50
40
16 Ω
30
32 Ω
20
140
120
100
16 Ω
80
60
32 Ω
40
64 Ω
10
64 Ω
20
0
8Ω
160
0
0
20
40
60
80 100 120 140 160 180
0
200
Load Power − mW
20
40
60
80 100 120 140 160 180
200
Load Power − mW
Figure 33. Power Dissipation and Amplifier vs Load Power
Figure 34. Power Dissipation and Amplifier vs Load Power
8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
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9 Detailed Description
9.1 Overview
The TPA6111A2 device is a stereo audio power amplifier available in 8-pin SOIC and 8-pin MSOP packages.
This device is able to deliver 150 mW of continuous RMS power per channel into 16-Ω loads. The gain of the
amplifier is externally configured from 0 dB to 20 dB through two resistors per channel. The TPA6111A2 device
is fully specified for operation at 3.3 V and 5 V, which makes this device ideal for PC and mobile applications.
9.2 Functional Block Diagram
Left
Right
Bias Control
9.3 Feature Description
9.3.1 5-V Versus 3.3-V Operation
The TPA6111A2 was designed for operation over a supply range of 2.5 V to 5.5 V. This data sheet provides full
specifications for 5-V and 3.3-V operation because these are considered to be the two most common standard
voltages. There are no special considerations for 3.3-V versus 5-V operation as far as supply bypassing, gain
setting, or stability. The most important consideration is that of output power. Each amplifier in the TPA6111A2
can produce a maximum voltage swing of VDD – 1 V. This means, for 3.3-V operation, clipping starts to occur
when VO(PP) = 2.3 V as opposed when VO(PP) = 4 V while operating at 5 V. The reduced voltage swing
subsequently reduces maximum output power into the load before distortion begins to become significant.
9.4 Device Functional Modes
The TPA6111A2 can be put in shutdown mode when asserting SHUTDOWN pin to a logic HIGH level. While in
shutdown mode, the device is turned off, making the current consumption very low. The device exits shutdown
mode when a LOW logic level is applied to SHUTDOWN pin.
12
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
This typical connection diagram highlights the required external components and system level connections for
proper operation of the device in popular use case. Any design variation can be supported by TI through
schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion
forum for additional information.
10.2 Typical Application
VDD 8
RF
Audio
Input
VDD
C(S)
VDD/2
RI
2
IN 1−
3
BYPASS
6
IN 2−
CI
VO1 1
−
+
C(C)
C(BYP)
Audio
Input
RI
CI
From Shutdown
Control Circuit
5
VO2 7
−
+
SHUTDOWN
C(C)
4
Bias
Control
RF
Figure 35. Typical Application
10.2.1 Design Requirements
Table 2 lists the design requirements of the TPA111A2.
Table 2. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage supply range
3.3 V to 5 V
Current
2 mA
Load impedance
16 Ω
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10.2.2 Detailed Design Procedure
10.2.2.1 Gain Setting Resistors, RF and Ri
The gain for the TPA6111A2 is set by resistors RF and RI according to Equation 1.
æR ö
Gain = - ç F ÷
è RI ø
(1)
Given that the TPA6111A2 is a MOS amplifier, the input impedance is high. Consequently, input leakage
currents are not generally a concern, although noise in the circuit increases as the value of RF increases. In
addition, a certain range of RF values is required for proper start-up operation of the amplifier. Taken together, TI
recommends that the effective impedance seen by the inverting node of the amplifier be set between 5 kΩ and
20 kΩ. The effective impedance is calculated in Equation 2.
æ R R ö
Effective Impedance = - ç F I ÷
è RF + RI ø
(2)
As an example, consider an input resistance of 20 kΩ and a feedback resistor of 20 kΩ. The gain of the amplifier
would be –1 and the effective impedance at the inverting terminal would be 10 kΩ, which is within the
recommended range.
For high-performance applications, metal film resistors are recommended because they tend to have lower noise
levels than carbon resistors. For values of RF above 50 kΩ, the amplifier tends to become unstable due to a pole
formed from RF and the inherent input capacitance of the MOS input structure. For this reason, a small
compensation capacitor of approximately 5 pF must be placed in parallel with RF. In effect, this creates a lowpass filter network with the cutoff frequency defined in Equation 3.
1
fc ( lowpass ) =
2pRF CF
(3)
For example, if RF is 100 kΩ and CF is 5 pF, then fc(lowpass) is 318 kHz, which is well outside the audio range.
10.2.2.2 Input Capacitor, Ci
In the typical application, input capacitor CI is required to allow the amplifier to bias the input signal to the proper
DC level for optimum operation. In this case, Ci and RI form a high-pass filter with the corner frequency
determined in Equation 4.
1
fc ( highpass ) =
2pRI CI
(4)
The value of CI is important to consider, as it directly affects the bass (low-frequency) performance of the circuit.
Consider the example where RI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz.
Equation 4 is reconfigured as Equation 5.
1
CI =
2pRI fc ( highpass )
(5)
In this example, CI is 0.40 µF, so TI recommends choosing a value in the range of 0.47 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and
the feedback resistor (RF) to the load. This leakage current creates a DC offset voltage at the input to the
amplifier that reduces useful headroom, especially in high-gain applications (> 10). For this reason a low-leakage
tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the
capacitor must face the amplifier input in most applications, as the DC level there is held at VDD/2, which is likely
higher than the source DC level.
NOTE
It is important to confirm the capacitor polarity in the application.
14
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10.2.2.3 Power Supply Decoupling, C(S)
The TPA6111A2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF, placed as close as possible to the device VDD lead, works best. For filtering
lower frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the power
amplifier is recommended.
10.2.2.4 Midrail Bypass Capacitor, C(BYP)
The midrail bypass capacitor, C(BYP), serves several important functions. During start-up, C(BYP) determines the
rate at which the amplifier starts up. This helps to push the start-up pop noise into the subaudible range (so low it
cannot be heard). The second function is to reduce noise produced by the power supply caused by coupling into
the output drive signal. This noise is from the midrail generation circuit internal to the amplifier. The capacitor is
fed from a 230-kΩ source inside the amplifier. To keep the start-up pop as low as possible, the relationship
shown in Equation 6 must be maintained.
1
1
£
(CI RI )
C(BYP ) ´ 230 kΩ
(
)
(6)
As an example, consider a circuit where C(BYP) is 1 µF, CI is 1 µF, and RI is 20 kΩ. Inserting these values into
Equation 6 results in: 6.25 ≤ 50 which satisfies the rule. Recommended values for bypass capacitor C(BYP) are
0.1-µF to 1-µF, ceramic or tantalum low-ESR, for the best THD and noise performance.
10.2.2.5 Output Coupling Capacitor, C(C)
In the typical single-supply single-ended (SE) configuration, an output coupling capacitor (CC) is required to block
the DC bias at the output of the amplifier, thus preventing DC currents in the load. As with the input coupling
capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by
Equation 7.
1
fc =
2pRLC(C )
(7)
The main disadvantage, from a performance standpoint, is that the typically small load impedances drive the lowfrequency corner higher. Large values of C(C) are required to pass low frequencies into the load. Consider the
example where a C(C) of 68 µF is chosen and loads vary from 32 Ω to 47 kΩ. Table 3 summarizes the frequency
response characteristics of each configuration.
Table 3. Common Load Impedances vs Low Frequency
Output Characteristics in SE Mode
RL
CC
32 Ω
68 µF
LOWEST FREQUENCY
73 Hz
10,000 Ω
68 µF
0.23 Hz
47,000 Ω
68 µF
0.05 Hz
As Table 3 indicates, headphone response is adequate and drive into line level inputs (a home stereo for
example) is good.
The output coupling capacitor required in single-supply SE mode also places additional constraints on the
selection of other components in the amplifier circuit. With the rules described earlier still valid, add the following
relationship in Equation 8:
1
1
1
£
£
(CI RI ) RLC(C )
C(BYP ) ´ 230 k W
(
)
(8)
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10.2.2.6 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application. A real capacitor can be modeled simply as a
resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves
like an ideal capacitor.
10.2.3 Application Curves
The characteristics of this design are shown in Table 4 from the Typical Characteristics section.
Table 4. Table of Graphs
FIGURE
THD+N
Total harmonic distortion plus noise
vs Frequency
Figure 11
vs Output power
Figure 12
11 Power Supply Recommendations
The device is designed to operate form an input voltage supply of 3.3 V and 5 V. Therefore, the output voltage
range of power supply must be within this range and well regulated. Ti recommends placing decoupling
capacitors in every voltage source pin. Place these decoupling capacitors as close as possible to the
TPA6111A2.
16
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12 Layout
12.1 Layout Guidelines
Solder the exposed metal pad on the TPA6111A2 DGN package to the PCB. The pad on the PCB may be
grounded or may be allowed to float (not be connected to ground or power). If the pad is grounded, it must be
connected to the same ground as the GND pin (4). See the layout and mechanical drawings in Mechanical,
Packaging, and Orderable Information for proper sizing. Soldering the thermal pad improves mechanical
reliability, improves grounding of the device, and enhances thermal conductivity of the package.
12.2 Layout Examples
IN1
Vo1
4
3
2
1
Decoupling capacitor
placed as close as
possible to the device
TPA6111A2
SHUTDOWN
5
6
7
8
Vo2
IN2
Ground Plane
Top Layer Traces
Pad to Ground Plane
Thermal Pad
Via to Ground Plane
Via to Power Supply
Figure 36. TPA611A2 MSOP Layout Example
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Layout Examples (continued)
IN1
Vo1
4
3
2
1
Decoupling capacitor
placed as close as
possible to the device
TPA6111A2
SHUTDOWN
5
6
7
8
Vo2
IN2
Ground Plane
Top Layer Traces
Pad to Ground Plane
Thermal Pad
Via to Ground Plane
Via to Power Supply
Figure 37. TPA611A2 SOIC Layout Example
18
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
PowerPAD Thermally Enhanced Package Application Report (SLMA002)
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPA6111A2D
ACTIVE
SOIC
D
8
75
RoHS & Green
TPA6111A2DGN
ACTIVE
HVSSOP
DGN
8
80
TPA6111A2DGNR
ACTIVE
HVSSOP
DGN
8
TPA6111A2DGNRG4
ACTIVE
HVSSOP
DGN
TPA6111A2DR
ACTIVE
SOIC
D
NIPDAU
Level-1-260C-UNLIM
-40 to 85
6111A2
Samples
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AJA
Samples
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AJA
Samples
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJA
Samples
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
6111A2
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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