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TPA6204A1
SLOS429C – MAY 2004 – REVISED MAY 2016
TPA6204A1 1.7-W Mono Fully Differential Audio Power Amplifier
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
Designed for Wireless or Cellular Handsets and
PDAs
1.7 W Into 8 Ω From a 5-V Supply at THD = 10%
(Typical)
Low Supply Current: 4 mA Typical at 5 V
Shutdown Current: 0.01 µA Typical
Fast Start-Up With Minimal Pop
Only Three External Components
– Improved PSRR (−80 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
– Fully Differential Design Reduces RF
Rectification
– −63-dB CMRR Eliminates Two Input Coupling
Capacitors
Pin-to-Pin Compatible With TPA2005D1 and
TPA6211A1 in SON Package
Available in 3 mm × 3 mm SON Package (DRB)
Ideal for Wireless Handsets
PDAs
Notebook Computers
3 Description
The TPA6204A1 device (sometimes referred to as
TPA6204) is a 1.7-W mono fully-differential amplifier
designed to drive a speaker with at least 8-Ω
impedance while consuming only 20 mm2 total
printed-circuit board (PCB) area in most applications.
The device operates from 2.5 V to 5.5 V, drawing
only 4 mA of quiescent supply current. The
TPA6204A1 (TPA6204) is available in the spacesaving 3 mm × 3 mm SON (DRB) package.
The TPA6204A1 (TPA6204) is ideal for PDA or
smartphone applications due to features such as −80dB supply voltage rejection from 20 Hz to 2 kHz,
improved RF rectification immunity, small PCB area,
and a fast start-up with minimal pop.
Device Information(1)
PART NUMBER
TPA6204A1
PACKAGE
SON (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Circuit
VDD 6
Cs
40 kΩ
In From
DAC
− RI
4
IN−
+ RI
3
IN+
_
+
40 kΩ
2
SHUTDOWN
1
C(BYPASS)(1)
To Battery
VO+ 5
VO− 8
GND 7
Bias
Circuitry
100 kΩ
Copyright © 2016, Texas Instruments Incorporated
(1)
C(BYPASS) is optional.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA6204A1
SLOS429C – MAY 2004 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
3
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: TA = 25°C ........................
Operating Characteristics: TA = 25°C, Gain = 1 V/V
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................... 9
9.4 Device Functional Modes........................................ 12
10 Application and Implementation........................ 13
10.1 Application Information.......................................... 13
10.2 Typical Application ................................................ 13
10.3 System Examples ................................................. 15
11 Power Supply Recommendations ..................... 16
11.1 Power Supply Decoupling Capacitor .................... 17
12 Layout................................................................... 17
12.1 Layout Guidelines ................................................. 17
12.2 Layout Example .................................................... 17
13 Device and Documentation Support ................. 18
13.1
13.2
13.3
13.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
14 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
Changes from Revision B (September 2009) to Revision C
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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5 Device Comparison Table
DEVICE NUMBER
TPA6203A1
TPA6204A1
TPA6205A1 (1.8-V COMP SD)
TPA6211A1
Speaker Channels
Mono
Mono
Mono
Mono
Output Power (W)
1.25
1.7
1.25
3.1
PSRR (dB)
90
85
90
85
Pin/Package
8BGA, 8MSOP,
8SON
8SON
8BGA, 8MSOP, 8SON
8MSOP, 8SON
6 Pin Configuration and Functions
DRB Package
8-Pin SON
Top View
SHUTDOWN
1
8 V
O−
BYPASS
2
7 GND
IN+
3
6 VDD
IN−
4
5 VO+
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BYPASS
2
—
Mid-supply voltage, adding a bypass capacitor improves PSRR
IN–
4
I
Negative differential input
IN+
3
I
Positive differential input
GND
7
I
High-current ground
SHUTDOWN
1
I
Shutdown terminal (active low logic)
Thermal Pad
—
—
VDD
6
I
Power supply
VO+
5
O
Positive BTL output
VO–
8
O
Negative BTL output
Connect to ground. Thermal pad must be soldered down in all applications to properly
secure device on the PCB.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage, VDD
–0.3
6
V
Input voltage, VI
–0.3
VDD + 0.3
V
Continuous total power dissipation
See Dissipation Ratings
Operating free-air temperature, TA
–40
85
°C
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD
High-level input voltage, VIH
SHUTDOWN
Low-level input voltage, VIL
SHUTDOWN
MIN
MAX
2.5
5.5
UNIT
V
1.55
Operating free-air temperature, TA
V
–40
0.5
V
85
°C
7.4 Thermal Information
TPA6204A1
THERMAL METRIC
(1)
DRB (SON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
50.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
69.2
°C/W
RθJB
Junction-to-board thermal resistance
25.5
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
25.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics: TA = 25°C
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOS
Output offset voltage (measured
differentially)
VI = 0 V differential, Gain = 1 V/V, VDD = 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
VIC
Common mode input range
VDD = 2.5 V to 5.5 V
CMRR
Common mode rejection ratio
Low-output swing
High-output swing
MIN
TYP
MAX
–9
0.3
9
mV
–60
dB
VDD – 0.8
V
–85
0.5
VDD = 5.5 V, VIC = 0.5 V to 4.7 V
–63
–40
VDD = 2.5 V, VIC = 0.5 V to 1.7 V
–63
–40
RL = 8 Ω, VIN+ = VDD, Gain = 1
V/V, VIN− = 0 V or VIN+ = 0 V,
VIN− = VDD
RL = 8 Ω, VIN+ = VDD, Gain = 1
V/V, = 0 V or VIN− = VDD
VIN− VIN+ = 0 V
VDD = 5.5 V
0.45
VDD = 3.6 V
0.37
VDD = 2.5 V
0.26
VDD = 5.5 V
4.95
VDD = 3.6 V
VDD = 2.5 V
dB
V
0.4
3.18
2
UNIT
V
2.13
| IIH |
High-level input current,
SHUTDOWN
VDD = 5.5 V, VI = 5.8 V
58
100
µA
| IIL |
Low-level input current,
SHUTDOWN
VDD = 5.5 V, VI = −0.3 V
3
100
µA
IQ
Quiescent current
VDD = 2.5 V to 5.5 V, no load
4
6
mA
Supply current
V(SHUTDOWN) ≤ 0.5 V, VDD = 2.5 V to 5.5 V,
RL = 8 Ω
0.01
1
µA
Gain
RL = 8 Ω
40 kΩ / RI
42 kΩ / RI
V/V
I(SD)
38 kΩ / RI
Resistance from shutdown to GND
4
100
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7.6 Operating Characteristics: TA = 25°C, Gain = 1 V/V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
THD + N = 1%, f = 1 kHz,
RL = 8 Ω
PO
Output power
THD + N = 10%, f = 1 kHz,
RL = 8 Ω
THD+N
Total harmonic distortion +
noise
MIN
VDD = 5.5 V
1.36
VDD = 3.6 V
0.72
VDD = 2.5 V
0.33
VDD = 5.5 V
1.7
VDD = 3.6 V
0.85
VDD = 2.5 V
0.4
VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz
0.02%
VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz
0.02%
VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz
0.03%
kSVR
Supply ripple rejection ratio
VDD = 3.6 V, Inputs
AC-grounded with Ci = 2 µF,
V(RIPPLE) = 200 mVPP
SNR
Signal-to-noise ratio
VDD = 5 V, PO = 1 W, RL = 8 Ω
Vn
Output voltage noise
VDD = 3.6 V, f = 20 Hz to 20
kHz, Inputs AC-grounded
with Ci = 2 μF
CMRR
Common-mode rejection ratio VDD = 3.6 V VIC = 1 VPP
RF
Feedback resistance
f = 217 Hz
–80
f = 20 Hz to 20 kHz
–70
MAX
UNIT
W
W
dB
105
No weighting
15
A weighting
12
f = 217 Hz
dB
µVRMS
–65
38
Start-up time from shutdown
TYP
VDD = 3.6 V, CBYPASS = 0.1 μF
40
dB
44
27
kΩ
ms
7.7 Dissipation Ratings
PACKAGE
TA ≤ 25°C POWER
RATINGS
DERATING FACTOR
DRB
2.7 W
21.8 mW/°C
TA = 70°C POWER RATINGS TA = 85°C POWER
RATINGS
1.7 W
1.4 W
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7.8 Typical Characteristics
Table 1. Table of Graphs
FIGURE
vs Supply voltage
Figure 1
vs Load resistance
Figure 2
vs Output power
Figure 3
vs Output power
Figure 4
vs Frequency
Figure 5
vs Common-mode input voltage
Figure 6
Supply voltage rejection ratio
vs Frequency
Figure 7
GSM Power supply rejection
vs Time
Figure 8
GSM Power supply rejection
vs Frequency
Figure 9
Closed-loop gain/phase
vs Frequency
Figure 10
Open-loop gain/phase
vs Frequency
Figure 11
vs Supply voltage
Figure 12
vs Shutdown voltage
Figure 13
vs Bypass capacitor
Figure 14
PO
Output power
PD
Power dissipation
THD+N
Total harmonic distortion + noise
KSVR
IDD
Supply current
Start-up time
3.5
3.5
f = 1 kHz
Gain = 1 V/V
2.5
2
PO = 8 Ω, THD 10%
PO = 8 Ω, THD 1%
1.5
1
0.5
3.5
4
4.5
VDD − Supply Voltage − V
2
VDD = 3.6 V, THD 10%
VDD = 3.6 V, THD 1%
VDD = 2.5 V, THD 10%
1.5
VDD = 2.5 V, THD 1%
1
8
5
5V
0.6
0.4
3.6 V
0.2
0.2
0.4
0.6 0.8
1
1.2 1.4
PO − Output Power − W
18
23
28
Figure 2. Output Power vs Load Resistance
THD+N − Total Harmonic Distortion + Noise − %
8W
0
13
RL − Load Resistance − Ω
Figure 1. Output Power vs Supply Voltage
PD − Power Dissipation − W
VDD = 5 V, THD 10%
VDD = 5 V, THD 1%
0
3
0.8
1.6
1.8
Figure 3. Power Dissipation vs Output Power
6
2.5
0.5
0
2.5
0
f = 1 kHz
Gain = 1 V/V
3
Po − Output Power − W
Po − Output Power − W
3
0.06
f = 1 kHz
PO = 200 mW,
RL = 1 kHz
0.056
0.052
VDD = 2.5 V
VDD = 5 V
0.048
VDD = 3.6 V
0.044
0.04
0
1
2
3
4
VIC − Common Mode Input Voltage − V
5
Figure 4. Total Harmonic Distortion + Noise vs CommonMode Input Voltage
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5
RL = 8 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
f = 1kHz
2
1
0.5
2.5 V
0.2
3.6 V
0.1
5V
0.05
0.02
0.01
10m 20m
−20
−30
2
1
0.5
0.25 W
0.6 W
0.2
0.1 W
0.1
0.05
0.02
0.01
0.005
0.002
20
2
50
100 200
500 1k 2k
f − Frequency − Hz
5k
0
RL = 8 Ω,
C(BYPASS) = 0.47 µF,
Gain = 1 V/V,
CI = 2 µF,
Inputs ac Grounded
−50
−100
−40
−50
−60
VDD = 3.6 V
VDD = 2.5 V
−70
−80
−90
−100
20
10k 20k
Figure 6. Total Harmonic Distortion + Noise vs Frequency
VDD = 5 V
50
100 200
500 1k
2k
5k
10k 20k
VO − Output Voltage − dBV
k SVR − Supply Voltage Rejection Ratio − dB
−10
VDD = 3.6 V,
RL = 8 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
0.001
50m 100m 200m
500m 1
PO − Output Power − W
Figure 5. Total Harmonic Distortion + Noise vs Output
Power
+0
10
VDD Shown in Figure 9,
RL = 8 Ω,
CI = 2.2 µF,
Inputs Grounded
−100
−120
−140
−160
C(BYPASS) = 0.47 µF
−180
0
400
f − Frequency − Hz
Figure 7. Supply Voltage Rejection Ratio vs Frequency
−150
V − Supply Voltage − dBV
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
20
800
1200
f − Frequency − Hz
1600
2000
Figure 8. GSM Power Supply Rejection vs Frequency
300
VDD
RL = 8 Ω
CI = 2.2 µF
C(BYPASS) = 0.47 µF
VOUT
250
Start-Up Time − ms
Voltage − V
C1
Frequency
217 Hz
C1 − Duty
20%
C1 Pk−Pk
500 mV
200
150
100
50
Ch1 100 mV/div
Ch4 10 mV/div
0
0
2 ms/div
t − Time − ms
Figure 9. GSM Power Supply Rejection vs Time
0.2
0.4
0.6
0.8
C(Bypass) − Bypass Capacitor − µF
1
Figure 10. Start-Up Time vs Bypass Capacitor
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Phase
180
100
150
90
20
120
10
90
0
60
150
80
120
−20
0
−30
−30
−40
−60
−50
−60
VDD = 5 V
RL = 8 Ω
Gain = 1
−70
−80
1
10
100
1 k 10 k 100 k
f − Frequency − Hz
1M
90
60
60
Gain
50
Gain − dB
30
Phase – Degrees
Gain
−10
40
30
30
0
20
−30
10
−60
Phase
−90
0
−10
−120
−20
−120
−150
−180
−30
−150
10 M
Figure 11. Closed-Loop Gain/Phase vs Frequency
−90
−40
100
1k
10 k
100 k
f − Frequency − Hz
−180
1M
Figure 12. Open-Loop Gain/Phase vs Frequency
10
5
VDD = 5 V
TA = 125°C
4.5
VDD = 5 V
1
4
I DD − Supply Current − mA
I DD − Supply Current − mA
180
VDD = 5 V,
RL = 8 Ω
70
−
Gain – dB
30
Phase − Degrees
40
TA = 25°C
3.5
3
TA = −40°C
2.5
2
1.5
1
VDD = 3.6 V
0.1
VDD = 2.5 V
0.01
0.001
0.0001
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0.00001
VDD − Supply Voltage − V
1
2
3
4
5
Voltage on SHUTDOWN Terminal − V
Figure 13. Supply Current vs Supply Voltage
Figure 14. Supply Current vs Supply Voltage
0
8 Parameter Measurement Information
All parameters are measured according to the conditions described in Specifications.
8
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9 Detailed Description
9.1 Overview
The TPA6204A1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode
feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the
common-mode voltage at the input.
9.2 Functional Block Diagram
+
Shutdown
Bias Circuitry
9.3 Feature Description
9.3.1 Advantages of Fully Differential Amplifiers
• Input coupling capacitors not required: A fully differential amplifier with good CMRR, like the TPA6204A1,
allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has mid-supply lower
than the mid-supply of the TPA6204A1, the common-mode feedback circuit adjusts for that, and the
TPA6204A1 outputs are still biased at mid-supply of the TPA6204A1. The inputs of the TPA6204A1 can be
biased from 0.5 V to VDD − 0.8 V. If the inputs are biased outside of that range, input coupling capacitors are
required.
• Mid-supply bypass capacitor, C(BYPASS), not required: The fully differential amplifier does not require a
bypass capacitor. This is because any shift in the mid-supply affects both positive and negative channels
equally and cancels at the differential output. It is important to remember that removing the bypass capacitor
slightly worsens the kSVR. A slight decrease of kSVR, however, may be acceptable when an additional
component can be eliminated.
• Better RF-immunity: GSM handsets save power by turning on and shutting off the RF transmitter at a rate of
217 Hz. The transmitted signal is picked up on input and output traces. The fully differential amplifier cancels
the signal much better than the typical audio amplifier.
9.3.2 Fully Differential Amplifier Efficiency and Thermal Information
Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output
stage transistors. There are two components of the internal voltage drop. One is the headroom or DC voltage
drop that varies inversely to output power. The second component is due to the sinewave nature of the output.
The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The
internal voltage drop multiplied by the average value of the supply current, IDD(avg), determines the internal
power dissipation of the amplifier.
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Feature Description (continued)
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 15).
VO
V(LRMS)
IDD
IDD(avg)
Figure 15. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
Figure 13 and are the basis for calculating amplifier efficiency.
PL
Efficiency of a BTL amplifier =
PSUP
where
VL rms 2
V
V 2
, and VLRMS = P , therefore, PL = P
RL
2RL
2
PL =
where
•
•
•
•
PL = Power delivered to load
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage of BTL load
and
PSUP = VDD IDD avg and IDD avg =
1
p
pV
P
V
2V
ò0 RL sin(t ) dt = - p1 ´ RPL [cos(t )]0 = pRPL
p
where
•
•
•
•
•
PSUP = Power drawn from power supply
RL = Load resistance
VP = Peak voltage of BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
Therefore,
PSUP =
2VDDVP
pRL
(2)
Substituting PL and PSUP in Equation 5,
10
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Feature Description (continued)
VP 2
2RL
pVP
Efficiency if a BTL amplifer =
=
2VDDVP
4VDD
pRL
where
VP = 2PL RL
Therefore,
hBTL =
p 2PL RL
4VDD
where
•
ηBTL = Efficiency of a BTL amplifier
(4)
Table 2 and Table 3 employ Equation 5 to calculate efficiencies for four different output power levels. Note that
the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is
increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the
internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a
specific system is the key to proper power supply design. For a 1-W audio system with 8-Ω loads and a 5-V
supply, the maximum draw on the power supply is almost 1.6 W.
A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to
the utmost advantage when possible.
A simple formula for calculating the maximum power dissipated, PDmax, may be used for a differential output
application:
PD max =
2
2VDD
p2RL
(5)
The PDmax for a 5-V, 8-Ω system is 0.64 W.
The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor
for the 3 mm × 3 mm DRB package is shown in the dissipation rating table. Converting this to RθJA:
1
1
RqJA =
=
= 45.9 oC/W
Derating Factor
0.0218
(6)
Given RθJA, the maximum allowable junction temperature, and the maximum internal dissipation, the maximum
ambient temperature can be calculated with the following equation. The maximum recommended junction
temperature for the TPA6204A1 is 150°C.
TA Max = TJ Max - RqJA PDmax
(7)
= 150 – 45.9(0.64) = 120.6°C
Equation 7 shows that the maximum ambient temperature is 120.6°C (package limited to 85°C) at maximum
power dissipation with a 5-V supply.
Table 2 shows that for most applications no airflow is required to keep junction temperatures in the specified
range. The TPA6204A1 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. In addition, using speakers with an impedance
higher than 8-Ω dramatically increases the thermal performance by reducing the output current.
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Feature Description (continued)
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power in 3.6-V 8-Ω BTL Systems (1)
(1)
(2)
OUTPUT POWER
(W)
EFFICIENCY (%)
INTERNAL DISSIPATION
(W)
POWER FROM SUPPLY
(W)
MAX AMBIENT
TEMPERATURE (2) (°C)
0.1
27.6
0.262
0.36
85
0.2
39.0
0.312
0.51
85
0.5
61.7
0.310
0.81
85
0.6
67.6
0.288
0.89
85
DRB package
Package limited to 85°C ambient
Table 3. Efficiency and Maximum Ambient Temperature vs Output Power in 5-V 8-Ω Systems (1)
(1)
(2)
OUTPUT POWER
(W)
EFFICIENCY (%)
INTERNAL DISSIPATION
(W)
POWER FROM SUPPLY
(W)
MAX AMBIENT
TEMPERATURE (2) (°C)
0.5
44.4
0.625
1.13
85
1
62.8
0.592
1.60
85
1.36
73.3
0.496
1.86
85
1.7
81.9
0.375
2.08
85
DRB package
Package limited to 85°C ambient
9.4 Device Functional Modes
9.4.1 Shutdown Mode
The TPA6204A1 can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW level. While in
shutdown mode, the device is turned off, making the current consumption very low. The device exits shutdown
mode when a HIGH logic level is applied to SHUTDOWN pin.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPA6204A1 device starts its operation by asserting the SHUTDOWN pin to logic 1. The device enters in
shutdown mode when pulling the SHUTDOWN pin low. This typical connection diagram highlights the required
external components and system level connections for proper operation of the device in popular use case. Any
design variation can be supported by TI through schematic and layout reviews. Visit e2e.ti.com for design
assistance and join the audio amplifier discussion forum for additional information.
10.2 Typical Application
Figure 16 shows a typical circuit for the TPA6204A1 with a speaker, input resistors and supporting power supply
capacitors.
VDD 6
To Battery
Cs
40 kΩ
In From
DAC
− RI
4
IN−
+ RI
3
IN+
_
+
40 kΩ
Bias
Circuitry
1
C(BYPASS)(1)
VO− 8
GND 7
2
SHUTDOWN
VO+ 5
100 kΩ
Copyright © 2016, Texas Instruments Incorporated
(1)
C(BYPASS) is optional.
Figure 16. Typical Differential Input Application Schematic
10.2.1 Design Requirements
Table 4 lists the design parameters for this example.
Table 4. Design Parameters
PARAMETER
EXAMPLE VALUE
Power supply
2.5 V to 5 V
Current
1A
Speaker
8Ω
10.2.2 Detailed Design Procedure
10.2.2.1 Selecting Components for Resistors (RI)
The input resistor (RI) can be selected to set the gain of the amplifier according to Equation 8.
Gain = RF/RI
(8)
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The internal feedback resistors (RF) are trimmed to 40 kΩ. Resistor matching is very important in fully differential
amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors.
CMRR, PSRR, and the cancellation of the second harmonic distortion diminishes if resistor mismatch occurs.
Therefore, TI recommends using 1% tolerance resistors or better to keep the performance optimized.
10.2.2.2 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
10.2.2.2.1 Bypass Capacitor (C(BYPASS)) and Start-Up Time
The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references
and sets the output common-mode voltage to VDD/2. Adding a capacitor to this pin filters any noise into this pin
and increases kSVR. C(BYPASS) also determines the rise time of VO+ and VO− when the device is taken out of
shutdown. The larger the capacitor, the slower the rise time. Figure 10 shows the relationship of C(BYPASS) to
start-up time.
10.2.2.2.2 Input Capacitor (CI)
The TPA6204A1 does not require input coupling capacitors if using a differential input source that is biased from
0.5 V to VDD − 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors. In
the single-ended input application an input capacitor, CI, is required to allow the amplifier to bias the input signal
to the proper DC level. In this case, CI and RI form a high-pass filter with the corner frequency determined in
Equation 9.
1
fc =
2pRI CI
(9)
−3 dB
fc
Figure 17. CI and RI High-Pass Filter Cutoff Frequency
The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit.
Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 100 Hz.
Equation 9 is reconfigured as Equation 10.
1
CI =
2pRI fc
(10)
In this example, CI is 0.16 μF, so one would likely choose a value in the range of 0.22 μF to 0.47 μF. Ceramic
capacitors should be used when possible, as they are the best choice in preventing leakage current. When
polarized capacitors are used, the positive side of the capacitor must face the amplifier input in most applications,
as the DC level there is held at VDD/2, which is likely higher than the source DC level. It is important to confirm
the capacitor polarity in the application.
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10.2.2.2.3 Decoupling Capacitor (CS)
The TPA6204A1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes,
or digital hash on the line, a good low equivalent-series resistance (ESR) ceramic capacitor, typically 0.1 μF to
1 μF, placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals,
a 10-μF or greater capacitor placed near the audio power amplifier also helps, but is not required in most
applications because of the high PSRR of this device.
10.2.3 Application Curves
For application curves, see the figures listed in Table 5.
Table 5. Table of Graphs
FIGURE
PO
Output power
PD
Power dissipation
vs Supply voltage
Figure 1
vs Load resistance
Figure 2
vs Output power
Figure 3
vs Output power
Figure 4
vs Frequency
Figure 5
THD+N
Total harmonic distortion + noise
vs Common-mode input voltage
Figure 6
KSVR
Supply voltage rejection ratio
vs Frequency
Figure 7
GSM Power supply rejection
vs Time
Figure 8
GSM Power supply rejection
vs Frequency
Figure 9
Closed-loop gain/phase
vs Frequency
Figure 10
10.3 System Examples
Figure 18 through Figure 19 show application schematics for differential and single-ended inputs. Typical values
are shown in Table 6.
Table 6. Typical Component Values
COMPONENT
VALUE
RI
40 kΩ
C(BYPASS)
0.22 µF
CS
1 µF
CI
0.22 µF
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VDD 6
CI
Cs
40 kΩ
−
RI
4
IN−
+
RI
3
IN+
CI
_
+
2
VO− 8
Bias
Circuitry
1
C(BYPASS)(1)
(1)
VO+ 5
GND 7
40 kΩ
SHUTDOWN
To Battery
100 kΩ
C(BYPASS) is optional
Figure 18. Differential Input Application Schematic Optimized With Input Capacitors
VDD 6
CI
IN
4
IN−
RI
3
IN+
CI
1
C(BYPASS)(1)
(1)
(2)
_
+
VO+ 5
VO− 8
GND 7
40 kΩ
2
SHUTDOWN
Cs
40 kΩ
RI
To Battery
Bias
Circuitry
100 kΩ
C(BYPASS) is optional
Due to the fully differential design of this amplifier, the
performance is severly degraded if you connect the unused
input to BYPASS when using single-ended inputs.
(1)
C(BYPASS) is optional
(2)
Due to the fully differential design of this amplifier, the performance is severely degraded if you connect the unused
input to BYPASS when using single-ended inputs.
Figure 19. Single-Ended Input Application Schematic
11 Power Supply Recommendations
The TPA6204A1 is designed to operate from an input voltage supply range between 2.5 V and 5.5 V. Therefore,
the output voltage range of power supply must be within this range and well regulated. The current capability of
upper power must not exceed the maximum current limit of the power switch. TI recommends placing decoupling
capacitors in every voltage source pin. Place these decoupling capacitors as close as possible to the
TPA6204A1.
16
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11.1 Power Supply Decoupling Capacitor
The TPA6204A1 device requires adequate power supply decoupling to ensure a high efficiency operation with
low total harmonic distortion (THD). Place a low equivalent series resistance (ESR) ceramic capacitor, typically
0.1 µF, as close as possible of the VDD pin. This choice of capacitor and placement helps with higher frequency
transients, spikes, or digital hash on the line. Also is recommended to place a 2.2-µF to 10-µF capacitor on the
VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy faster than the board
supply, thus helping to prevent any droop in the supply voltage.
12 Layout
12.1 Layout Guidelines
It is important to keep the TPA6204A1 external components very close to the TPA6204A1 to limit noise pickup.
12.2 Layout Example
SHUTDOWN
1
8
2
7
IN +
3
6
-
4
5
IN
OUT Decoupling capacitor
placed as close as
possible to the device
OUT +
TPA6204A1
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 20. TPA6204A1 Layout Recommendation
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13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPA6204A1DRB
ACTIVE
SON
DRB
8
121
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AYJ
Samples
TPA6204A1DRBG4
ACTIVE
SON
DRB
8
121
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AYJ
Samples
TPA6204A1DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AYJ
Samples
TPA6204A1DRBRG4
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AYJ
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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