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TPA6211A1
SLOS367E – AUGUST 2003 – REVISED NOVEMBER 2015
TPA6211A1 3.1-W Mono Fully Differential Audio Power Amplifier
1 Features
3 Description
•
The TPA6211A1 is a 3.1-W mono fully-differential
amplifier designed to drive a speaker with at least 3Ω impedance while consuming only 20 mm2 total
printed-circuit board (PCB) area in most applications.
The device operates from 2.5 V to 5.5 V, drawing
only 4 mA of quiescent supply current. The
TPA6211A1 is available in the space-saving
3-mm × 3-mm SON (DRB) and the 8-pin MSOPPowerPAD™ (DGN) packages.
1
•
•
•
•
•
Designed for Wireless or Cellular Handsets and
PDAs
3.1 W Into 3 Ω From a 5-V Supply at
THD = 10% (Typ)
Low Supply Current: 4 mA Typ at 5 V
Shutdown Current: 0.01 μA Typ
Fast Startup With Minimal Pop
Only Three External Components
– Improved PSRR (–80 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
– Fully Differential Design Reduces RF
Rectification
– –63 dB CMRR Eliminates Two Input
Coupling Capacitors
Features like –80 dB supply voltage rejection from
20 Hz to 2 kHz, improved RF rectification immunity,
small PCB area, and a fast startup with minimal pop
makes the TPA6211A1 ideal for PDA and smart
phone applications.
Device Information(1)
PART NUMBER
TPA6211A1
2 Applications
•
PACKAGE
BODY SIZE (NOM)
MSOP-PowerPAD (8)
3.00 mm × 3.00 mm
SON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Ideal for Wireless Handsets, PDAs, and
Notebook Computers
Application Circuit
V DD
6
Cs
40 kΩ
RI
4
IN–
+ RI
3
IN+
–
In from
DAC
_
1
V O+
5
V O–
8
+
40 kΩ
SHUTDOWN
To Battery
GND
7
Bias
Circuitry
100 kΩ
(1)
C(BYPASS)
2
(1) C
(BYPASS)
is optional.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA6211A1
SLOS367E – AUGUST 2003 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
4
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operation Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 17
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 Typical Application ............................................... 18
10.3 System Examples ................................................. 22
11 Power Supply Recommendations ..................... 24
11.1 Power Supply Decoupling Capacitor .................... 24
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Examples................................................... 24
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2011) to Revision E
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision C (June 2008) to Revision D
•
2
Page
Deleted the Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds row from the Abs Max Table ........................ 4
Changes from Revision B (August 2004) to Revision C
•
Page
Page
Changed Storage temperature From: –65°C to 85°C To: –65°C to 150°C............................................................................ 4
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SLOS367E – AUGUST 2003 – REVISED NOVEMBER 2015
5 Device Comparison Table
DEVICE
NUMBER
SPEAKER CHANNELS
SPEAKER AMP
TYPE
OUTPUT POWER (W)
PSRR (dB)
TPA6211A1
Mono
Class-AB
3.1
85
TPA6203A1
Mono
Class-AB
1.25
90
TPA6204A1
Mono
Class-AB
1.7
85
TPA6205a1
Mono
Class-AB
1.25
90
6 Pin Configuration and Functions
DGN Package
8-Pin MSOP-PowerPAD
Top View
DRB Package
8-Pin SON With Exposed Thermal Pad
Top View
SHUTDOWN
1
8
VO–
BYPASS
2
7
GND
IN+
3
6
VDD
IN–
4
5
VO+
SHUTDOWN
1
BYPASS 2
8 VO–
7 GND
IN+ 3
6 VDD
4
5 VO+
IN–
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BYPASS
2
–
Mid-supply voltage, adding a bypass capacitor improves PSRR
GND
7
I
High-current ground
IN+
3
I
Positive differential input
IN-
4
I
Negative differential input
SHUTDOWN
1
I
Shutdown terminal (active low logic)
VDD
6
I
Power supply
VO+
5
O
Positive BTL output
VO-
8
O
Negative BTL output
Thermal Pad
–
–
Connect to ground. Thermal pad must be soldered down in all applications to properly secure
device on the PCB.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
VD
MIN
MAX
UNIT
Supply voltage
–0.3
6
V
Input voltage
–0.3
VDD + 0.3
V
D
VI
Continuous total power dissipation
See Dissipation Ratings
TA
Operating free-air temperature
–40
85
°C
TJ
Junction temperature
–40
150
°C
Tstg Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operation Conditions
MIN
VDD
Supply voltage
VIH
High-level input voltage
SHUTDOWN
VIL
Low-level input voltage
SHUTDOWN
TA
Operating free-air temperature
NOM
2.5
MAX
5.5
1.55
UNIT
V
V
–40
0.5
V
85
°C
7.4 Thermal Information
TPA6211A1
THERMAL METRIC (1)
DGN (MSOPPowerPAD™)
DRB (SON)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
62.8
49.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.9
24.8
°C/W
RθJB
Junction-to-board thermal resistance
42.1
58.8
°C/W
ψJT
Junction-to-top characterization parameter
3.3
1.7
°C/W
ψJB
Junction-to-board characterization parameter
41.9
25
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
11
8.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
VOS
Output offset voltage (measured
differentially)
VI = 0 V differential, Gain = 1 V/V, VDD = 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
VIC
Common mode input range
VDD = 2.5 V to 5.5 V
4
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MIN
TYP
MAX
-9
0.3
9
mV
–60
dB
VDD-0.8
V
–85
0.5
UNIT
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SLOS367E – AUGUST 2003 – REVISED NOVEMBER 2015
Electrical Characteristics (continued)
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5.5 V,
VIC = 0.5 V to 4.7 V
-63
–40
VDD = 2.5 V,
VIC = 0.5 V to 1.7 V
-63
–40
RL = 4 Ω,
VIN+ = VDD,
VIN+ = 0 V,
VDD = 5.5 V
Gain = 1 V/V,
VIN- = 0 V or VDD = 3.6 V
VIN- = VDD
VDD = 2.5 V
0.45
RL = 4 Ω,
VIN+ = VDD,
VIN- = VDD
VDD = 5.5 V
Gain = 1 V/V,
VIN- = 0 V or VDD = 3.6 V
VIN+ = 0 V
VDD = 2.5 V
4.95
High-output swing
| IIH |
High-level input current, shutdown
VDD = 5.5 V,
VI = 5.8 V
58
100
μA
| IIL |
Low-level input current, shutdown
VDD = 5.5 V,
VI = –0.3 V
3
100
μA
IQ
Quiescent current
VDD = 2.5 V to 5.5 V, no load
4
5
mA
Supply current
V(SHUTDOWN) ≤ 0.5 V, VDD = 2.5 V to 5.5 V,
RL = 4Ω
0.01
1
μA
Gain
RL = 4Ω
CMRR
Common mode rejection ratio
Low-output swing
I(SD)
0.37
0.26
V
0.4
3.18
2
38 kW
RI
V
2.13
40 kW
RI
Resistance from shutdown to GND
dB
42 kW
RI
100
V/V
kΩ
7.6 Operating Characteristics
TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
THD + N= 1%, f = 1 kHz, RL = 3 Ω
PO
Output power
THD + N= 1%, f = 1 kHz, RL = 4 Ω
THD + N= 1%, f = 1 kHz, RL = 8 Ω
MIN
VDD = 5 V
2.45
VDD = 3.6 V
1.22
VDD = 2.5 V
0.49
VDD = 5 V
2.22
VDD = 3.6 V
1.1
VDD = 2.5 V
0.47
VDD = 5 V
1.36
VDD = 3.6 V
0.72
VDD = 2.5 V
f = 1 kHz, RL = 3 Ω
Total harmonic distortion plus
THD+N
noise
f = 1 kHz, RL = 4 Ω
f = 1 kHz, RL = 8 Ω
TYP
MAX
W
0.33
PO = 2 W
VDD = 5 V
PO = 1 W
VDD = 3.6 V
0.05%
PO = 300 mW
VDD = 2.5 V
0.06%
PO = 1.8 W
VDD = 5 V
0.03%
PO = 0.7 W
VDD = 3.6 V
0.03%
PO = 300 mW
VDD = 2.5 V
0.04%
PO = 1 W
VDD = 5 V
0.02%
PO = 0.5 W
VDD = 3.6 V
0.02%
PO = 200 mW
VDD = 2.5 V
0.045%
0.03%
f = 217 Hz
-80
f = 20 Hz to 20 kHz
-70
kSVR
Supply ripple rejection ratio
VDD = 3.6 V, Inputs ac-grounded with
Ci = 2 μF, V(RIPPLE) = 200 mVpp
SNR
Signal-to-noise ratio
VDD = 5 V, PO = 2 W, RL = 4 Ω
Vn
Output voltage noise
VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with Ci = 2 μF
No weighting
15
A weighting
12
CMRR
Common mode rejection ratio
VDD = 3.6 V, VIC = 1 Vpp
f = 217 Hz
ZI
Input impedance
dB
105
dB
μVRMS
-65
38
40
dB
44
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UNIT
kΩ
5
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SLOS367E – AUGUST 2003 – REVISED NOVEMBER 2015
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Operating Characteristics (continued)
TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
MIN
VDD = 3.6 V, No CBYPASS
Start-up time from shutdown
VDD = 3.6 V, CBYPASS = 0.1 μF
TYP
MAX
UNIT
4
μs
27
ms
7.7 Dissipation Ratings
(1)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR (1)
TA= 70°C
POWER RATING
TA= 85°C
POWER RATING
DGN
2.13 W
17.1 mW/°C
1.36 W
1.11 W
DRB
2.7 W
21.8 mW/°C
1.7 W
1.4 W
Derating factor based on high-k board layout.
7.8 Typical Characteristics
Table 1. Table of Graphs
FIGURE
PO
Output power
PD
Power dissipation
THD+N
Total harmonic distortion + noise
vs Supply voltage
Figure 1
vs Load resistance
Figure 2
vs Output power
Figure 3, Figure 4
vs Output power
Figure 5,
Figure 6, Figure 7
vs Frequency
Figure 8,
Figure 9,
Figure 10,
Figure 11, ,
Figure 12
vs Common-mode input voltage
Figure 13
KSVR
Supply voltage rejection ratio
vs Frequency
Figure 14,
Figure 15,
Figure 16,
Figure 17
KSVR
Supply voltage rejection ratio
vs Common-mode input voltage
Figure 18
GSM Power supply rejection
vs Time
Figure 19
GSM Power supply rejection
vs Frequency
Figure 20
vs Frequency
Figure 21
vs Common-mode input voltage
Figure 22
Closed loop gain/phase
vs Frequency
Figure 23
Open loop gain/phase
vs Frequency
Figure 24
vs Supply voltage
Figure 25
vs Shutdown voltage
Figure 26
vs Bypass capacitor
Figure 27
CMRR
IDD
Common-mode rejection ratio
Supply current
Start-up time
6
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3.5
3.5
f = 1 kHz
Gain = 1 V/V
3
3
VDD = 5 V, THD 1%
PO - Output Power - W
PO - Output Power - W
PO = 4 Ω, THD 10%
PO = 3 Ω, THD 1%
2.5
PO = 4 Ω, THD 1%
2
PO = 8 Ω, THD 10%
PO = 8 Ω, THD 1%
1.5
1
0.5
2.5
VDD = 3.6 V, THD 10%
2
VDD = 3.6 V, THD 1%
1.5
VDD = 2.5 V, THD 10%
VDD = 2.5 V, THD 1%
1
0.5
0
2.5
0
3
3.5
4
VDD - Supply Voltage - V
4.5
3
5
13
18
23
28
Figure 2. Output Power vs Load Resistance
1.4
0.8
VDD = 3.6 V
4Ω
VDD = 5 V
0.7
1.2
4Ω
0.6
PD - Power Dissiaption - W
PD - Power Dissiaption - W
8
RL - Load Resistance - Ω
Figure 1. Output Power vs Supply Voltage
0.5
0.4
8Ω
0.3
0.2
0
0
0.3
0.6
0.9
1.2
PO - Output Power - W
1.5
0.8
8Ω
0.6
0.4
0
1.8
Figure 3. Power Dissipation vs Output Power
0
0.3
0.6
0.9
1.2
PO - Output Power - W
1.5
1.8
Figure 4. Power Dissipation vs Output Power
20
10
RL = 3 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
THD+N - Total Harmonic Distortion + Noise - %
5
1
0.2
0.1
THD+N - Total Harmonic Distortion + Noise - %
f = 1 kHz
Gain = 1 V/V
VDD = 5 V, THD 10%
PO = 3 Ω, THD 10%
2
1
0.5
0.2
2.5 V
3.6 V
0.1
5V
0.05
0.02
0.01
20m
50m 100m 200m
500m 1
2
3
10
5
2
1
0.5
2.5 V
0.2
3.6 V
5V
0.1
0.05
0.02
0.01
10m 20m
PO - Output Power - W
Figure 5. Total Harmonic Distortion + Noise vs Output
Power
RL = 4 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
50m 100m 200m 500m 1
PO - Output Power - W
2 3
Figure 6. Total Harmonic Distortion + Noise vs Output
Power
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10
5
10
RL = 8 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
20
2
1
2.5 V
0.5
3.6 V
0.2
5V
0.1
0.05
0.02
0.01
10m 20m
1W
0.2
0.1
2W
0.05
0.02
0.01
20
50
100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
Figure 8. Total Harmonic Distortion + Noise vs Frequency
10
VDD = 5 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
1
0.5
2 3
10
2W
0.5
1.8 W
0.2
1W
0.1
0.05
0.02
0.01
VDD = 3.6 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
0.5
1W
0.1 W
0.2
0.5 W
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.005
20
50
100 200 500 1k 2k
f - Frequency - Hz
10
1
0.5
0.4 W
0.2
0.28 W
0.1
100 200 500 1k 2k
f - Frequency - Hz
5k
10k 20k
Figure 10. Total Harmonic Distortion + Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
2
50
10
VDD = 2.5 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
20
5k 10k 20k
Figure 9. Total Harmonic Distortion + Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
2
0.005
50m 100m 200m 500m 1
PO - Output Power - W
Figure 7. Total Harmonic Distortion + Noise vs Output
Power
0.05
0.02
0.01
0.005
0.002
0.001
VDD = 3.6 V,
RL = 8 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
0.5
0.25 W
0.6 W
0.2
0.1 W
0.1
0.05
0.02
0.01
0.005
0.002
0.001
20
50
100 200
500 1k 2k
f - Frequency - Hz
5k
10k 20k
Figure 11. Total Harmonic Distortion + Noise vs Frequency
8
VDD = 5 V,
RL = 3 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
20
50
100 200
500 1k 2k
f - Frequency - Hz
5k
10k 20k
Figure 12. Total Harmonic Distortion + Noise vs Frequency
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+0
f = 1 kHz
PO = 200 mW,
RL = 1 kHz
0.058
0.056
k SVR - Supply Voltage Rejection Ratio - dB
THD+N - Total Harmonic Distortion + Noise - %
0.06
0.054
0.052
VDD = 2.5 V
0.05
VDD = 5 V
0.048
0.046
VDD = 3.6 V
0.044
0.042
0.04
0
1
2
3
4
VIC - Common Mode Input Voltage - V
-30
-40
-50
-60
VDD = 3.6 V
VDD = 2.5 V
-70
-80
-90
VDD = 5 V
-10
-20
-30
-50
VDD = 3.6 V
-70
-80
VDD = 5 V
-90
20
50
100 200
500 1k
2k
5k
100 200
-20
-30
-50
-60
-70
-80
-90
50
100 200
−40
C(BYPASS) = 0.1 µF
No C(BYPASS)
−70
−80
−90
−100
20
C(BYPASS) = 1 µF
C(BYPASS) = 0.47 µF
50
100 200
500 1k
2k
5k
10k 20k
Figure 16. Supply Ripple Rejection Ratio vs Frequency
0
RL = 4 Ω,,
CI = 2 µF,
Gain = 1 V/V,
VDD = 3.6 V
−60
500 1k
f - Frequency - Hz
−30
−50
10k 20k
-40
20
k SVR − Supply Voltage Rejection Ratio − dB
k SVR − Supply Voltage Rejection Ratio − dB
−20
5k
-100
10k 20k
Figure 15. Supply Voltage Rejection Ratio vs Frequency
−10
2k
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
CI = 2 µF,
VDD = 2.5 V to 5 V
Inputs Floating
-10
f - Frequency - Hz
+0
500 1k
Figure 14. Supply Voltage Rejection Ratio vs Frequency
+0
-40
VDD = 2.5 V
50
f - Frequency - Hz
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
Gain = 5 V/V,
CI = 2 µF,
Inputs ac Grounded
-60
20
5
k SVR - Supply Voltage Rejection Ratio - dB
+0
k SVR - Supply Voltage Rejection Ratio - dB
-20
-100
Figure 13. Total Harmonic Distortion + Noise vs Common
Mode Input Voltage
-100
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
Gain = 1 V/V,
CI = 2 µF,
Inputs ac Grounded
-10
2k
5k
10k 20k
−20
−30
−40
VDD = 2.5 V
VDD = 3.6 V
−50
−60
−70
VDD = 5 V
−80
−90
−100
f − Frequency − Hz
Figure 17. Supply Voltage Rejection Ratio vs Frequency
RL = 4 Ω,,
CI = 2 µF,
Gain = 1 V/V,
C(BYPASS) = 0.47 µF
VDD = 3.6 V,
f = 217 Hz,
Inputs ac Grounded
−10
0
1
2
3
4
DC Common Mode Input − V
5
6
Figure 18. Supply Voltage Rejection Ratio vs DC Common
Mode Input
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0
VDD
−50
−100
RL = 8 Ω
CI = 2.2 µF
VOUT
C(BYPASS) = 0.47 µF
VDD Shown in Figure 19,
RL = 8 Ω,
CI = 2.2 µF,
Inputs Grounded
−100
−140
−160
C(BYPASS) = 0.47 µF
400
t − Time − ms
Figure 19. GSM Power Supply Rejection vs Time
-20
-30
-40
VDD = 2.5 V
-60
-70
VDD = 5 V
-80
-90
50
100 200
500 1k
2k
5k
RL = 4 Ω,,
Gain = 1 V/V,
dc Change in VIC
-10
-20
-30
-40
-50
VDD = 2.5 V
-60
-80
-90
10k 20k
0
0.5
Figure 21. Common Mode Rejection Ratio vs Frequency
40
Phase
1.5
2
2.5
3
3.5
100
150
90
90
0
60
120
Gain
-10
30
-20
0
-30
-30
-40
90
60
Gain
50
Gain − dB
10
-50
VDD = 5 V
RL = 8 Ω
AV = 1
-80
10
100
1 k 10 k 100 k
f - Frequency - Hz
1M
60
40
30
30
0
20
−30
10
-60
1
5
150
70
-70
4.5
180
VDD = 5 V,
RL = 8 Ω
80
120
-60
4
Figure 22. Common-Mode Rejection Ratio vs CommonMode Input Voltage
180
Phase - Degrees
Gain - dB
20
Phase
−60
-90
0
−10
-120
−20
−120
-150
-180
−30
−150
10 M
Figure 23. Closed Loop Gain/Phase vs Frequency
10
1
VIC - Common Mode Input Voltage - V
f - Frequency - Hz
30
VDD = 5 V
VDD = 3.5 V
-70
-100
20
2000
Phase − Degrees
-50
1600
0
RL = 4 Ω,,
VIC = 200 mV Vp-p,
Gain = 1 V/V,
-10
800
1200
f − Frequency − Hz
Figure 20. GSM Power Supply Rejection vs Frequency
CMRR - Common Mode Rejection Ratio - dB
CMRR - Common-Mode Rejection Ratio - dB
+0
−150
−120
−180
0
2 ms/div
Ch1 100 mV/div
Ch4 10 mV/div
VO − Output Voltage − dBV
Voltage − V
C1
Frequency
217 Hz
C1 − Duty
20%
C1 Pk−Pk
500 mV
VDD − Supply Voltage − dBV
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−40
100
−90
1k
10 k
100 k
f − Frequency − Hz
−180
1M
Figure 24. Open Loop Gain/Phase vs Frequency
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5
VDD = 5 V
VDD = 5 V
1
4
I DD - Supply Current - mA
I DD - Supply Current - mA
4.5
10
TA = 125°C
TA = 25°C
3.5
3
TA = -40°C
2.5
2
1.5
1
VDD = 3.6 V
0.1
VDD = 2.5 V
0.01
0.001
0.0001
0.5
0
0
0.5
1
1.5 2 2.5 3 3.5 4
VDD - Supply Voltage - V
4.5
5
5.5
Figure 25. Supply Current vs Supply Voltage
0.00001
0
1
2
3
4
5
Voltage on SHUTDOWN Terminal - V
Figure 26. Supply Current vs Shutdown Voltage
300
Start-Up Time - ms
250
200
150
100
50
0
0
0.2
0.4
0.6
0.8
C(Bypass) - Bypass Capacitor - µF
1
Figure 27. Start-Up Time vs Bypass Capacitor
8 Parameter Measurement Information
All parameters are measured according to the conditions described in Specifications section.
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9 Detailed Description
9.1 Overview
The TPA6211A1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common- mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode
feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the
common- mode voltage at the input.
9.2 Functional Block Diagram
VDD
40 NŸ
IN+
+
Vo+
IN-
_
Vo-
40 NŸ
GND
BYPASS
Bias
Circuitry
SHUTDOWN
100 NŸ
9.3 Feature Description
9.3.1 Fully Differential Amplifier Efficiency and Thermal Information
Class-AB amplifiers are inefficient, primarily because of voltage drop across the output-stage transistors. The two
components of this internal voltage drop are the headroom or dc voltage drop that varies inversely to output
power, and the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS
value of the output voltage from VDD. The internal voltage drop multiplied by the average value of the supply
current, IDD(avg), determines the internal power dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 28).
12
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Feature Description (continued)
VO
V(LRMS)
IDD
IDD(avg)
Figure 28. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
The following equations are the basis for calculating amplifier efficiency.
These definitions are true for the following equations:
• ηBTL = Efficiency of a BTL amplifier
• PL = Power delivered to load
• PSUP = Power drawn from power supply
• VLRMS = RMS voltage on BTL load
• VP = Peak voltage on BTL load
• VDD = Power supply voltage
• IDDavg = Average current drawn from the power supply
Use Equation 1 to calculate the efficiency of a BTL amplifier.
PL
KBTL
PSUP
where
•
VLRMS2
RL
PL
where
–
VP
VLRMS
2
therefore
–
•
VP2
2RL
PL
PSUP
VDDIDDavg
where
–
1
S
IDDavg
S
V
³0 RPL sin(t)dt
1 VP
u
>cos(t)@0S
S RL
2VP
SRL
therefore
–
PSUP
2VDD VP
SRL
(1)
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Feature Description (continued)
Using these values, substitute PL and PSUP from Equation 1 as shown in Equation 2.
VP2
2RL
2VDD VP
SRL
KBTL
SVP
4VDD
where
•
VP
2PLRL
(2)
Therefore, ηBTL can be calculated using Equation 3.
hBTL =
p 2PLRL
4VDD
(3)
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power
OUTPUT
POWER
(W)
EFFICIENCY
(%)
INTERNAL DISSIPATION
(W)
POWER FROM SUPPLY
(W)
MAX AMBIENT TEMPERATURE
(°C)
0.5
27.2
1.34
1.84
85 (2)
(1)
5-V, 3-Ω Systems
1
38.4
1.6
2.6
76
2.45
60.2
1.62
4.07
75
3.1
67.7
1.48
4.58
82
0.5
31.4
1.09
1.59
85 (2)
1
44.4
1.25
2.25
85 (2)
2
62.8
1.18
3.18
85 (2)
2.8
74.3
0.97
3.77
85 (2)
0.5
44.4
0.625
1.13
85 (2)
1
62.8
0.592
1.6
85 (2)
1.36
73.3
0.496
1.86
85 (2)
1.7
81.9
0.375
2.08
85 (2)
5-V, 4-Ω BTL Systems
5-V, 8-Ω Systems
(1)
(2)
DRB package
Package limited to 85°C ambient
Table 2 uses Equation 3 to calculate efficiencies for four different output power levels. Note that the efficiency of
the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a
nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half power range. Calculating the efficiency for a specific system is the key to
proper power supply design. For a 2.8-W audio system with 4-Ω loads and a 5-V supply, the maximum draw on
the power supply is almost 3.8 W.
A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to
the utmost advantage when possible. Note that in Equation 3, VDD is in the denominator. This indicates that as
VDD goes down, efficiency goes up.
Use Equation 4 as a simple formula for calculating the maximum power dissipated, PDmax, for a differential output
application.
PDmax
2
2VDD
S2RL
where
14
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•
PDmax for a 5-V, 4-Ω system is 1.27 W.
(4)
The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor
for the 3 mm ×3 mm DRB package is shown in the dissipation rating table. Converting this to θJA:
1
1
TJA
45.9qC / W
Derating Factor 0.0218
(5)
Given θJA, the maximum allowable junction temperature, and the maximum internal dissipation, the maximum
ambient temperature can be calculated with Equation 6. The maximum recommended junction temperature for
the TPA6211A1 is 150°C.
TAMax TJMax TJAPDmax 150 45.9(1.27) 91.7qC
(6)
Equation 6 shows that the maximum ambient temperature is 91.7°C (package limited to 85°C ambient) at
maximum power dissipation with a 5-V supply.
Table 2 shows that for most applications no airflow is required to keep junction temperatures in the specified
range. The TPA6211A1 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. In addition, using speakers with an impedance
higher than 4-Ω dramatically increases the thermal performance by reducing the output current.
9.3.1.1 Advantages of Fully Differential Amplifiers
• Input coupling capacitors not required: A fully differential amplifier with good CMRR, like the TPA6211A1,
allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has a lower midsupply voltage than that of the TPA6211A1, the common-mode feedback circuit compensates, and the
outputs are still biased at the mid-supply point of the TPA6211A1. The inputs of the TPA6211A1 can be
biased from 0.5 V to VDD - 0.8 V. If the inputs are biased outside of that range, input coupling capacitors are
required.
• Mid-supply bypass capacitor, C(BYPASS), not required: The fully differential amplifier does not require a
bypass capacitor. Any shift in the mid-supply voltage affects both positive and negative channels equally, thus
canceling at the differential output. Removing the bypass capacitor slightly worsens power supply rejection
ratio (kSVR), but a slight decrease of kSVR may be acceptable when an additional component can be
eliminated (See Figure 17).
• Better RF-immunity: GSM handsets save power by turning on and shutting off the RF transmitter at a rate of
217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels
the signal much better than the typical audio amplifier.
• Figure 31 through Figure 38 show application schematics for differential and single-ended inputs.
9.3.1.2 Differential Output Versus Single-Ended Output
Figure 29 shows a Class-AB audio power amplifier (APA) in a fully differential configuration. The TPA6211A1
amplifier has differential outputs driving both ends of the load. One of several potential benefits to this
configuration is power to the load. The differential drive to the speaker means that as one side is slewing up, the
other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to a
ground-referenced load. Plugging 2 × VO(PP) into the power equation, where voltage is squared, yields 4× the
output power from the same supply rail and load impedance Equation 7.
VO(PP)
V(rms)
2 2
Power
V(rms)2
RL
(7)
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VDD
VO(PP)
RL
2x VO(PP)
VDD
-VO(PP)
Figure 29. Differential Output Configuration
In a typical wireless handset operating at 3.6 V, bridging raises the power into an 8-Ω speaker from a singledended (SE, ground reference) limit of 200 mW to 800 mW. This is a 6-dB improvement in sound
power—loudness that can be heard. In addition to increased power, there are frequency-response concerns.
Consider the single-supply SE configuration shown in Figure 30. A coupling capacitor (CC) is required to block
the dc-offset voltage from the load. This capacitor can be quite large (approximately 33 μF to 1000 μF) so it
tends to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting lowfrequency performance. This frequency-limiting effect is due to the high-pass filter network created with the
speaker impedance and the coupling capacitance. This is calculated with Equation 8.
1
fc
2SRL CC
(8)
For example, a 68-μF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
VDD
VO(PP)
CC
RL
VO(PP)
-3 dB
fc
Figure 30. Single-Ended Output and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4× the output power of the SE
configuration.
16
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9.4 Device Functional Modes
9.4.1 Shutdown Mode
The TPA6211A1 device can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW. While in
shutdown mode, the device output stage is turned off and set into high impedance, making the current
consumption very low. The device exits shutdown mode when a HIGH logic level is applied to SHUTDOWN pin.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPA6211A1 is a fully-differential amplifier designed to drive a speaker with at least 3-Ω impedance while
consuming only 20 mm2 total printed circuit board (PCB) area in most applications.
10.2 Typical Application
Figure 31 shows a typical application circuit for the TPA6211A1 with a speaker, input resistors and supporting
power supply decoupling capacitors.
VDD 6
To Battery
Cs
40 kΩ
In From
DAC
− RI
4
IN−
+ RI
3
IN+
_
VO− 8
+
40 kΩ
1
SHUTDOWN
C(BYPASS)(1)
2
(1)
VO+ 5
GND 7
Bias
Circuitry
100 kΩ
C(BYPASS) is optional
Figure 31. Typical Differential Input Application Schematic
Typical values are shown in Table 3.
Table 3. Typical Component Values
COMPONENT
(1)
18
VALUE
RI
40 kΩ
C(BYPASS) (1)
0.22 μF
CS
1 μF
CI
0.22 μF
C(BYPASS) is optional.
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10.2.1 Design Requirements
For this design example, use the parameters listed in Table 4.
Table 4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Power supply
2.5 V to 5.5 V
Current
4 mA to 5 mA
High > 1.55 V
Shutdown
Low < 0.5 V
3 Ω, 4 Ω, or 8 Ω
Speaker
10.2.2 Detailed Design Procedure
10.2.2.1 Selecting Components
10.2.2.1.1
Resistors (RI)
The input resistor (RI) can be selected to set the gain of the amplifier according to Equation 9.
RF
Gain
RI
(9)
The internal feedback resistors (RF) are trimmed to 40 kΩ.
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic
distortion diminishes if resistor mismatch occurs. Therefore, 1%-tolerance resistors or better are recommended to
optimize performance.
10.2.2.1.2
Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references
and sets the output common mode voltage to VDD/2. Adding a capacitor filters any noise into this pin, increasing
kSVR. C(BYPASS)also determines the rise time of VO+ and VO- when the device exits shutdown. The larger the
capacitor, the slower the rise time.
10.2.2.1.3
Input Capacitor (CI)
The TPA6211A1 does not require input coupling capacitors when driven by a differential input source biased
from 0.5 V to VDD - 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors.
In the single-ended input application, an input capacitor, CI, is required to allow the amplifier to bias the input
signal to the proper dc level. In this case, CI and RI form a high-pass filter with the corner frequency defined in
Equation 10.
1
fc
2SRICI
(10)
-3 dB
fc
Figure 32. Input Filter Cutoff Frequency
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The value of CI is an important consideration. It directly affects the bass (low frequency) performance of the
circuit. Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 100
Hz. Equation 10 is reconfigured as Equation 11.
1
CI
2SRIfc
(11)
In this example, CI is 0.16 μF, so the likely choice ranges from 0.22 μF to 0.47 μF. Ceramic capacitors are
preferred because they are the best choice in preventing leakage current. When polarized capacitors are used,
the positive side of the capacitor faces the amplifier input in most applications. The input dc level is held at VDD/2,
typically higher than the source dc level. It is important to confirm the capacitor polarity in the application.
10.2.2.1.4 Band-Pass Filter (Ra, Ca, and Ca)
It may be desirable to have signal filtering beyond the one-pole high-pass filter formed by the combination of CI
and RI. A low-pass filter may be added by placing a capacitor (CF) between the inputs and outputs, forming a
band-pass filter.
An example of when this technique might be used would be in an application where the desirable pass-band
range is between 100 Hz and 10 kHz, with a gain of 4 V/V. The following equations illustrate how the proper
values of CF and CI can be determined.
10.2.2.1.4.1 Step 1: Low-Pass Filter
fc(LPF)
1
2SRFCF
where
•
RF is the internal 40 kΩ resistor
(12)
1
2S 40k: CF
(13)
1
2S40 k: fc(LPF)
(14)
fc(LPF)
Therefore,
CF
Substitute fc(LPF) with 10 kHz and solve for CF: CF = 398 pF
10.2.2.1.4.2 Step 2: High-Pass Filter
fc(HPF)
1
2SRICI
where
•
R| is the input resistor
(15)
Because the application in this case requires a gain of 4 V/V, RI must be set to 10 kΩ.
Substitute RI in Equation 15 with 10 kΩ as shown in Equation 16.
1
fc(HPF)
2S10 k: CI
(16)
Therefore,
CI
1
2S10 k: fc(HPF)
(17)
Substitute fc(HPF) with 100 Hz and solve for CI: CI = 0.16 μF
At this point, a first-order band-pass filter has been created with the low-frequency cutoff set to 100 Hz and the
high-frequency cutoff set to 10 kHz.
20
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The process can be taken a step further by creating a second-order high-pass filter. This is accomplished by
placing a resistor (Ra) and capacitor (Ca) in the input path. It is important to note that Ra must be at least 10
times smaller than RI; otherwise its value has a noticeable effect on the gain, as Ra and RI are in series.
10.2.2.1.4.3 Step 3: Additional Low-Pass Filter
Ra must be at least 10x smaller than RI, Set Ra = 1 kΩ,
1
fc(LPF)
2SRaCa
(18)
Therefore,
Ca
1
2S 1k: fc(LPF)
(19)
Substitute fc(LPF) with 10 kHz and solving for Ca: Ca = 160 pF
Figure 33 is a bode plot for the band-pass filter in the previous example. Figure 38 shows how to configure the
TPA6211A1 as a band-pass filter.
AV
12 dB
9 dB
−20 dB/dec
+20 dB/dec
−40 dB/dec
fc(HPF) = 100 Hz
fc(LPF) = 10 kHz
f
Figure 33. Bode Plot
10.2.2.1.5
Decoupling Capacitor (CS)
The TPA6211A1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes,
or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 μF to 1
μF, placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a
10-μF or greater capacitor placed near the audio power amplifier also helps, but is not required in most
applications because of the high PSRR of this device.
10.2.2.1.6 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance
the more the real capacitor behaves like an ideal capacitor.
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10.2.3 Application Curves
3.5
3
3.5
f = 1 kHz
Gain = 1 V/V
3
VDD = 5 V, THD 1%
PO = 3 Ω, THD 1%
PO - Output Power - W
PO - Output Power - W
PO = 4 Ω, THD 10%
2.5
PO = 4 Ω, THD 1%
2
1.5
PO = 8 Ω, THD 10%
PO = 8 Ω, THD 1%
1
0.5
0
2.5
f = 1 kHz
Gain = 1 V/V
VDD = 5 V, THD 10%
PO = 3 Ω, THD 10%
2.5
VDD = 3.6 V, THD 10%
2
VDD = 3.6 V, THD 1%
1.5
VDD = 2.5 V, THD 10%
VDD = 2.5 V, THD 1%
1
0.5
0
3
3.5
4
VDD - Supply Voltage - V
4.5
3
5
8
13
18
23
28
RL - Load Resistance - Ω
Figure 34. Output Power vs Supply Voltage
Figure 35. Output Power vs Load Resistance
10.3 System Examples
VDD 6
CI
−
4
IN−
+
RI
3
IN+
CI
40 kΩ
1
SHUTDOWN
C(BYPASS)(1)
(1)
Cs
40 kΩ
RI
To Battery
_
VO+ 5
VO− 8
+
GND 7
Bias
Circuitry
100 kΩ
2
C(BYPASS) is optional
Figure 36. Differential Input Application Schematic Optimized With Input Capacitors
22
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System Examples (continued)
VDD 6
IN
RI
4
IN−
RI
3
IN+
CI
_
VO+ 5
VO− 8
+
40 kΩ
GND 7
1
SHUTDOWN
C(BYPASS)(1)
(1)
Cs
40 kΩ
CI
To Battery
Bias
Circuitry
100 kΩ
2
C(BYPASS) is optional
Figure 37. Single-Ended Input Application Schematic
CF
CF
VDD 6
Ra
−
Ca
Ra
RI
4
IN−
RI
3
IN+
CI
+
_
SHUTDOWN
C(BYPASS)(1)
VO+ 5
VO− 8
+
40 kΩ
Ca
(1)
Cs
40 kΩ
CI
To Battery
1
GND 7
Bias
Circuitry
100 kΩ
2
C(BYPASS) is optional
Figure 38. Differential Input Application Schematic With Input Bandpass Filter
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11 Power Supply Recommendations
The TPA6211A1 device is designed to operate from an input voltage supply range between 2.5 V and 5.5 V.
Therefore, the output voltage range of power supply must be within this range and well regulated. The current
capability of upper power should not exceed the maximum current limit of the power switch.
11.1 Power Supply Decoupling Capacitor
The TPA6211A1 device requires adequate power supply decoupling to ensure a high efficiency operation with
low total harmonic distortion (THD).
Place a low equivalent series resistance (ESR) ceramic capacitor, typically 0.1 uF, as close as possible of the
VDD pin. This choice of capacitor and placement helps with higher frequency transients, spikes, or digital hash
on the line. Also is recommended to place a 2.2-µF to 10-µF capacitor on the VDD supply trace. This larger
capacitor acts as a charge reservoir, providing energy faster than the board supply, thus helping to prevent any
droop in the supply voltage.
12 Layout
12.1 Layout Guidelines
Place all the external components close to the TPA6211A1 device. The input resistors need to be close to the
device input pins so noise does not couple on the high impedance nodes between the input resistors and the
input amplifier of the device. Placing the decoupling capacitors, CS and C(BYPASS), close to the TPA6211A1
device is important for the efficiency of the amplifier. Any resistance or inductance in the trace between the
device and the capacitor can cause a loss in efficiency.
12.2 Layout Examples
Bypass capacitor placed as
close as possible to the
device
SHUTDOWN
Decoupling capacitor
placed as close as possible
to the device
1
8
2
7
OUT -
0.22 µF
1 µF
IN +
3
6
IN -
4
5
OUT +
TPA6211A1
Input Resistors placed
as close as possible
to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 39. TPA6211A1 8-Pin SON (DRB) Board Layout
24
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Layout Examples (continued)
Bypass capacitor placed
as close as possible to the
device
SHUTDOWN
Decoupling capacitor
placed as close as
possible to the device
1
8
2
7
OUT -
0.22 µF
1 µF
IN +
3
6
IN -
4
5
OUT +
TPA6211A1
Input Resistors placed
as close as possible
to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 40. TPA6211A1 8-Pin MSOP-PowerPAD™ (DGN) Board Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
For the TPA6211A1 TINA-TI Spice Model, see SBOM819.
For the TPA6211A1 TINA-TI Reference Design, see SBOM820.
For the TPA6211A1EVM Gerber files, see SLOC009.
For the Speaker Amplifier Class AB/Class D Parametric Table, go to www.ti.com/lsds/ti/audio-ic/speakeramplifier-class-ab-class-d-product.page
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation, see the following:
TPA6211A1EVM User's Guide, TPA6211A1 Audio Power Amplifier Evaluation Module, SLOU162
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPA6211A1DGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AYK
Samples
TPA6211A1DGNG4
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
AYK
Samples
TPA6211A1DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AYK
Samples
TPA6211A1DGNRG4
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AYK
Samples
TPA6211A1DRB
ACTIVE
SON
DRB
8
121
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AYN
Samples
TPA6211A1DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AYN
Samples
TPA6211A1DRBRG4
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AYN
Samples
NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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