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TPA6211A1-Q1
SBOS555E – JUNE 2011 – REVISED AUGUST 2019
TPA6211A1-Q1 3.1-W Mono Fully Differential Audio Power Amplifier
1 Features
3 Description
•
The TPA6211A1-Q1 device is a 3.1-W mono fullydifferential amplifier designed to drive a speaker with
at least 3-Ω impedance while consuming only
20‑mm2 total printed-circuit board (PCB) area in most
applications. The device operates from 2.5 V to 5.5 V,
drawing only 4 mA of quiescent supply current. The
TPA6211A1-Q1 device is available in the spacesaving 8-pin HVSSOP package.
1
•
•
•
•
•
Qualified for automotive applications
– Device HBM ESD classification level 3A
– Device CDM ESD classification level C6
3.1 W into 3 Ω from a 5-V supply at
THD = 10% (typical)
Low supply current: 4 mA (typical) at 5 V
Shutdown current: 0.01 µA (typical)
Fast startup with minimal pop
Only three external components
– Improved PSRR (–80 dB) and wide supply
voltage (2.5 V to 5.5 V) for direct battery
operation
– Fully differential design reduces RF
rectification
– –63-dB CMRR Eliminates two input
coupling capacitors
The device includes features such as a –80-dB
supply voltage rejection from 20 Hz to 2 kHz,
improved RF-rectification immunity, small PCB area,
and a fast start-up with minimal pop makes the
TPA6211A1-Q1 device ideal for emergency call
applications. Additionally, the device supports lowpower needs in infotainment and cluster applications,
such as cluster chimes or driver notification.
Device Information(1)
PART NUMBER
TPA6211A1-Q1
2 Applications
•
•
•
•
Automotive audio
Emergency calls
Driver notifications
Cluster chimes
PACKAGE
HVSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Circuit
5 V DC
(1)
C(BYPASS) is optional
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA6211A1-Q1
SBOS555E – JUNE 2011 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
5
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 19
9
Power Supply Recommendations...................... 24
9.1 Power Supply Decoupling Capacitor ...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2019) to Revision E
Page
•
Changed packaging to HVSSOP............................................................................................................................................ 1
•
Changed packaging to HVSSOP............................................................................................................................................ 5
•
Changed packaging to HVSSOP.......................................................................................................................................... 25
Changes from Revision C (August 2016) to Revision D
Page
•
Deleted AEC-Q100 from the Feature: Qualified for automotive applications......................................................................... 1
•
Deleted Feature: Temperature Grade 2 ................................................................................................................................. 1
•
Changed the ESD Ratings table............................................................................................................................................. 4
Changes from Revision B (January 2014) to Revision C
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes section,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
•
Added missing Max Ambient Temperature values to Table 2.............................................................................................. 15
•
Changed 45.9 to 71.7, 1.27 to 1.25, and 91.7 to 60 in Equation 12 .................................................................................... 16
Changes from Revision A (November 2013) to Revision B
•
2
Page
Added three new equations to the DIFFERENTIAL OUTPUT VERSUS SINGLE-ENDED OUTPUT section in order
to show difference between single-ended and differential output ........................................................................................ 16
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SBOS555E – JUNE 2011 – REVISED AUGUST 2019
Changes from Original (June 2011) to Revision A
Page
•
Deleted Designed for Wireless or Cellular Handsets and PDAs from Features list............................................................... 1
•
Deleted Ordering Information table ........................................................................................................................................ 4
•
Changed reference from "equation 6" to Equation 25 in the High-Pass Filter section......................................................... 21
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SBOS555E – JUNE 2011 – REVISED AUGUST 2019
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5 Pin Configuration and Functions
DGN Package
8-Pin HVSSOP
Top View
8
1
SHUTDOWN
IN+
2 Thermal 7
Pad
3
6
IN–
4
BYPASS
5
VO–
GND
VDD
VO+
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BYPASS
2
I
Mid-supply voltage, adding a bypass capacitor improves PSRR
GND
7
I
High-current ground
IN–
4
I
Negative differential input
IN+
3
I
Positive differential input
SHUTDOWN
1
I
Shutdown pin (active low logic)
Thermal Pad
—
—
VDD
6
I
Power supply
VO+
5
O
Positive BTL output
VO–
8
O
Negative BTL output
Connect to ground. Thermal pad must be soldered down in all applications to properly secure device on
the PCB.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
MIN
MAX
UNIT
Supply voltage, VDD
–0.3
6
V
Input voltage, VI
–0.3
VDD + 0.3 V
V
Continuous total power dissipation
See Dissipation Ratings
Lead temperature 1.6 mm (1/16 Inch) from case for 10 s
260
°C
Operating free-air temperature, TA
–40
105
°C
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
DGN
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
4
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
VDD
Supply voltage
VIH
High-level input voltage
SHUTDOWN
VIL
Low-level input voltage
SHUTDOWN
TA
Operating free-air temperature
MIN
MAX
2.5
5.5
UNIT
V
1.55
V
–40
0.5
V
105
°C
6.4 Thermal Information
TPA6211A1-Q1
THERMAL METRIC (1)
DGN (HVSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
71.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.9
°C/W
RθJB
Junction-to-board thermal resistance
44.9
°C/W
ψJT
Junction-to-top characterization parameter
3.7
°C/W
ψJB
Junction-to-board characterization parameter
44.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
19.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
VOS
Output offset voltage (measured
differentially)
VI = 0-V differential, Gain = 1 V/V, VDD = 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
VIC
Common mode input range
VDD = 2.5 V to 5.5 V
CMRR
Common mode rejection ratio
Low-output swing
High-output swing
MIN
TYP
MAX
–9
0.3
9
mV
–60
dB
VDD – 0.8
V
–85
0.5
VDD = 5.5 V, VIC = 0.5 V to 4.7 V
–63
–40
VDD = 2.5 V, VIC = 0.5 V to 1.7 V
–63
–40
RL = 4 Ω, VIN+ = VDD, VIN+ = 0 V,
Gain = 1 V/V, VIN– = 0 V or VIN– = VDD
RL = 4 Ω, VIN+ = VDD, VIN– = VDD,
Gain = 1 V/V, VIN– = 0 V or VIN+ = 0 V
VDD = 5.5 V
0.45
VDD = 3.6 V
0.37
VDD = 2.5 V
0.26
VDD = 5.5 V
4.95
VDD = 3.6 V
2
dB
V
0.4
3.18
VDD = 2.5 V
UNIT
V
2.13
| IIH |
High-level input current, shutdown
VDD = 5.5 V, VI = 5.8 V
58
100
| IIL |
Low-level input current, shutdown
VDD = 5.5 V, VI = –0.3 V
3
100
µA
IQ
Quiescent current
VDD = 2.5 V to 5.5 V, no load
4
5
mA
I(SD)
Supply current
VSHUTDOWN ≤ 0.5 V, VDD = 2.5 V to 5.5 V, RL = 4 Ω
1
µA
Gain
RL = 4 Ω
Resistance from shutdown to GND
0.01
38 kW
RI
40 kW
RI
42 kW
RI
100
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µA
V/V
kΩ
5
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SBOS555E – JUNE 2011 – REVISED AUGUST 2019
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6.6 Operating Characteristics
TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
THD + N = 1%, f = 1 kHz, RL = 3 Ω
PO
THD + N = 1%, f = 1 kHz, RL = 4 Ω
Output power
THD + N = 1%, f = 1 kHz, RL = 8 Ω
MIN
2.45
VDD = 3.6 V
1.22
VDD = 2.5 V
0.49
VDD = 5 V
2.22
VDD = 3.6 V
1.1
VDD = 2.5 V
0.47
VDD = 5 V
1.36
VDD = 3.6 V
0.72
VDD = 2.5 V
THD+N Total harmonic distortion plus noise
f = 1 kHz, RL = 4 Ω
f = 1 kHz, RL = 8 Ω
UNIT
W
0.045%
PO = 1 W, VDD = 3.6 V
0.05%
PO = 300 mW, VDD = 2.5 V
0.06%
PO = 1.8 W, VDD = 5 V
0.03%
PO = 0.7 W, VDD = 3.6 V
0.03%
PO = 300 mW, VDD = 2.5 V
0.04%
PO = 1 W, VDD = 5 V
0.02%
PO = 0.5 W, VDD = 3.6 V
0.02%
PO = 200 mW, VDD = 2.5 V
0.03%
kSVR
Supply ripple rejection ratio
VDD = 3.6 V, Inputs AC-grounded with f = 217 Hz
CI = 2 µF, VRIPPLE = 200 mVpp
f = 20 Hz to 20 kHz
SNR
Signal-to-noise ratio
VDD = 5 V, PO = 2 W, RL = 4 Ω
Vn
Output voltage noise
VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs AC-grounded with CI = 2 µF
No weighting
CMRR
Common mode rejection ratio
VDD = 3.6 V, VIC = 1 Vpp
f = 217 Hz
ZI
Input impedance
–80
105
dB
–70
15
A weighting
12
dB
µVRMS
–65
38
VDD = 3.6 V, No CBYPASS
Start-up time from shutdown
MAX
0.33
PO = 2 W, VDD = 5 V
f = 1 kHz, RL = 3 Ω
TYP
VDD = 5 V
VDD = 3.6 V, CBYPASS = 0.1 µF
40
dB
44
kΩ
4
µs
27
ms
6.7 Dissipation Ratings
(1)
6
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR (1)
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGN
2.13 W
17.1 mW/°C
1.36 W
1.11 W
Derating factor based on High-k board layout.
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6.8 Typical Characteristics
Table 1. Table of Graphs
FIGURE
Output power
Power dissipation
vs Supply voltage
Figure 1
vs Load resistance
Figure 2
vs Output power
Figure 3, Figure 4
vs Output power
Total harmonic distortion + noise
vs Frequency
Figure 5, Figure 6, Figure 7
Figure 8, Figure 9, Figure 10, Figure 11, Figure 12
vs Common-mode input voltage
Figure 13
Supply voltage rejection ratio
vs Frequency
Supply voltage rejection ratio
vs Common-mode input voltage
Figure 18
GSM Power supply rejection
vs Time
Figure 19
GSM Power supply rejection
vs Frequency
Figure 20
vs Frequency
Figure 21
vs Common-mode input voltage
Figure 22
Closed loop gain/phase
vs Frequency
Figure 23
Open loop gain/phase
vs Frequency
Figure 24
vs Supply voltage
Figure 25
vs Shutdown voltage
Figure 26
vs Bypass capacitor
Figure 27
Common-mode rejection ratio
Supply current
Start-up time
Figure 14, Figure 15, Figure 16, Figure 17
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3.5
3.5
f = 1 kHz
Gain = 1 V/V
3
3
VDD = 5 V, THD 1%
PO = 3 Ω, THD 1%
PO - Output Power - W
PO - Output Power - W
PO = 4 Ω, THD 10%
2.5
PO = 4 Ω, THD 1%
2
PO = 8 Ω, THD 10%
PO = 8 Ω, THD 1%
1.5
1
0.5
2.5
VDD = 3.6 V, THD 10%
2
VDD = 3.6 V, THD 1%
1.5
VDD = 2.5 V, THD 10%
VDD = 2.5 V, THD 1%
1
0.5
0
2.5
0
3
3.5
4
VDD - Supply Voltage - V
4.5
3
5
8
Figure 1. Output Power vs Supply Voltage
23
28
Figure 2. Output Power vs Load Resistance
VDD = 3.6 V
4Ω
VDD = 5 V
1.2
4Ω
PD - Power Dissiaption - W
PD - Power Dissiaption - W
18
1.4
0.7
0.6
0.5
0.4
8Ω
0.3
0.2
0
0
0.3
0.6
0.9
1.2
PO - Output Power - W
1.5
0.8
8Ω
0.6
0.4
0
1.8
Figure 3. Power Dissipation vs Output Power
0
0.3
0.6
0.9
1.2
PO - Output Power - W
1.5
1.8
Figure 4. Power Dissipation vs Output Power
20
10
RL = 3 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
THD+N - Total Harmonic Distortion + Noise - %
5
1
0.2
0.1
THD+N - Total Harmonic Distortion + Noise - %
13
RL - Load Resistance - Ω
0.8
2
1
0.5
0.2
2.5 V
3.6 V
5V
0.1
0.05
0.02
0.01
20m
50m 100m 200m
500m 1
2
3
10
5
Figure 5. Total Harmonic Distortion + Noise
vs Output Power
RL = 4 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
2
1
0.5
2.5 V
0.2
3.6 V
5V
0.1
0.05
0.02
0.01
10m 20m
PO - Output Power - W
8
f = 1 kHz
Gain = 1 V/V
VDD = 5 V, THD 10%
PO = 3 Ω, THD 10%
50m 100m 200m 500m 1
PO - Output Power - W
2 3
Figure 6. Total Harmonic Distortion + Noise
vs Output Power
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10
5
10
RL = 8 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
20
2
1
2.5 V
0.5
3.6 V
0.2
5V
0.1
0.05
0.02
0.01
10m 20m
50m 100m 200m 500m 1
PO - Output Power - W
1
0.5
1W
0.2
0.1
2W
0.05
0.02
0.01
2 3
20
50
100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
Figure 8. Total Harmonic Distortion + Noise vs Frequency
10
10
VDD = 5 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
2
0.005
Figure 7. Total Harmonic Distortion + Noise
vs Output Power
2W
0.5
1.8 W
0.2
1W
0.1
0.05
0.02
0.01
VDD = 3.6 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
0.5
1W
0.1 W
0.2
0.5 W
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.005
20
50
100 200 500 1k 2k
f - Frequency - Hz
10
1
0.5
0.4 W
0.2
0.28 W
0.1
100 200 500 1k 2k
f - Frequency - Hz
5k
10k 20k
Figure 10. Total Harmonic Distortion + Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
2
50
10
VDD = 2.5 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
20
5k 10k 20k
Figure 9. Total Harmonic Distortion + Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
VDD = 5 V,
RL = 3 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
0.05
0.02
0.01
0.005
0.002
0.001
VDD = 3.6 V,
RL = 8 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
0.5
0.25 W
0.6 W
0.2
0.1 W
0.1
0.05
0.02
0.01
0.005
0.002
0.001
20
50
100 200
500 1k 2k
f - Frequency - Hz
5k
10k 20k
Figure 11. Total Harmonic Distortion + Noise vs Frequency
20
50
100 200
500 1k 2k
f - Frequency - Hz
5k
10k 20k
Figure 12. Total Harmonic Distortion + Noise vs Frequency
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+0
f = 1 kHz
PO = 200 mW,
RL = 1 kHz
0.058
0.056
k SVR - Supply Voltage Rejection Ratio - dB
THD+N - Total Harmonic Distortion + Noise - %
0.06
0.054
0.052
VDD = 2.5 V
0.05
VDD = 5 V
0.048
0.046
VDD = 3.6 V
0.044
0.042
0.04
1
2
3
4
VIC - Common Mode Input Voltage - V
5
-40
-50
-60
-10
-20
-30
-70
-80
-90
-40
-50
-60
VDD = 3.6 V
-70
-80
VDD = 5 V
-90
20
50
100 200
VDD = 5 V
20
+0
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
Gain = 5 V/V,
CI = 2 µF,
Inputs ac Grounded
VDD = 2.5 V
VDD = 3.6 V
VDD = 2.5 V
500 1k
2k
5k
50
100 200
-20
-30
-50
-60
-70
-80
-90
20
50
100 200
−40
C(BYPASS) = 0.1 µF
−60
No C(BYPASS)
−70
−80
−90
−100
20
C(BYPASS) = 1 µF
C(BYPASS) = 0.47 µF
50
100 200
500 1k
2k
5k
10k 20k
2k
5k
10k 20k
RL = 4 Ω,,
CI = 2 µF,
Gain = 1 V/V,
C(BYPASS) = 0.47 µF
VDD = 3.6 V,
f = 217 Hz,
Inputs ac Grounded
−10
−20
−30
−40
VDD = 2.5 V
VDD = 3.6 V
−50
−60
−70
VDD = 5 V
−80
−90
−100
0
f − Frequency − Hz
Figure 17. Supply Voltage Rejection Ratio vs Frequency
10
500 1k
Figure 16. Supply Ripple Rejection Ratio vs Frequency
0
RL = 4 Ω,,
CI = 2 µF,
Gain = 1 V/V,
VDD = 3.6 V
−30
−50
10k 20k
f - Frequency - Hz
k SVR − Supply Voltage Rejection Ratio − dB
k SVR − Supply Voltage Rejection Ratio − dB
−20
5k
-40
-100
10k 20k
Figure 15. Supply Voltage Rejection Ratio vs Frequency
−10
2k
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
CI = 2 µF,
VDD = 2.5 V to 5 V
Inputs Floating
-10
f - Frequency - Hz
+0
500 1k
Figure 14. Supply Voltage Rejection Ratio vs Frequency
k SVR - Supply Voltage Rejection Ratio - dB
+0
k SVR - Supply Voltage Rejection Ratio - dB
-30
f - Frequency - Hz
Figure 13. Total Harmonic Distortion + Noise
vs Common-Mode Input Voltage
-100
-20
-100
0
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
Gain = 1 V/V,
CI = 2 µF,
Inputs ac Grounded
-10
1
2
3
4
DC Common Mode Input − V
5
6
Figure 18. Supply Voltage Rejection Ratio
vs DC Common-Mode Input
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0
VDD
−50
−100
RL = 8 Ω
CI = 2.2 µF
VOUT
C(BYPASS) = 0.47 µF
−160
C(BYPASS) = 0.47 µF
400
-30
-40
VDD = 2.5 V
-60
-70
VDD = 5 V
-80
-90
50
100 200
-20
-30
-40
-50
500 1k
2k
5k
VDD = 2.5 V
-60
-80
-90
10k 20k
0
0.5
1
1.5
2
2.5
3
3.5
40
Phase
20
180
100
150
90
10
150
80
120
30
-20
0
-30
-30
-40
-60
-50
VDD = 5 V
RL = 8 Ω
AV = 1
-80
1
10
100
1 k 10 k 100 k
f - Frequency - Hz
1M
90
60
Gain
50
Gain − dB
60
Gain
-10
Phase - Degrees
90
-70
5
180
VDD = 5 V,
RL = 8 Ω
70
-60
4.5
Figure 22. Common-Mode Rejection Ratio
vs Common-Mode Input Voltage
120
0
4
VIC - Common Mode Input Voltage - V
Figure 21. Common-Mode Rejection Ratio vs Frequency
Gain - dB
VDD = 5 V
VDD = 3.5 V
-70
f - Frequency - Hz
30
2000
RL = 4 Ω,,
Gain = 1 V/V,
dc Change in VIC
-10
-100
20
1600
0
-20
-50
800
1200
f − Frequency − Hz
Figure 20. GSM Power Supply Rejection vs Frequency
CMRR - Common Mode Rejection Ratio - dB
CMRR - Common-Mode Rejection Ratio - dB
−140
t − Time − ms
RL = 4 Ω,,
VIC = 200 mV Vp-p,
Gain = 1 V/V,
-10
−150
−120
−180
0
2 ms/div
Figure 19. GSM Power Supply Rejection vs Time
+0
VDD Shown in Figure 19,
RL = 8 Ω,
CI = 2.2 µF,
Inputs Grounded
−100
60
40
30
30
0
20
−30
10
Phase
−60
Phase − Degrees
Ch1 100 mV/div
Ch4 10 mV/div
VO − Output Voltage − dBV
Voltage − V
C1
Frequency
217 Hz
C1 − Duty
20%
C1 Pk−Pk
500 mV
VDD − Supply Voltage − dBV
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-90
0
−10
-120
−20
−120
-150
-180
−30
−150
10 M
Figure 23. Closed Loop Gain/Phase vs Frequency
−40
100
−90
1k
10 k
100 k
f − Frequency − Hz
−180
1M
Figure 24. Open Loop Gain/Phase vs Frequency
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5
10
VDD = 5 V
TA = 125°C
4.5
VDD = 5 V
1
4
I DD - Supply Current - mA
I DD - Supply Current - mA
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TA = 25°C
3.5
3
TA = -40°C
2.5
2
1.5
1
VDD = 3.6 V
0.1
VDD = 2.5 V
0.01
0.001
0.0001
0.5
0
0
0.5
1
1.5 2 2.5 3 3.5 4
VDD - Supply Voltage - V
4.5
5
5.5
Figure 25. Supply Current vs Supply Voltage
0.00001
0
1
2
3
4
5
Voltage on SHUTDOWN Terminal - V
Figure 26. Supply Current vs Shutdown Voltage
300
Start-Up Time - ms
250
200
150
100
50
0
0
0.2
0.4
0.6
0.8
C(Bypass) - Bypass Capacitor - µF
1
Figure 27. Start-up Time vs Bypass Capacitor
12
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7 Detailed Description
7.1 Overview
The TPA6211A1-Q1 device is a fully differential amplifier with differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that
the amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode
feedback ensures that the common-mode voltage at the output is biased around VDD / 2 regardless of the
common-mode voltage at the input.
7.2 Functional Block Diagram
5 V DC
(1)
C(BYPASS) is optional
7.3 Feature Description
7.3.1 Advantages of Fully Differential Amplifiers
Input coupling capacitors are not required. A fully differential amplifier with good CMRR, such as the
TPA6211A1-Q1 device, allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC
has a lower mid-supply voltage than that of the TPA6211A1-Q1 device, the common-mode feedback circuit
compensates, and the outputs are still biased at the mid-supply point of the TPA6211A1-Q1 device. The inputs of
the TPA6211A1-Q1 device can be biased from 0.5 V to VDD – 0.8 V. If the inputs are biased outside of that
range, input coupling capacitors are required.
A Mid-supply bypass capacitor, CBYPASS, is not required. The fully differential amplifier does not require a bypass
capacitor. Any shift in the mid-supply voltage affects both positive and negative channels equally, thus canceling
at the differential output. Removing the bypass capacitor slightly worsens power supply rejection ratio (kSVR), but
a slight decrease of kSVR can be acceptable when an additional component can be eliminated (see Figure 17).
The RF-immunity is improved. A fully differential amplifier cancels the noise from RF disturbances much better
than the typical audio amplifier.
7.3.2 Fully Differential Amplifier Efficiency and Thermal Information
Class-AB amplifiers are inefficient, primarily because of voltage drop across the output-stage transistors. The two
components of this internal voltage drop are the headroom or DC voltage drop that varies inversely to output
power, and the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS
value of the output voltage from VDD. The internal voltage drop multiplied by the average value of the supply
current, IDD(avg), determines the internal power dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 28).
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Feature Description (continued)
VO
V(LRMS)
IDD
IDD(avg)
Figure 28. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL the current waveform is a full-wave rectified waveform. This means RMS conversion
factors are different. Keep in mind that for most of the waveform both the push and pull transistors are not on at
the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply
for half the waveform. Equation 1 to Equation 10 are the basis for calculating amplifier efficiency.
P
hBTL = L
PSUP
where
•
•
•
ŋBTL is the efficiency of a BTL amplifier
PL is the power delivered to load
PSUP is the power drawn from power supply
(1)
PL is calculated with Equation 2, and VLRMS is calculated with Equation 3.
PL =
VLRMS 2
RL
where
•
•
VLRMS = RMS voltage on BTL load
RL is load resistance
VLRMS =
(2)
VP
2
where
•
VP is peak voltage on BTL load
(3)
Therefore, PL can be given as Equation 4.
PL =
VP 2
2 ´ RL
(4)
PSUP is calculated with Equation 5.
PSUP = VDD × IDDavg
where
•
•
VDD is power supply voltge
IDDavg is average current drawn from the power supply
(5)
IDDavg is calculated with Equation 6.
14
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Feature Description (continued)
IDDavg =
1
p
p
V
1
V
2´ V
ò0 RPL ´ sin(t) ´ dt = – p ´ RPL ´ cos(t)0 = p ´ RPL
p
(6)
Therefore, PSUP can be given as Equation 7.
2 ´ VDD ´ VP
PSUP =
p ´ RL
(7)
Substituting for PL and PSUP, Equation 1 becomes Equation 8
hBTL =
VP 2
2´R L
2´ VDD ´ VP
p´R L
=
p ´ VP
4 ´ VDD
(8)
VP is calculated with Equation 9.
VP = 2 ´ PL ´ R L
(9)
And substituting for VP, ŋBTL can be calculated with Equation 10
hBTL =
p 2 ´ PL ´ R L
4 ´ VDD
(10)
A simple formula for calculating the maximum power dissipated (PDmax) can be used for a differential output
application:
PDmax
2
2VDD
S2RL
(11)
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power
OUTPUT POWER
EFFICIENCY
INTERNAL DISSIPATION
POWER FROM SUPPLY
MAX AMBIENT TEMPERATURE
0.5 W
27.2%
1.34 W
1.84 W
54°C
5-V, 3-Ω SYSTEMS
1W
38.4%
1.6 W
2.6 W
35°C
2.45 W
60.2%
1.62 W
4.07 W
34°C
3.1 W
67.7%
1.48 W
4.58 W
44°C
0.5 W
31.4%
1.09 W
1.59 W
72°C
1W
44.4%
1.25 W
2.25 W
60°C
2W
62.8%
1.18 W
3.18 W
65°C
2.8 W
74.3%
0.97 W
3.77 W
80°C
0.5 W
44.4%
0.625 W
1.13 W
105°C (limited by maximum ambient
temperature specification)
1W
62.8%
0.592 W
1.6 W
105°C (limited by maximum ambient
temperature specification)
1.36 W
73.3%
0.496 W
1.86 W
105°C (limited by maximum ambient
temperature specification)
1.7 W
81.9%
0.375 W
2.08 W
105°C (limited by maximum ambient
temperature specification)
5-V, 4-Ω BTL SYSTEMS
5-V, 8-Ω SYSTEMS
Equation 10 is used to calculate efficiencies for four different output power levels, see Table 2. The efficiency of
the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a
nearly flat internal power dissipation over the normal operating range. The internal dissipation at full output power
is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power
supply design. For a 2.8-W audio system with 4-Ω loads and a 5-V supply, the maximum draw on the power
supply is almost 3.8 W.
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A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to
the utmost advantage when possible. In Equation 10, VDD is in the denominator. This indicates that as VDD goes
down, efficiency goes up.
The maximum ambient temperature depends on the heat sinking ability of the PCB system. Given RθJA (junctionto-ambient thermal resistance), the maximum allowable junction temperature, and the internal dissipation at 1-W
output power with a 4-Ohm load, the maximum ambient temperature can be calculated with Equation 12. The
maximum recommended junction temperature for the TPA6211A1-Q1 device is 150°C.
TA (Max) = TJ (Max) - R qJA ´ PD = 150 - 71.7 ´ 1.25 = 60°C
(12)
Equation 12 shows that the maximum ambient temperature is 60°C at 1-W output power and 4-Ohm load with a
5-V supply.
Table 2 shows that the thermal performance must be considered when using a Class-AB amplifier to keep
junction temperatures in the specified range. The TPA6211A1-Q1 device is designed with thermal protection that
turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. In addition,
using speakers with an impedance higher than 4 Ω dramatically increases the thermal performance by reducing
the output current.
7.3.3 Differential Output Versus Single-Ended Output
Figure 29 shows a Class-AB audio power amplifier (APA) in a fully differential configuration. The TPA6211A1-Q1
amplifier has differential outputs driving both ends of the load. One of several potential benefits to this
configuration is power to the load. The differential drive to the speaker means that as one side is slewing up, the
other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to a
ground-referenced load. Plugging 2 × VO(PP) into the power equation (Equation 13) yields four-times the output
power (as the voltage is squared) from the same supply rail and load impedance (see Equation 15 and
Equation 16).
VO(PP)
V(rms)
2 2
Power
V(rms)2
RL
(13)
2
Power(S -E) =
V(rms)2
RL
æ VO(PP) ö
ç
÷
VO(PP)2
2 2 ø
=è
=
RL
8RL
(14)
2
Power(Diff ) =
V(rms)
RL
2
æ 2 ´ VO(PP) ö
ç
÷
2
2 2
ø = VO(PP)
=è
RL
2RL
Power(Diff ) = 4 ´ Power(S -E)
16
(15)
(16)
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VDD
VO(PP)
RL
2x VO(PP)
VDD
-VO(PP)
Figure 29. Differential Output Configuration
In a typical automotive application operating at 5 V, bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 390 mW to 1.56 W. This is a 6-dB improvement in sound power, or
loudness of the sound. In addition to increased power, there are frequency-response concerns. Consider the
single-supply SE configuration shown in Figure 30. A coupling capacitor (CC) is required to block the DC-offset
voltage from the load. This capacitor can be quite large (approximately 33 µF to 1000 µF) so it tends to be
expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency
performance. This frequency-limiting effect is due to the high-pass filter network created with the speaker
impedance and the coupling capacitance. This is calculated with Equation 17.
1
fc
2SRL CC
(17)
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the DC offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
VDD
VO(PP)
CC
RL
VO(PP)
-3 dB
fc
Figure 30. Single-Ended Output and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces four-times the output power of the
SE configuration.
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7.4 Device Functional Modes
The TPA6211A1-Q1 device can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW.
While in shutdown mode, the device output stage is turned off and set into high impedance, making the current
consumption very low. The device exits shutdown mode when a HIGH logic level is applied to SHUTDOWN pin.
18
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPA6211A1-Q1 is a fully-differential amplifier designed to drive a speaker with at least 3-Ω impedance while
consuming only 20-mm2 total printed-circuit board (PCB) area in most applications.
8.2 Typical Applications
Figure 31 shows a typical application circuit for the TPA6211A1-Q1 with a speaker, input resistors, and
supporting power supply decoupling capacitors.
8.2.1 Typical Differential Input Application
5 V DC
Copyright © 2016, Texas Instruments Incorporated
(1)
C(BYPASS) is optional
Figure 31. Typical Differential Input Application Schematic
Typical values are shown in Table 3.
Table 3. Typical Component Values
COMPONENT
(1)
VALUE
RI
40 kΩ
CBYPASS (1)
0.22 µF
CS
1 µF
CI
0.22 µF
CBYPASS is optional.
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 4 as the input parameters.
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Table 4. Design Parameters
PARAMETER
EXAMPLE VALUE
Power supply voltage
2.5 V to 5.5 V
Current
4 mA to 5 mA
High > 1.55 V
Shutdown
Low < 0.5 V
3 Ω, 4 Ω, or 8 Ω
Speaker
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Resistors (RI)
The input resistor (RI) can be selected to set the gain of the amplifier according to Equation 18.
RF
Gain
RI
(18)
The internal feedback resistors (RF) are trimmed to 40 kΩ.
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic
distortion diminishes if resistor mismatch occurs. Therefore, TI recommends 1%-tolerance resistors or better to
optimize performance.
8.2.1.2.2 Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references
and sets the output common mode voltage to VDD / 2. Adding a capacitor filters any noise into this pin, increasing
kSVR. CBYPASS also determines the rise time of VO+ and VO– when the device exits shutdown. The larger the
capacitor, the slower the rise time.
8.2.1.2.3 Input Capacitor (CI)
The TPA6211A1-Q1 device does not require input coupling capacitors when driven by a differential input source
biased from 0.5 V to VDD – 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling
capacitors.
In the single-ended input application, an input capacitor (CI) is required to allow the amplifier to bias the input
signal to the proper DC level. In this case, CI and RI form a high-pass filter with the corner frequency defined in
Equation 19.
1
fc
2SRICI
(19)
-3 dB
fc
Figure 32. Input Filter Cutoff Frequency
The value of CI is an important consideration, as it directly affects the bass (low frequency) performance of the
circuit. Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to
100 Hz. Equation 19 is reconfigured as Equation 20.
20
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1
2SRIfc
(20)
In this example, CI is 0.16 µF, so the likely choice ranges from 0.22 µF to 0.47 µF. TI recommends the use of
ceramic capacitors because they are the best choice in preventing leakage current. When polarized capacitors
are used, the positive side of the capacitor faces the amplifier input in most applications. The input DC level is
held at VDD / 2, typically higher than the source DC level. Confirming the capacitor polarity in the application is
important.
8.2.1.2.4 Band-Pass Filter (RI, CI, and CF)
Having signal filtering beyond the one-pole high-pass filter formed by the combination of CI and RI can be
desirable. A low-pass filter can be added by placing a capacitor (CF) between the inputs and outputs, forming a
band-pass filter.
An example of when this technique might be used would be in an application where the desirable pass-band
range is between 100 Hz and 10 kHz, with a gain of 4 V/V. Equation 21 to Equation 28 allow the proper values of
CF and CI to be determined.
8.2.1.2.4.1 Step 1: Low-Pass Filter
fc(LPF)
1
2SRFCF
(21)
fc(LPF)
1
2S 40k: CF
(22)
1
2S40 k: fc(LPF)
(23)
Therefore,
CF
Substituting 10 kHz for fc(LPF) and solving for CF:
CF = 398 pF
(24)
8.2.1.2.4.2 Step 2: High-Pass Filter
fc(HPF)
1
2SRICI
(25)
Because the application in this case requires a gain of 4 V/V, RI must be set to 10 kΩ.
Substituting RI into Equation 25.
1
fc(HPF)
2S10 k: CI
(26)
Therefore,
CI
1
2S10 k: fc(HPF)
(27)
Substituting 100 Hz for fc(HPF) and solving for CI:
CI = 0.16 µF
(28)
At this point, a first-order band-pass filter has been created with the low-frequency cutoff set to 100 Hz and the
high-frequency cutoff set to 10 kHz.
The process can be taken a step further by creating a second-order high-pass filter. This is accomplished by
placing a resistor (Ra) and capacitor (Ca) in the input path. Ra must be at least 10 times smaller than RI;
otherwise its value has a noticeable effect on the gain, as Ra and RI are in series.
8.2.1.2.4.3 Step 3: Additional Low-Pass Filter
Ra must be at least ten-times smaller than RI. Set Ra = 1 kΩ
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1
2SRaCa
(29)
1
2S 1k: fc(LPF)
(30)
fc(LPF)
Therefore,
Ca
Substituting 10 kHz for fc(LPF) and solving for Ca:
Ca = 160 pF
(31)
Figure 33 is a bode plot for the band-pass filter in the previous example. Figure 38 shows how to configure the
TPA6211A1-Q1 device as a band-pass filter.
AV
12 dB
9 dB
−20 dB/dec
+20 dB/dec
−40 dB/dec
fc(HPF) = 100 Hz
fc(LPF) = 10 kHz
f
Figure 33. Bode Plot
8.2.1.2.5 Decoupling Capacitor (CS)
The TPA6211A1-Q1 device is a high-performance CMOS audio amplifier that requires adequate power supply
decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling
also prevents oscillations for long lead lengths between the amplifier and the speaker. For higher frequency
transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor,
typically 0.1 µF to 1 µF, placed as close as possible to the device VDD lead works best. For filtering lower
frequency noise signals, a 10-µF or greater capacitor placed near the audio power amplifier also helps, but is not
required in most applications because of the high PSRR of this device.
8.2.1.2.6 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
22
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8.2.1.3 Application Curves
3.5
3.5
PO = 8 :, THD 1%
PO = 8 :, THD 10%
PO = 4 :, THD 1%
PO = 3 :, THD 1%
PO = 4 :, THD 10%
PO = 3 :, THD 10%
2.5
VDD = 2.5 V, THD 1%
VDD = 2.5 V, THD 10%
VDD = 3.6 V, THD 1%
VDD = 3.6 V, THD 10%
VDD = 5 V, THD 1%
VDD = 5 V, THD 10%
3
Output Power (W)
Output Power (W)
3
2
1.5
1
2.5
2
1.5
1
0.5
0.5
0
2.5
0
3
3.5
4
Supply Voltage (V)
4.5
5
3
8
D002
Figure 34. Output Power vs Supply Voltage
13
18
23
Load Resistance (:)
28
33
D001
Figure 35. Output Power vs Load Resistance
8.2.2 Other Application Circuits
Figure 36, Figure 37, and Figure 38 show example circuits using the TPA6211A1-Q1 device.
5 V DC
C
C
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C(BYPASS) is optional
Figure 36. Differential Input Application Schematic Optimized With Input Capacitors
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5 V DC
C
C
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C(BYPASS) is optional
Figure 37. Single-Ended Input Application Schematic
CF
CF
5 V DC
C
C
C
C
Copyright © 2016, Texas Instruments Incorporated
(1)
C(BYPASS) is optional
Figure 38. Differential Input Application Schematic With Input Bandpass Filter
9 Power Supply Recommendations
The TPA6211A1-Q1 device is designed to operate from an input voltage supply range between 2.5 V and 5.5 V.
Therefore, the output voltage range of power supply must be within this range and well regulated. The current
capability of upper power should not exceed the maximum current limit of the power switch.
24
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TPA6211A1-Q1
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SBOS555E – JUNE 2011 – REVISED AUGUST 2019
9.1 Power Supply Decoupling Capacitor
The TPA6211A1-Q1 device requires adequate power supply decoupling to ensure a high efficiency operation
with low total harmonic distortion (THD). Place a low equivalent series resistance (ESR) ceramic capacitor,
typically 0.1 µF, as close as possible of the VDD pin. This choice of capacitor and placement helps with higher
frequency transients, spikes, or digital hash on the line. TI recommends placing a 2.2-µF to 10-µF capacitor on
the VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy faster than the board
supply, thus helping to prevent any droop in the supply voltage.
10 Layout
10.1 Layout Guidelines
Place all the external components close to the TPA6211A1-Q1 device. The input resistors need to be close to
the device input pins so noise does not couple on the high impedance nodes between the input resistors and the
input amplifier of the device. Placing the decoupling capacitors, CS and CBYPASS, close to the TPA6211A1-Q1
device is important for the efficiency of the amplifier. Any resistance or inductance in the trace between the
device and the capacitor can cause a loss in efficiency.
10.2 Layout Example
Bypass capacitor placed
as close as possible to the
device
Decoupling capacitor
placed as close as
possible to the device
1
8
2
7
IN +
3
6
IN -
4
5
SHUTDOWN
OUT -
0.22 µF
1 µF
OUT +
TPA6211A1
Input Resistors placed
as close as possible
to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 39. TPA6211A1-Q1 8-Pin HVSSOP (DGN) Board Layout
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TPA6211A1-Q1
SBOS555E – JUNE 2011 – REVISED AUGUST 2019
www.ti.com
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPA6211A1TDGNRQ1
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
6211Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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