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TPD12S015A
SLLSE74D – JUNE 2011 – REVISED JULY 2016
TPD12S015A HDMI Companion Chip With Step-Up DC-DC, I2C Level Shifter, and HighSpeed ESD Clamps
1 Features
3 Description
•
The TPD12S015A device is an integrated HDMI
companion chip solution. This device offers 8 low
capacitance ESD clamps allowing HDMI 1.3/1.4 data
rates. The 0.4-mm pitch DSBGA package pin
mapping matches the HDMI Type D or Type C
connectors. The integrated ESD clamps in monolithic
silicon technology provide good matching between
each differential signal pair. This provides an
advantage over discrete ESD clamp solutions where
variations between ESD clamps degrade the
differential signal quality.
Conforms to HDMI Compliance Tests Without Any
External Components
Supports HDMI 1.3 and HDMI 1.4 Data Rate
Match Class D and Class C Pin Mapping
Excellent Matching Capacitance (0.05 pF) in Each
Differential Signal Pair
Internal Boost Converter to Generate 5 V From a
2.3-V to 5.5-V Battery Voltage
Auto-Direction Sensing Level Shifting in the CEC,
SDA, and SCL Paths
IEC 61000-4-2 (Level 4) System Level ESD
Compliance
Improved Drop-In Replacement for the Industry
Popular TPD12S015A
Industrial Temperature Range: –40°C to 85°C
1
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
Smart Phones
eBooks
Tablet PCs
Digital Camcorders
Portable Game Consoles
Digital Still Cameras
SCL_B or SDA_B Buffers of TPD12S015A Driving
Long HDMI Cable (750-pF Load)
DDC Line Switching
6
TPD12S015A DDC Translator
5
FET Switch Translator
Voltage (V)
4
The TPD12S015A provides a regulated 5-V output
(5VOUT) for sourcing the HDMI power line. The
5VOUT pin supplies minimum 55 mA to the HDMI
receiver while meeting the HDMI 5VOUT
specifications. The 5VOUT and the hot plug detect
(HPD) circuitry are independent of the LS_OE control
signal; they are controlled by the CT_CP_HPD pin.
This independent control enables the detection
scheme (5VOUT + HPD) to be active before enabling
the HDMI link. The HPD_B port has a glitch filter to
avoid false detection due to the bouncing while
inserting the HDMI plug.
There are three noninverting bidirectional translation
circuits for the SDA, SCL, and CEC lines; they are
controlled by the LS_OE control signal. Each have a
common power rail (VCCA) on the A side from 1.1 V
to 3.6 V. On the B side, the SCL_B and SDA_B each
have an internal 1.75-kΩ pullup connected to the
regulated 5-V rail (5VOUT). The SCL and SDA pins
meet the I2C specifications, and drive at least 750-pF
loads which exceeds the HDMI cable specification.
An LDO generates a 3.3-V internal rail for the CEC
line operation when LS_OE = H & CT_CP_HPD = H.
The CEC_B pin has a 26-kΩ pullup to this internal
3.3-V rail.
The TPD12S015A provides IEC61000-4-2 (Level 4)
ESD protection. This device is offered in a spacesaving 1.56-mm × 2.76-mm DSBGA package.
3
2
1
Device Information(1)
0
4.0
5.0
6.0
7.0
Time (uSec)
8.0
9.0
10.0
PART NUMBER
TPD12S015A
PACKAGE
DSBGA (28)
BODY SIZE (NOM)
1.56 mm × 2.76 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD12S015A
SLLSE74D – JUNE 2011 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
CEC Line (x_A & x_B ports); VCCA = 1.8 V .............
6.23 Switching Characteristics: Voltage Level Shifter:
HPD Line (x_A & x_B ports); VCCA = 1.8 V .............
6.24 Switching Characteristics: Voltage Level Shifter:
SCL, SDA Lines (x_A & x_B ports); VCCA = 2.5 V...
6.25 Switching Characteristics: Voltage Level Shifter:
CEC Line (x_A & x_B ports); VCCA = 2.5 V .............
6.26 Switching Characteristics: Voltage Level Shifter:
HPD Line (x_A & x_B ports); VCCA = 2.5 V .............
6.27 Switching Characteristics: Voltage Level Shifter:
SCL, SDA Lines (x_A & x_B ports); VCCA = 3.3 V...
6.28 Switching Characteristics: Voltage Level Shifter:
CEC Line (x_A & x_B ports); VCCA = 3.3 V .............
6.29 Switching Characteristics: Voltage Level Shifter:
HPD Line (x_A & x_B ports); VCCA = 3.3 V .............
6.30 Typical Characteristics ..........................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics: ICC ................................... 6
Electrical Characteristics: High-Speed ESD Lines:
Dx, CLK...................................................................... 6
6.7 Electrical Characteristics: DC-DC Converter ............ 7
6.8 Electrical Characteristics: Passive Components....... 7
6.9 Electrical Characteristics: Voltage Level Shifter: SCL,
SDA Lines (x_A/x_B Ports)........................................ 8
6.10 Electrical Characteristics: Voltage Level Shifter:
CEC Lines (x_A/x_B Ports)........................................ 8
6.11 Electrical Characteristics: Voltage Level Shifter:
HPD Line (x_A/x_B Ports) ......................................... 9
6.12 Electrical Characteristics: LS_OE, CT_CP_HPD.... 9
6.13 Electrical Characteristics: I/O Capacitance............. 9
6.14 Switching Characteristics ........................................ 9
6.15 Switching Characteristics: Voltage Level Shifter:
SCL, SDA Lines (x_A & x_B ports); VCCA = 1.2 V..... 9
6.16 Switching Characteristics: Voltage Level Shifter:
CEC Line (x_A & x_B ports); VCCA = 1.2 V ............. 10
6.17 Switching Characteristics: Voltage Level Shifter:
HPD Line (x_A & x_B ports); VCCA = 1.2 V ............. 10
6.18 Switching Characteristics: Voltage Level Shifter:
SCL, SDA Lines (x_A & x_B ports); VCCA = 1.5 V... 10
6.19 Switching Characteristics: Voltage Level Shifter:
CEC Line (x_A & x_B ports); VCCA = 1.5 V ............. 10
6.20 Switching Characteristics: Voltage Level Shifter:
HPD Line (x_A & x_B ports); VCCA = 1.5 V ............. 11
6.21 Switching Characteristics: Voltage Level Shifter:
SCL, SDA Lines (x_A & x_B ports); VCCA = 1.8 V... 11
6.22 Switching Characteristics: Voltage Level Shifter:
7
8
11
12
12
12
12
13
13
14
Parameter Measurement Information ................ 17
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
9
11
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
21
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Applications ................................................ 22
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2013) to Revision D
•
Page
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
Changes from Revision B (April 2012) to Revision C
Page
•
Added Power Derating Curve............................................................................................................................................... 14
•
Changed Board Layout section ............................................................................................................................................ 27
2
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SLLSE74D – JUNE 2011 – REVISED JULY 2016
5 Pin Configuration and Functions
YFF Package
28-Pin DSBGA
Top View
1
2
3
4
A
B
C
D
E
F
G
For package dimensions, see Mechanical, Packaging, and Orderable Information
Pin Functions
PIN
TYPE
DESCRIPTION
F1
Power Out
DC-DC output. The 5-V power pin can supply 55 mA of regulated current to the HDMI
receiver. Separate DC-DC converter control pin CT_CP_HPD disables the DC-DC converter
when operating at low-power mode.
CEC_A
B2
I/O
System-side CEC bus I/O. This pin is bidirectional and referenced to VCCA.
CEC_B
D3
I/O
HDMI-side CEC bus I/O. This pin is bidirectional and referenced to the 3.3-V internal supply.
CLK–, CLK+
G4, F4
ESD
High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential data
lines
CT_CP_HPD
D1
Control
DC-DC Enable. Enables the DC-DC converter and HPD circuitry when CT_CP_HPD = H.
The CT_CP_HPD is referenced to VCCA.
E4, D4,
C4, B4,
A4, A3
ESD
High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential data
lines
E1
I
B3, C3,
D2, E2
Ground
HPD_A
C2
O
System-side output for the hot plug detect. This pin is unidirectional and is referenced to
VCCA.
HPD_B
G3
I
HDMI-side input for the hot plug detect. This pin is unidirectional and is referenced to
5VOUT.
LS_OE
A1
Control
Level shifter enable. This pin is referenced to VCCA. Enables SCL, SDA, CEC level shifters,
and LDO when LS_OE = H.
PGND
G1
Analog
Ground
DC-DC converter ground. This pin must be tied externally to the system GND plane. See
Layout Guidelines.
SCL_A
B1
I/O
System-side input and output for I2C bus. This pin is bidirectional and referenced to VCCA.
SCL_B
E3
I/O
HDMI-side input and output for I2C bus. This pin is bidirectional and referenced to 5VOUT.
SDA_A
C1
I/O
System-side input and output for I2C bus. This pin is bidirectional and referenced to VCCA.
SDA_B
F3
I/O
HDMI-side input and output for I2C bus. This pin is bidirectional and referenced to 5VOUT.
SW
F2
I
VBAT
G2
Supply
Battery supply. This voltage is typically 2.3 V to 5.5 V
VCCA
A2
Supply
System-side supply. this voltage is typically 1.2 V to 3.3 V from the core microcontroller.
NAME
NO.
5VOUT
D0–, D0+,
D1– , D1+,
D2–, D2+
FB
GND
Feedback input. This pin is a feedback control pin for the DC-DC converter. It must be
connected to 5VOUT.
Device ground
Switch input. This pin is the inductor input for the DC-DC converter.
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Table 1. YFF Package Pin Mapping
1
2
3
4
LS_OE
VCCA
D2+
D2–
B
SCL_A
CEC_A
GND
D1+
C
SDA_A
HPD_A
GND
D1–
D
CT_CP_HPD
GND
CEC_B
D0+
E
FB
GND
SCL_B
D0–
F
5VOUT
SW
SDA_B
CLK+
G
PGND
VBAT
HPD_B
CLK–
A
4
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SLLSE74D – JUNE 2011 – REVISED JULY 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCCA
Supply voltage
VBAT
Supply voltage
VI
Input voltage
Voltage range applied to any output in the highimpedance or power-off state (2)
VO
MAX
UNIT
4
V
–0.3
6
HPD_B, Dx, CLKx
–0.3
6
CT_CP_HPD, LS_OE
–0.3
4
SCL_A, SDA_A, CEC_A, HPD_A
–0.3
4
SCL_B, SDA_B, CEC_B
–0.3
6
–0.3
VCCA + 0.3
Voltage range applied to any output in the high or SCL_A, SDA_A, CEC_A, HPD_A
low state (3)
SCL_B, SDA_B, CEC_B
–0.3
V
V
6
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IOUTMAX
Continuous current through 5VOUT or GND
±100
mA
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
V(ESD)
Electrostatic
discharge
±2500
Pins E4, D4, B4, C4, D2+,
D2-, F4, G4, E3, F3, D3,
G3, F1, and E1
±15000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
V
±1000
Pins D4, E4, B4, C4, A3,
A4, F4, G4, E3, F3, D3,
G3, F1, E1
IEC 61000-4-2 contact discharge
(1)
(2)
All pins except B1, C1, B2,
D1, A1, and A2
±8000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over recommended operating free-air temperature range (unless otherwise noted)
SUPPLY
MIN
NOM
MAX
UNIT
VCCA
Supply voltage
1.1
3.6
V
VBAT
Supply voltage
2.3
5.5
V
0.7 × VCCA
VCCA
SCL_A, SDA_A,
CEC_A
VCCA = 1.1 V to 3.6 V
CT_CP_HPD, LS_OE
VIH
High-level input voltage
SCL_B, SDA_B
CEC_B
5VOUT = 5 V
HPD_B
(1)
1
3.6
0.7 ×
5VOUT
5VOUT
0.7 × 3.3
(internal) (1)
3.3
(internal) (1)
2
5VOUT
V
'3.3V (internal)' is an internally generated voltage node for the CEC_B output buffer supply reference. An LDO generates this 3.3 V from
5VOUT when LS_OE = H & CT_CP_HPD = H.
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Recommended Operating Conditions (continued)
over recommended operating free-air temperature range (unless otherwise noted)
SUPPLY
SCL_A, SDA_A,
CEC_A
MIN
VCCA = 1.1 V to 3.6 V
CT_CP_HPD, LS_OE
VIL
Low-level input voltage
SCL_B, SDA_B
5VOUT = 5 V
CEC_B
HPD_B
VILC
Low-level input voltage
(contention)
SCL_A, SDA_A,
CEC_A
VCCA = 1.1 V to 3.6 V
VOL –
VILC
Delta between VOL and VILC
SCL_A, SDA_A,
CEC_A
VCCA = 1.1 V to 3.6 V
TA
Operating free-air temperature
NOM
MAX
UNIT
0.082 ×
VCCA
0
0
0.4
0
0.3 ×
5VOUT
0
0.3 × 3.3V
(internal) (1)
0
0.8
0
0.065 ×
VCCA
V
V
0.1 ×
VCCA
V
–40
85
°C
6.4 Thermal Information
TPD12S015A
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
63
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.4
°C/W
RθJB
Junction-to-board thermal resistance
9.2
°C/W
ψJT
Junction-to-top characterization parameter
1.6
°C/W
ψJB
Junction-to-board characterization parameter
9.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: ICC
PARAMETER
ICCA
ICCB
Standby
Active
PIN
TEST CONDITIONS
VCCA
MIN
TYP
MAX
2
I/O = High
15
UNIT
µA
Standby
CT_CP_HPD=L, LS_OE=L, HPD_B=L
2
DC-DC and HPD active
CT_CP_HPD=H, LS_OE=L, HPD_B=L
30
50
CT_CP_HPD=H LS_OE=H, HPD_B=L,
I/O =H
225
300
TYP
MAX
0.01
0.5
µA
0.85
1
V
VBAT
DC-DC, HPD, DDC, CEC
active
µA
6.6 Electrical Characteristics: High-Speed ESD Lines: Dx, CLK
PARAMETER
TEST CONDITIONS
IOFF
Current from IO port to supply
pins
VCC = 0 V, VIO = 3.3 V
VDL
Diode forward voltage
ID = 8 mA,
Lower clamp diode
RDYN
Dynamic resistance
I=1A
D, CLK
CIO
IO capacitance
VCC = 5 V
VIO = 2.5 V
VBR
Break-down voltage
IIO = 1 mA
6
MIN
D, CLK
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9
UNIT
1
Ω
1.3
pF
12
V
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6.7 Electrical Characteristics: DC-DC Converter
PARAMETER
VBAT
TEST CONDITIONS
Input voltage range
5VOUT
V
5
5.13
V
Total output voltage accuracy
Includes voltage references, DC load / line
regulations, transient load / line regulations,
ripple, process, and temperature
4.8
5
5.3
V
20
mVp-p
Output voltage ripple, loaded
IO = 65 mA
Internal operating frequency
VBAT = 2.3 V to 5.5 V
Start-up time
From CT_CP_HPD input to 5-V power output
90% point
Output current
VBAT = 2.3 V to 5.5 V
Reverse leakage current VO
CT_CP_HPD= L, VO = 5.5 V
Leakage current from battery to
VO
CT_CP_HPD= L
Undervoltage lockout threshold
VBATOVT
UNIT
5.5
4.9
F_clk
VBATUVT
MAX
Includes voltage references, DC load / line
regulations, process and temperature
VO_Ripple
IO
TYP
2.3
Total DC output voltage
TOVA
tstart
MIN
Overvoltage lockout threshold
3.5
MHz
300
55
µs
mA
2.5
µA
5
µA
Falling
2
V
Rising
2.1
V
Falling
5.9
V
Rising
6
V
Line transient response
VBAT = 3.6 V, a pulse of 217-Hz 600 mVp-p
square wave, IO = 20/65 mA
Load transient response
VBAT = 3.6 V, IO = 5 to 65 mA, pulse of 10 µs, tr
= tf = 0.1 µs
IDD (idle)
Power supply current from VBAT IO = 0 mA
to DC-DC, enabled, unloaded
IDD (disabled)
Power supply current from
VBAT, DC-DC Disabled,
Unloaded
IDD(system
±25
±50
50
mVpk
50
µA
VBAT = 2.3 V to 5.5 V, IO = 0 mA, CT_CP_HPD
Low
2
µA
Power supply current from
VBAT, VCCA =0 V
VCCA = 0 V
5
µA
I_inrush
(startup)
Inrush current, average over
T_startup time
VBAT = 2.3 V to 5.5 V, IO = 65 mA
100
mA
TSD
Thermal shutdown
Increasing junction temperature
140
°C
ΔTSD
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
ISC
Short-circuit current limit from
output
5-Ω short to GND
off)
30
mVpk
500
mA
TYP
UNIT
6.8 Electrical Characteristics: Passive Components
PARAMETER
LIN
External inductor, 0805 footprint
1
µH
CIN
Input capacitor, 0603 footprint
4.7
µF
COUT
Output capacitor, 0603 footprint
4.7
µF
CVCCA
Input capacitor, 0402 footprint
0.1
µF
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6.9 Electrical Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A/x_B Ports)
TA = –40°C to 85°C unless otherwise specified
PARAMETER
VOHA
TEST CONDITIONS
IOH = –10 μA, VI = VIH
VOLA
IOL = 10 μA,
VOHB
IOH = –10 μA, VI = VIH
VOLB
VI = VIL
IOL = 3 mA,
VCCA
MIN
1.1 V to 3.6 V
TYP
VCCA × 0.8
1.1 V to 3.6 V
V
VI = VIL
0.4
1.1 V to 3.6 V
40
SDx_B (VT+ – VT–)
1.1 V to 3.6 V
400
RPU
(Internal pullup)
IOZ
V
5VOUT × 0.9
SDx_A (VT+ – VT–)
IOFF
UNIT
V
VCCA ×
0.17
ΔVT
hysteresis
IPULLUPAC
MAX
SCL_A,
SDA_A,
Internal pullup connected
to VCCA rail
10
SCL_B,
SDA_B,
Internal pullup connected
to 5-V rail
1.75
Transient boosted
pullup current (rise
time accelerator)
SCL_B,
SDA_B,
Internal pullup connected
to 5-V rail
15
A port
VCCA = 0 V, VI or VO = 0 to 3.6 V
B port
5VOUT = 0 V, VI or VO = 0 to 5.5 V
B port
A port
V
mV
kΩ
mA
0V
±5
0 V to 3.6 V
±5
VO = VCCO or GND
1.1 V to 3.6 V
±5
VI = VCCI or GND
1.1 V to 3.6 V
±5
µA
µA
6.10 Electrical Characteristics: Voltage Level Shifter: CEC Lines (x_A/x_B Ports)
TA = –40°C to 85°C unless otherwise specified
PARAMETER
TEST CONDITIONS
VCCA
MIN
VOHA
IOH = –10 µA, VI = VIH
1.1 V to
3.6 V
VOLA
IOL = 10 µA,
1.1 V to
3.6 V
VOHB
IOH = –10 µA, VI = VIH
VOLB
IOL = 3 mA,
VI = VIL
8
V
0.4
CEC_B (VT+ – VT–)
1.1 V to
3.6 V
300
V
mV
CEC_A
Internal pullup connected
to VCCA rail
10
CEC_B
Internal pullup connected
to internal 3.3-V rail
26
VCCA = 0 V, VI or VO = 0 to 3.6 V
V
3.3V
(internal) ×
0.9 (1)
40
kΩ
0V
±5
0 V to 3.6
V
B port
5VOUT = 0 V, VI or VO = 0 to 5.5 V
B port
VO = VCCO or GND
1.1 V to
3.6 V
±5
A port
VI = VCCI or GND
1.1 V to
3.6 V
±5
IOZ
(1)
VCCA ×
0.17
CEC_A (VT+ – VT–)
A port
IOFF
UNIT
V
1.1 V to
3.6 V
(Internal pullup)
MAX
VCCA × 0.8
VI = VIL
ΔVT hysteresis
RPU
TYP
±1.8
µA
µA
3.3 V (internal) is an internally generated voltage node for the CEC_B output buffer supply reference. An LDO generates this 3.3 V from
5VOUT when LS_OE = H & CT_CP_HPD = H
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6.11 Electrical Characteristics: Voltage Level Shifter: HPD Line (x_A/x_B Ports)
TA = –40°C to 85°C unless otherwise specified
PARAMETER
TEST CONDITIONS
VCCA
MIN
VOHA
IOH = –3 mA,
VI = VIH
1.1 V to 3.6 V
VOLA
IOL = 3 mA,
VI = VIL
1.1 V to 3.6 V
ΔVT
hysteresis
HPD_B (VT+ – VT–)
RPD
(Internal pulldown)
HPD_B,
IOZ
A port
VI = VCCI or GND
TYP
MAX
UNIT
VCCA × 0.7
V
0.4
1.1 V to 3.6 V
Internal pulldown
connected to GND
V
200
mV
11
kΩ
3.6 V
±5
µA
6.12 Electrical Characteristics: LS_OE, CT_CP_HPD
TA = –40°C to 85°C unless otherwise specified
PARAMETER
TEST CONDITIONS
II
VCCA
VI = VCCA or GND
MIN
TYP
1.1 V to 3.6 V
MAX
UNIT
±12
µA
6.13 Electrical Characteristics: I/O Capacitance
TA = –40°C to 85°C unless otherwise specified
PARAMETER
CI
Control
inputs
TEST CONDITIONS
VCCA
MIN
TYP
MAX
UNIT
VI = 1.89 V or GND, AC input = 30 mV(p-p); f = 10 MHz
1.1 V to 3.6
V
7.1
pF
A port
VO = 1.89 V or GND, AC input = 30 mV(p-p); f = 10 MHz,
CT_CP_HPD = H, LS_OE = L
1.1 V to 3.6
V
8.3
pF
B port
VO = 5 V or GND, AC input = 30 mV(p-p); f = 10 MHz,
CT_CP_HPD = H, LS_OE = L
3.3 V
15
pF
SCL_B,
SDA_B
VBAT = 0 V, Vbias = 2.5 V; AC input = 3.5 V(p-p); f = 100 kHz
0V
20
pF
VBAT = 0 V, Vbias = 1.65 V; AC input = 2.5 V(p-p); f = 100
kHz
0V
20
pF
3.3 V
20
pF
CIO
CIO
CEC_B
VBAT = 3.3 V, Vbias = 1.65 V; AC input = 2.5 V(p-p); f = 100
kHz, CT_CP_HPD = H, LS_OE = L
6.14 Switching Characteristics
PARAMETER
CL
TEST CONDITIONS
MIN
TYP
MAX
Bus load capacitance (B side)
750
Bus load capacitance (A side)
15
UNIT
pF
6.15 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA
= 1.2 V
VCCA = 1.2 V
PARAMETER
tPHL
Propagation delay
tPLH
Propagation delay
tf
tr
fMAX
PINS
A to B
B to A
A to B
B to A
A port fall time
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
TEST CONDITIONS
MIN
MAX
344
DDC Channels Enabled
355
452
DDC Channels Enabled
178
138
DDC Channels Enabled
83
194
DDC Channels Enabled
DDC Channels Enabled
TYP
92
400
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UNIT
ns
ns
ns
ns
kHz
9
TPD12S015A
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6.16 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.2 V
VCCA = 1.2 V
PARAMETER
Propagation delay
tPLH
tr
TEST CONDITIONS
MIN
A to B
tPLH
tf
PINS
B to A
A to B
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
MAX
445
13
µs
0.266
140
CEC Channels Enabled
ns
96
CEC Channels Enabled
UNIT
ns
337
CEC Channels Enabled
B to A
A port fall time
TYP
202
ns
15
µs
6.17 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.2 V
VCCA = 1.2 V
PARAMETER
tPLH
tPLH
Propagation delay
PINS
B to A
B to A
TEST CONDITIONS
MIN
TYP
MAX
10
CEC Channels Enabled
UNIT
µs
9
tf
A port fall time
A Port
CEC Channels Enabled
0.67
ns
tr
A port rise time
A Port
CEC Channels Enabled
0.74
ns
6.18 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA
= 1.5 V
VCCA = 1.5 V
PARAMETER
tPLH
Propagation delay
tPLH
tf
tr
fMAX
PINS
TEST CONDITIONS
MIN
A to B
B to A
A to B
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
MAX
UNIT
335
265
DDC Channels Enabled
ns
438
B to A
A port fall time
TYP
169
110
DDC Channels Enabled
190
DDC Channels Enabled
DDC Channels Enabled
ns
83
ns
92
400
kHz
6.19 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.5 V
VCCA = 1.5 V
PARAMETER
tPLH
Propagation delay
tPLH
tf
tr
10
PINS
TEST CONDITIONS
MIN
TYP
A to B
437
B to A
267
A to B
CEC Channels Enabled
B to A
A port fall time
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
13
0.264
CEC Channels Enabled
CEC Channels Enabled
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110
96
MAX
UNIT
ns
µs
ns
202
ns
15
µs
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6.20 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.5 V
VCCA = 1.5 V
PARAMETER
tPLH
tPLH
Propagation delay
PINS
B to A
B to A
TEST CONDITIONS
MIN
TYP
MAX
10
CEC Channels Enabled
UNIT
µs
9
tf
A port fall time
A Port
CEC Channels Enabled
0.47
ns
tr
A port rise time
A Port
CEC Channels Enabled
0.51
ns
6.21 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA
= 1.8 V
VCCA = 1.8 V
PARAMETER
Propagation delay
tPLH
tr
fMAX
TEST CONDITIONS
MIN
A to B
tPLH
tf
PINS
B to A
A to B
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
MAX
UNIT
334
229
DDC Channels Enabled
ns
431
B to A
A port fall time
TYP
169
94
DDC Channels Enabled
191
DDC Channels Enabled
DDC Channels Enabled
ns
83
ns
92
400
kHz
6.22 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.8 V
VCCA = 1.8 V
PARAMETER
tPLH
Propagation delay
tPLH
tf
tr
PINS
TEST CONDITIONS
MIN
A to B
B to A
A to B
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
MAX
441
13
µs
0.26
94
CEC Channels Enabled
ns
96
CEC Channels Enabled
UNIT
ns
231
CEC Channels Enabled
B to A
A port fall time
TYP
201
ns
15
µs
6.23 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.8 V
VCCA = 1.8 V
PARAMETER
tPLH
tPLH
Propagation delay
PINS
B to A
B to A
TEST CONDITIONS
CEC Channels Enabled
MIN
TYP
MAX
10
9
UNIT
µs
tf
A port fall time
A Port
CEC Channels Enabled
0.41
ns
tr
A port rise time
A Port
CEC Channels Enabled
0.45
ns
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6.24 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA
= 2.5 V
VCCA = 2.5 V
PARAMETER
tPLH
Propagation delay
tPLH
tf
tr
fMAX
PINS
TEST CONDITIONS
MIN
A to B
B to A
A to B
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
MAX
UNIT
330
182
DDC Channels Enabled
ns
423
B to A
A port fall time
TYP
166
79
DDC Channels Enabled
188
DDC Channels Enabled
DDC Channels Enabled
ns
83
ns
92
400
kHz
6.25 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 2.5 V
VCCA = 2.5 V
PARAMETER
tPLH
Propagation delay
tPLH
tf
tr
PINS
TEST CONDITIONS
MIN
A to B
B to A
A to B
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
MAX
454
13
µs
0.255
79
CEC Channels Enabled
ns
96
CEC Channels Enabled
UNIT
ns
184
CEC Channels Enabled
B to A
A port fall time
TYP
194
ns
15
µs
6.26 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 2.5 V
VCCA = 2.5 V
PARAMETER
tPLH
tPLH
Propagation delay
PINS
B to A
B to A
TEST CONDITIONS
MIN
TYP
MAX
10
CEC Channels Enabled
UNIT
µs
9
tf
A port fall time
A Port
CEC Channels Enabled
0.37
ns
tr
A port rise time
A Port
CEC Channels Enabled
0.39
ns
6.27 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA
= 3.3 V
VCCA = 3.3 V
PARAMETER
tPLH
Propagation delay
tPLH
tf
tr
fMAX
12
PINS
TEST CONDITIONS
MIN
A to B
B to A
A to B
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
MAX
UNIT
323
158
DDC channels enabled
421
B to A
A port fall time
TYP
ns
162
71
DDC channels enabled
84
188
DDC channels enabled
DDC channels enabled
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92
400
ns
ns
kHz
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6.28 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 3.3 V
VCCA = 3.3 V
PARAMETER
Propagation delay
tPLH
tr
TEST CONDITIONS
MIN
A to B
tPLH
tf
PINS
B to A
A to B
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
MAX
450
13
µs
0.251
71
CEC channels enabled
ns
96
CEC channels enabled
UNIT
ns
160
CEC channels enabled
B to A
A port fall time
TYP
194
ns
15
µs
6.29 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 3.3 V
VCCA = 3.3 V
PARAMETER
tPLH
tPLH
Propagation delay
PINS
B to A
B to A
TEST CONDITIONS
CEC channels enabled
MIN
TYP
MAX
10
9
UNIT
µs
tf
A port fall time
A Port
CEC channels enabled
0.35
ns
tr
A port rise time
A Port
CEC channels enabled
0.37
ns
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6.30 Typical Characteristics
5.5
70
5.040
VBAT
5VOUT (20mA)
5VOUT (60mA)
4.1
5.3
4.0
5.000
5.2
55
5.1
3.9
4.980
50
5.0
3.8
4.960
45
4.9
3.7
4.940
40
4.8
35
4.7
3.6
4.920
30
4.6
3.5
4.900
25
4.5
3.4
4.880
20
4.4
3.3
4.860
15
4.3
3.2
4.840
4.820
VBAT Voltage (V)
10
4.2
5
4.1
3.1
0
4.0
3.0
0 1
2 3 4
5 6 7
8 9 10 11 12 13 14 15 16 17 18 19 20
0
4.800
1000 1500 2000 2500 3000 3500 4000 4500 5000
500
Time (us)
Time (us)
Figure 1. Load Transient Response
Figure 2. Line Transient Response
6.0
6
VCCA = VIH = 2.5 V, VBAT = 3.6 V
5.5
VCCA = VIH = 2.5 V, VBAT = 3.6 V
5
5.0
4.5
CT_CP_HPD
5VOUT (55mA)
5VOUT (65mA)
4
Voltage (V)
4.0
3.5
Voltage (V)
5.020
60
5VOUT Voltage (V)
ICCB Current (mA)
4.2
5.4
ICC_5VOUT
5VOUT
65
5VOUT Voltage (V)
75
3
3.0
2
2.5
2.0
1
CT_CP_HPD
5VOUT (55 mA)
5VOUT(65 mA)
1.5
1.0
0
0.5
-1
0.0
0
500
1000
1500
2000
-0.5
2500
3000
3500
4000
Time (us)
-1.0
-50
0
50
100
150
200
250
300
Time (us)
Figure 4. DC-DC Start-Up and Shutdown
30
80
20
70
10
60
0
50
-10
40
-20
Amplitude (V)
Amplitude (V)
Figure 3. tSTART
90
30
20
-40
10
-50
0
-60
-10
-70
-20
-80
-30
-90
0
20
40
60
80
100
120
Time (ns)
140
160
180
200
Figure 5. IEC Clamping Waveforms 8-kV Contact
(IEC ESD Pins)
14
-30
0
20
40
60
80
100 120
Time (ns)
140
160
180
200
Figure 6. IEC Clamping Waveforms -8 kV Contact (IEC ESD
Pins)
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Typical Characteristics (continued)
1.00000
S21
0
Closest signals D2+ to D2Farthest signals D2+ to CLK+
D2+ to D2D2+ to CLK+
-1.00000
-20
-3.00000
Insertion Loss (dB)
S21 (dB)
-40
-60
-80
-5.00000
-7.00000
-9.00000
-11.00000
-100
Tested with typical
operating voltage
-120
1.00E+04
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
-13.00000
-15.00000
1.000E+07
1.00E+10
Frequency (Hz)
1.000E+09
1.000E+10
Frequency (Hz)
Figure 7. Channel-to-Channel Crosstalk
Figure 8. Insertion Loss Data Line to GND
0.65
100
0.60
90
0.55
80
0.50
70
0.45
60
0.40
50
0.35
40
0.30
30
0.25
Efficiency (%)
Output Current (A)
1.000E+08
20
015 I_5VOUT
0.20
10
015A Efficiency
0.15
Eye Diagram Without TPD12S015A (2.5 Gbps Data Rate)
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
VBAT (V)
C001
Figure 9. Power Derating Curve
Eye Diagram With TPD12S015A (2.5 Gbps Data Rate)
Figure 11. Eye Diagram Performance on a Test Board for
the D+, D- Lines at 2.5 Gbps
Figure 10. Eye Diagram Performance on a Test Board for
the D+, D- Lines at 2.5 Gbps
Eye Diagram Without TPD12S015A (3.3 Gbps Data Rate)
Figure 12. Eye Diagram Performance on a Test Board for
the D+, D- Lines at 3.3 Gbps
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Typical Characteristics (continued)
Eye Diagram With TPD12S015A (3.3 Gbps Data Rate)
Figure 13. Eye Diagram Performance on a Test Board for the D+, D- Lines at 3.3 Gbps
16
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7 Parameter Measurement Information
VCCI
VCCO
DUT
IN
OUT
Input
CL
1M
Copyright © 2016, Texas Instruments Incorporated
PIN
CL
DDC, CEC (A side)
750 pF
DDC, CEC, HPD (B
side)
15 pF
VCC
Input
50%
50%
0V
Output
70%
30%
tf
70%
30%
VCC
VOL
tr
A.
RT termination resistance must be equal to ZOUT of pulse generators.
B.
CL includes probe and jig capacitance.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate
≥ 1 V/ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLH and tPHL are the same as tpd.
Figure 14. Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TPD12S015A is an integrated interface solution for HDMI 1.3/1.4 interfaces, for both portable and nonportable electronics applications. It has a boost DC-DC converter that uses the 2.3-V to 5.5-V internal power
supply and outputs regulated 5-V standard compliant power supply to the cable. This power supply output has
current limit and short-circuit protection function. There are bidirectional level shifting and signal conditioning
circuits on CEC, SCL, SDA with pullup resistors integrated to minimize the external passive discrete component
use. There is also a unidirectional level shifter for HPD signal that translates the 5-V HPD down to VCCA level.
The HPD_B port has a glitch filter to avoid false detection due to the bouncing while inserting the HDMI plug. For
the eight TMDS lines, there are high-speed ESD diodes on each line to make sure that the system pass 8-kV
contact ESD.
8.2 Functional Block Diagram
FB (IEC)
SW
VBAT
CT_CP_HPD
5VOUT (IEC)
5V
DC/DC
470k
PGND
Dx+, DxCLK+, CLK8
(IEC) HDMI
ESD Clamp
(x8)
LS_OE_INTERNAL
5VOUT
VCCA
3.3V
(Internal )
LDO
470k
HPD_B (IEC)
11k
LS_OE
VCCA
HPD_A
CT_CP_HPD VCCA
3.3V (Internal)
10k
26k
CEC_B (IEC)
CEC_A
5VOUT
SCL_B (IEC)
VCCA
1.75k
10k
ERC
SCL_A
5VOUT
SDA_B (IEC)
VCCA
1.75k
10k
ERC
SDA_A
LS_OE_INTERNAL
PGND
PGND
GND
Copyright © 2016, Texas Instruments Incorporated
3.3 V (Internal) is an internally generated voltage node for the CEC_B output buffer supply reference. An LDO
generates this 3.3 V from 5VOUT when LS_OE = H & CT_CP_HPD = H.
18
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8.3 Feature Description
8.3.1 Rise-Time Accelerators
The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on
the HDMI cable side. The rise time accelerator boosts the cable side DDC signal independent of which side of
the bus is releasing the signal.
8.3.2 Internal Pullup Resistor
The TPD12S015A has incorporated all the required pullup and pulldown resistors at the interface pins. The
system is designed to work properly with no external pullup resistors on the DDC, CEC, and HPD lines. For
proper system operation, no external resistors must be placed at the A and B ports. If there is internal pullups at
the host processor, they must be disabled.
8.3.3 Undervoltage Lockout
The undervoltage lockout circuit prevents the DC-DC converter from malfunctioning at low input voltages and
from excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the
undervoltage lockout threshold VBATUV. The undervoltage lockout threshold VBATUV for falling VIN is typically 2 V.
The device starts operation once the rising VIN trips undervoltage lockout threshold VBATUV again at typical 2.1 V.
8.3.4 Soft Start
The DC-DC converter has an internal soft-start circuit that controls the ramp-up of the output voltage. The output
voltage reaches its nominal value within tStart of typically 250 µs after CT_CP_HPD pin has been pulled to high
level. The output voltage ramps up from 5% to its nominal value within tRamp of 300 µs. This limits the inrush
current in the converter during start-up, and prevents possible input voltage drops when a battery or high
impedance power source is used. During soft start, the switch current limit is reduced to 300 mA until the output
voltage reaches VIN. Once the output voltage trips this threshold, the device operates with its nominal current
limit ILIMF.
8.3.5 DDC/CEC Level Shifting Function
The TPD12S015A enables DDC translation from VCCA (system side) voltage levels to 5-V (HDMI cable side)
voltage levels without degradation of system performance. The TPD12S015A contains two bidirectional opendrain buffers specifically designed to support up-translation and down-translation between the low voltage, VCCA
side DDC-bus and the 5-V DDC-bus. The port B I/Os are overvoltage tolerant to 5.5 V even when the device is
unpowered. After power up and with the LS_OE and CT_CP_HPD pins high, a low level on port A (below
approximately VILC = 0.08 × VCCA V) turns the corresponding port B driver (either SDA or SCL) on and drives port
B down to VOLB V. When port A rises above approximately 0.10 × VCCA V, the port B pulldown driver is turned off,
and the internal pullup resistor pulls the pin high. When port B falls first and goes below 0.3 × 5VOUT, a CMOS
hysteresis input buffer detects the falling edge, turns on the port A driver, and pulls port A down to approximately
VOLA = 0.16 × VCCA V. The port B pulldown is not enabled unless the port A voltage goes below VILC. If the port A
low voltage goes below VILC, the port B pulldown driver is enabled until port A rises above (VILC + ΔVT-HYSTA);
then port B, if not externally driven LOW, continues to rise being pulled up by the internal pullup resistor.
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Feature Description (continued)
VCCA
5VOUT
IACCEL CMP2
RPUA
150 mV
700 mV
RPUB
CMP1
Glitch
Filter
ACCEL
Port B
Port A
DDC Lines Only
300 mV
Copyright © 2016, Texas Instruments Incorporated
Figure 15. DDC/CEC Level Shifter Block Diagram
8.3.6 DDC/CEC Level Shifting Function When VCCA = 1.8 V
•
•
•
•
•
•
•
•
The threshold of CMP1 is approximately 150 mV ± the 40 mV of total hysteresis.
The comparator trips for a falling waveform at approximately 130 mV
The comparator trips for a rising waveform at approximately 170 mV
To be recognized as a zero, the level at Port A must first go below 130 mV (VILC in spec) and then stay
below 170 mV (VILA in spec)
To be recognized as a one, the level at A must first go above 170 mV and then stay above 130 mV
VILC is set to 110 mV to give some margin to the 130 mV
VILA is set to 140 mV to give some margin to the 170 mV
VIHA is set to 70% of VCCA to be consistent with standard CMOS levels
Figure 16. DDC/CEC Level Shifter Operation (B to A Direction)
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Feature Description (continued)
8.3.7 CEC Level Shifting Function
The CEC level shift function operates in the same manner as the DDC lines except that the CEC line does not
need the rise time accelerator function.
8.4 Device Functional Modes
8.4.1 Enable
The DC-DC converter is enabled when the CT_CP_HPD is set to high. At first, the internal reference is activated
and the internal analog circuits are settled. Afterwards, the soft start is activated and the output voltage is
ramped up. The output voltage reaches its nominal value in typically 250 μs after the device has been enabled.
The CT_CP_HPD input can be used to control power sequencing in a system with various DC-DC converters.
The CT_CP_HPD pin can be connected to the output of another converter, to drive the EN pin high and getting a
sequencing of supply rails. With CT_CP_HPD = GND, the DC-DC enters shutdown mode.
8.4.2 Power Save Mode
The TPD12S015A integrates a power save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold
voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in
PFM mode.
Table 2. System Block Diagram Function Table
5VOUT
LS_OE
CT_CP_HPD
VCCA
A-SIDE
DDC, BSIDE
CEC, BSIDE
PULLUPS
PULLUPS
PULLUPS
VBAT
CEC LDO
DC-DC &
HPD
DDC/CEC
ICC VCCA
ICC VBAT
VLTs
TYP
TYP
COMMENT
L
L
1.8 V
3.3 V
Off
Off
Off
Off
Off
Off
Off
1 µA
1 µA
Fully
Disabled
L
H
1.8 V
3.3 V
On
On
On
Off
Off
On
Off
1 µA
30 µA
DC-DC
on
H
L
1.8 V
3.3 V
Off
Off
Off
Off
Off
Off
Off
1 µA
1 µA
Not Valid
State
H
H
1.8 V
3.3 V
On
On
On
On
On
On
On
13 µA
255 µA
Fully On
X
X
0V
0V
Off
High-Z
High-Z
High-Z
Off
Off
Off
0
0
Power
Down
X
X
1.8 V
0V
Off
Low
High-Z
High-Z
Off
Off
Off
0
0
Power
Down
X
X
0V
3.3 V
Off
High-Z
High-Z
High-Z
Off
Off
Off
0
0
Power
Down
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPD12S015A is an integrated solution for HDMI 1.3/1.4 interface. The device has a boost converter on the
power supply, signal conditioning circuits on CEC, SCL, SDA, HPD lines, and ESD protection on the TMDS lines.
To get the best performance, see Design Requirements, Detailed Design Procedure, and Application Curves.
9.2 Typical Applications
Some HDMI controller chips may have two GPIOs to control the HDMI interface chip. Figure 17 shows how
TPD12S015A is used in this situation. Whereas some HDMI driver chips may have only one GPIO(CT_CP_HPD)
available. In this situation, LE_OE pin is tied to HPD_A instead. Figure 18 shows how TPD12S015A is used in
this situation.
1.2V to 3.3V
0.1µF
HOT PLUG 1
VCCA
CT_CP_HPD
LS_OE
HPD_A
HPD_B
UTILITY 2
TMDS_D2+ 3
D2+
HDMI Connector
GND 4
TMDS_D2- 5
D2-
TMDSD1+ 6
D1+
GND 7
D1-
TMDSD1- 8
TPD12S015A
TMDS_D0+ 9
HDMI Controller
D0+
GND 10
D0-
TMDS_D0- 11
TMDS_CLK+ 12
CLK+
GND 13
CLK-
TMDS_CLK- 14
CEC 15
CEC_B
CEC_A
GND 16
SCL_B
SCL_A
SDA 18
SDA_B
SDA_A
P5V 19
5V_OUT
SCL 17
GND 20
4.7µF
FB
VBAT
GND/PGND
SW
1µH
4.7µF
Battery Supply
(2.3V to 5.5V)
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Application Schematics for HDMI Controllers With Two GPIOs for HDMI Interface Control
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Typical Applications (continued)
1.2V to 3.3V
0.1µF
HOT PLUG 1
VCCA
CT_CP_HPD
LS_OE
HPD_A
HPD_B
UTILITY 2
TMDS_D2+ 3
D2+
HDMI Connector
GND 4
TMDS_D2- 5
D2-
TMDSD1+ 6
D1+
GND 7
D1-
TMDSD1- 8
TPD12S015A
TMDS_D0+ 9
HDMI Controller
D0+
GND 10
D0-
TMDS_D0- 11
TMDS_CLK+ 12
CLK+
GND 13
CLK-
TMDS_CLK- 14
CEC 15
CEC_B
CEC_A
SCL 17
SCL_B
SCL_A
SDA 18
SDA_B
SDA_A
P5V 19
5V_OUT
GND 16
GND 20
4.7µF
FB
VBAT
GND/PGND
SW
1µH
Battery Supply
(2.3V to 5.5V)
4.7µF
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Application Schematics for HDMI Controllers With One GPIO for HDMI Interface Control
9.2.1 Design Requirements
Table 3 lists the known system parameters for an HDMI 1.3/1.4 application.
Table 3. Design Parameters
DESIGN PARAMETER
VALUE
5V_OUT DC current
55 mA
CEC_A, HPD_A, SCL_A, SDA_A voltage level
VCCA
HDMI data rate per TMDS signal pair
3.4 Gbps
Required IEC 61000-4-2 ESD Protection
±8-kV Contact
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
To make sure that the TPD12S015A devices can operate, an inductor must be connected between pin VBAT and
pin SW. A boost converter normally requires two main passive components for storing energy during the
conversion. A boost inductor and a storage capacitor at the output are required. To select the boost inductor, TI
recommends keeping the possible peak inductor current below the current limit threshold of the power switch in
the chosen configuration. The highest peak current through the inductor and the switch depends on the output
load, the input (VBAT), and the output voltage (5VOUT). Use Equation 1 to estimate the maximum average
inductor current.
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IL _ MAX » IOUT ´
www.ti.com
VOUT
h ´ VIN
(1)
For example, for an output current of 55 mA at 5VOUT, approximately 150 mA of average current flows through
the inductor at a minimum input voltage of 2.3 V.
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the
magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. However, in the same way,
regulation time at load changes rises. In addition, a larger inductor increases the total system size and cost. With
these parameters, it is possible to calculate the value of the minimum inductance by using Equation 2.
L M IN »
V IN ´ (V O U T - V IN )
D IL ´ f ´ V O U T
where
•
•
f is the switching frequency
ΔIL is the ripple current in the inductor, that is, 20% × IL
(2)
With this calculated value and the calculated currents, it is possible to choose a suitable inductor. In typical
applications, TI recommends 1-µH inductance. The device has been optimized to operate with inductance values
between 1 µH and 1.3 µH. TI recommends using at least 1-µH inductance, even if Equation 2 yields something
lower. Take care so that load transients and losses in the circuit can lead to higher currents as estimated in
Equation 3. Also, the losses in the inductor caused by magnetic hysteresis losses and copper losses are a major
parameter for total circuit efficiency.
With the chosen inductance value, the peak current for the inductor in steady state operation can be calculated.
Equation 3 shows how to calculate the peak current I.
IL ( peak ) =
where
VIN ´ D
IOUT
+
2 ´ f ´ L (1 - D )´h
D=
VOUT - VIN
VOUT
(3)
This would be the critical value for the current rating for selecting the inductor. It also must be considered that
load transients and error conditions may cause higher inductor currents.
9.2.2.2 Input Capacitor
Because of the nature of the boost converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. TI recommends at least a 1.2-µF input capacitor to improve transient behavior of the
regulator and EMI behavior of the total power supply circuit. TI recommends placing a ceramic capacitor as close
as possible to the VIN and GND pins; to improve the input noise filter, it is better to use a 4.7-µF capacitor.
9.2.2.3 Output Capacitor
For the output capacitor, TI recommends using small ceramic capacitors placed as close as possible to the VOUT
and GND pins of the IC. If, for any reason, the application requires the use of large capacitors, which cannot be
placed close to the IC, TI recommends using a smaller ceramic capacitor in parallel to the large one. This small
capacitor must be placed as close as possible to the VOUT and GND pins of the IC. To get an estimate of the
recommended minimum output capacitance, use Equation 4.
C min =
IOUT ´ (VOUT - VIN )
f ´ DV ´ VOUT
where
•
•
24
f is the switching frequency
ΔV is the maximum allowed ripple
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With a chosen ripple voltage of 10 mV, a minimum effective capacitance of 2.7 µF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using
Equation 5.
ΔVESR = IOUT × RESR
(5)
A capacitor with a value in the range of the calculated minimum must be used. This is required to maintain
control loop stability. There are no additional requirements regarding minimum ESR. There is no upper limit for
the output capacitance value. Larger capacitors cause lower output voltage ripple as well as lower output voltage
drop during load transients.
Note that ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective
capacitance needed. Therefore, the right capacitor value must be chosen very carefully. Package size and
voltage rating in combination with material are responsible for differences between the rated capacitor value and
the effective capacitance. The minimum effective capacitance value must be 1.2 µF, but the preferred value is
about 4.7 µF.
Table 4. Passive Components: Recommended Minimum Effective Values
COMPONENT
MIN
TARGET
MAX
UNIT
CIN
1.2
4.7
6.5
µF
COUT
1.2
4.7
10
µF
LIN
0.7
1
1.3
µH
9.2.2.4 CEC, HPD, SCL, SDA Level Shifting Function
To accommodate for the lower logic levels of some processors' control lines, level shifters are needed to
translate the interface voltage down to VCCA, the voltage level used by the processor. The TPD12S015A has
bidirectional level shifters on CEC, SCL, SDA lines to support the two-way communication. The pullup resistors
are integrated to minimize the number of external components. For HPD line, only one way of hot-plug indication
is needed, the level shifter is unidirectional. There is a built-in HPD_B pulldown resistor to keep the voltage level
low on the connector side when nothing is attached. Apart from the signal level translation, the rise-time
accelerators on the connector side increases the load driving capability.
9.2.2.5 ESD
To get the best ESD performance on the interface side pins, high performance ESD diodes are needed. The
TPD12S015A's ESD diodes on D0+, D0-, D1+, D1-, D2+, D2-, CLK+, CLK-, SCL_B, SDA_B, CEC_B, HPD_B,
5VOUT, FB ensure passing 8-kV contact IEC, the highest level ESD. Signal integrity on TMDS lines is also a
design concern that needs to be evaluated to meet the HDMI 1.3/1.4 data rate. With the typical I/O capacitance
of 1.3 pF and a bandwidth above 3 GHz, Figure 12 shows that TPD12S015A's ESD structure has enough margin
to meet the data rate requirement of HDMI 1.3/1.4.
9.2.2.6 Ground Offset Consideration
Ground offset between the TPD12S015A ground and the ground of devices on port A of the TPD12S015A must
be avoided. The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of sinking 3 mA of
current at 0.4 V has an output resistance of 133 Ω or less. Such a driver shares enough current with the port A
output pulldown of the TPD12S015A to be seen as a LOW as long as the ground offset is zero. If the ground
offset is greater than 0 V, then the driver resistance must be less. Because VILC can be as low as 90 mV at cold
temperatures and the low end of the current distribution, the maximum ground offset must not exceed 50 mV.
Bus repeaters that use an output offset are not interoperable with the port A of the TPD12S015A as their output
LOW levels are not recognized by the TPD12S015A as a LOW. If the TPD12S015A is placed in an application
where the VIL of port A of the TPD12S015A does not go below its VILC, it pulls port B LOW initially when port A
input transitions LOW but the port B returns HIGH, so it does not reproduce the port A input on port B. Such
applications must be avoided. Port B is interoperable with all I2C bus slaves, masters, and repeaters.
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9.2.3 Application Curves
6.0
VCCA = VIH = 2.5 V, VBAT = 3.6 V
5.5
5.0
4.5
4.0
Voltage (V)
3.5
3.0
2.5
2.0
CT_CP_HPD
5VOUT (55 mA)
5VOUT(65 mA)
1.5
1.0
0.5
0.0
-0.5
-1.0
-50
0
50
100
150
200
250
300
Time (us)
Figure 19. tSTART
Figure 20. DDC/CEC Level Shifting Operation (B to A
Direction)
Eye Diagram Without TPD12S015A (3.3 Gbps Data Rate)
Figure 21. Eye Diagram Performance on a Test Board for
the D+, D- Lines at 3.3 Gbps
26
Eye Diagram With TPD12S015A (3.3 Gbps Data Rate)
Figure 22. Eye Diagram Performance on a Test Board for
the D+, D- Lines at 3.3 Gbps
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10 Power Supply Recommendations
See Detailed Design Procedure for detailed power supply recommendations.
11 Layout
11.1 Layout Guidelines
For proper operation, follow these layout and design guidelines.
• Place the TPD12S015A as close to the connector as possible. This allows it to remove the energy associated
with ESD strike before it reaches the internal circuitry of the system board.
• Place power line capacitors and inductors close to the pins with wide traces to allow enough current to flow
through with less trace parasitics.
• Ensure that there is enough metallization for the GND pad. A sufficient current path enables safe discharge of
all the energy associated with the ESD strike.
• The critical routing paths for HDMI interface are the high-speed TMDS lines. Make sure to match the lengths
of the differential pair. Maintain constant trace width after to avoid impedance mismatches in the transmission
lines. Maximize differential pair-to-pair spacing when possible.
11.2 Layout Example
Figure 23. Board Layout (DC-DC Components) (Top View)
List of components:
• LIN = MURATA LQM21PN1R0MC0 (1 µH, 800 mA, 0805, Shielded)
• CIN = COUT = MURATA LLL31MR70J475MA01 (4.7 µF, Low ESL type, 6.3 V, 0306, X7R)
• CVCCA = MURATA GRM155R60J475ME87D (0.1 µF, 6.3 V, 0402, X5R)
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TPD12S015A EVM User's Guide (SLVU485)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD12S015AYFFR
ACTIVE
DSBGA
YFF
28
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
PN015A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
