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TPD12S016
SLLSE96F – SEPTEMBER 2011 – REVISED OCTOBER 2015
TPD12S016 HDMI Companion Chip with I2C Level Shifting Buffer,
12-Channel ESD Protection, and Current-Limit Load Switch
1 Features
3 Description
•
The TPD12S016 is a single-chip High Definition
Multimedia Interface (HDMI) device with autodirection sensing I2C voltage level shift buffers, a load
switch, and integrated low capacitance high-speed
electrostatic discharge (ESD) transient voltage
suppression (TVS) protection diodes. A 55-mA
current limited 5-V output (5V_OUT) sources the
HDMI power line. The control of 5V_OUT and the hot
plug detect (HPD) circuitry is independent of the
LS_OE control signal, and is controlled by the
CT_HPD pin, which enables the detection scheme
(5V_OUT and HPD) to be active before enabling the
HDMI link. The SDA, SCL, and CEC lines pull up to
VCCA on the A side. On the B side, the CEC_B pin
pulls up to an internal 3.3-V supply rail, SCL_B and
SDA_B each pull up to the 5-V rail (5V_OUT). The
SCL and SDA pins meet the I2C specification and
drive up to 750 pF capacitive loads, exceeding the
HDMI 1.4 specifications. The HPD_B port has a glitch
filter to avoid false detection due to plug bouncing
during the HDMI connector insertion. TPD12S016
offers reverse current blocking at the 5V_OUT pin.
SCL_B, SDA_B, CEC_B pins also feature reversecurrent blocking when the system is powered off.
1
•
•
•
•
•
•
•
•
•
Conforms to HDMI Compliance Tests without any
External Components
IEC 61000-4-2 ESD Protection
– ±8-kV Contact Discharge
Supports HDMI 1.4 Data Rate
Matches Class D and Class C Pin Mapping
8-Channel ESD Protection for Four Differential
Pairs With Ultra-Low Differential Capacitance
Matching (0.05 pF)
On-Chip Load Switch With 55-mA Current Limit at
the HDMI 5V_OUT Pin
Auto-direction Sensing I2C Level Shifter with Oneshot Circuit to Drive a Long HDMI Cable (750-pF
Load)
Back-drive Protection on HDMI Connector Side
Ports
Integrated Pullup and Pulldown Resistors per
HDMI Specification
Space Saving 24-Pin RKT Package and 24TSSOP Package
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
Cell Phones
eBook
Portable Media Players
Set-top Box
TPD12S016
PACKAGE
BODY SIZE (NOM)
QFN (24)
4.00 mm × 2.00 mm
TSSOP (24)
7.80 mm × 6.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1.2 V to 3.3 V
0.1 mF
HOT PLUG 1
VCCA CT_HPD LS_OE
HPD_B
HPD_A
UTILITY 2
TMDS_D2+ 3
D2+
GND 4
D2-
H D M I C o n ne c to r
TMDS_D2- 5
TMDSD1+ 6
D1+
GND 7
TMDSD1- 8
D1TPD12S016
TMDS_D0+ 9
HDMI Controller
D0+
GND 10
TMDS_D0 - 11
D0-
TMDS_CLK+ 12
CLK+
GND 13
TMDS_CLK - 14
CLK-
CEC 15
CEC_B
CEC_A
SCL 17
SCL_B
SCL_A
SDA 18
SDA_B
SDA_A
P5V 19
5V_OUT
VCC5V
GND 16
GND 20
0.1 mF
0.1 mF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD12S016
SLLSE96F – SEPTEMBER 2011 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 12
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
4
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 18
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Examples................................................... 21
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (December 2014) to Revision F
Page
•
Added test condition frequency to capacitance ..................................................................................................................... 7
•
Added test condition frequency to capacitance ..................................................................................................................... 8
•
Added Community Resources ............................................................................................................................................. 23
Changes from Revision D (August 2013) to Revision E
•
Page
Added Handling Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
Changes from Original (January 2013) to Revision A
Page
•
Added Eye Diagram Using EVM Without TPD12S016 for the TMDS Lines at 1080p, 340MHz Pixel Clock, 3.4Gbps....... 19
•
Added Eye Diagram Using EVM with TPD12S016 for the TMDS Lines at 1080p, 340MHz Pixel Clock, 3.4Gbps............. 19
Changes from Revision A (February 2013) to Revision B
Page
•
Added PW and RKT packages values for IO capacitance..................................................................................................... 7
•
Added LOAD SWITCH ILEAKAGE_REVERSE vs V5V_OUT graph. .................................................................................................. 12
•
Updated Circuit Schematic Diagram. ................................................................................................................................... 14
Changes from Revision B (February 2013) to Revision C
•
2
Page
Updated table formatting. ....................................................................................................................................................... 7
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SLLSE96F – SEPTEMBER 2011 – REVISED OCTOBER 2015
Changes from Revision C (August 2013) to Revision D
•
Page
Updated power savings options table................................................................................................................................... 17
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3
TPD12S016
SLLSE96F – SEPTEMBER 2011 – REVISED OCTOBER 2015
www.ti.com
5 Pin Configuration and Functions
SCL_A
PW Package
24-Pin TSSOP
Top View
VCCA
CEC_A
RKT Package
24-Pin UQFN
Top View
SDA_A
HPD_A
LS_OE
D2+
D2D1+
D1-
GND
CEC_B
SCL_B
SDA_B
HPD_B
VCC5V
GND
D0+
D0CLK+
CLKGND
CT_HPD
VCCA
SCL_A
D2+
SDA_A
D2-
HPD_A-
D1+
LS_OE
D1GND
GND
5 V_OUT
1
CEC_A
CEC_B
D0+
SCL_B
D0-
SDA_B
CLK+
HPD_B-
CLK-
VCC5V
GND
5V_OUT
CT_HPD
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
RKT
PW
16, 17, 19 to
22
17, 18, 20 to
23
IO
HDMI TMDS data. Connect to HDMI controller and HDMI connector
directly
14, 15
15, 16
IO
HDMI TMDS clock. Connect to HDMI controller and HDMI connector
directly
HPD_A
3
4
O
Hot plug detect output referenced to VCCA. Connect to HDMI controller hot
plug detect input pin
HPD_B
9
10
I
Hot plug detect input. Connect directly to HDMI connector hot plug detect
pin
CEC_A
24
1
IO
HDMI controller side CEC signal pin referenced to VCCA. Connect to HDMI
controller
CEC_B
6
7
IO
HDMI connector side CEC signal pin referenced to internal 3.3-V supply.
Connect to HDMI connector CEC pin
SCL_A
1
2
IO
HDMI controller side SCL signal pin referenced to VCCA. Connect to HDMI
controller
SCL_B
7
8
IO
HDMI connector side SCL signal pin referenced to 5V_OUT supply.
Connect to HDMI connector SCL pin
SDA_A
2
3
IO
HDMI controller side SDA signal pin referenced to VCCA. Connect to HDMI
controller
SDA_B
8
9
IO
HDMI connector side SDA signal pin referenced to 5V_OUT supply.
Connect to HDMI connector SDA pin
LS_OE
4
5
I
Disables the Level shifters when OE = L. The OE pin is referenced to VCCA
CT_HPD
11
12
I
Disables the load switch and HPD_B when CT_HPD = L. The CT_HPD is
referenced to VCCA
VCC5V
10
11
PWR
Internal 5-V supply (input to the load switch)
VCCA
23
24
PWR
Internal PCB low voltage supply (same as the HDMI controller chip supply)
5V_OUT
12
13
O
5, 13, 18
6, 14, 19
GND
D–, D+
CLK+, CLK–
GND
4
External 5-V supply (output of the load switch)
Connect to system ground plane
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SLLSE96F – SEPTEMBER 2011 – REVISED OCTOBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCCA
Supply voltage
VCC5V
Supply voltage
VI
Input voltage
(1)
MIN
MAX
UNIT
–0.3
4.0
V
V
–0.3
6.0
SCL_A, SDA_A, CEC_A
–0.3
4.0
SCL_B, SDA_B, CEC_B
–0.3
6.0
CT_HPD, LS_OE
–0.3
4.0
D, CLK
–0.3
6.0
–0.3
4.0
6.0
V
VO
Voltage applied to any output in the
high-impedance or power-off state (1)
SCL_A, SDA_A, CEC_A, CT_HPD, LS_OE
SCL_B, SDA_B, CEC_B
–0.3
VO
Voltage applied to any output in the
high or low state (1) (2)
SCL_A, SDA_A, CEC_A, CT_HPD, LS_OE
–0.3
VCCA + 0.5
SCL_B, SDA_B, CEC_B
–0.3
5V_OUT + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
±100
mA
150
°C
Continuous current through 5V_OUT,
or GND
Tstg
(1)
(2)
Storage temperature
–65
V
V
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
VALUE
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic
discharge
LS_OE, CT_HPD, SCL_A, SDA_A,
CEC_A, HPD_A, VCCA
±2000
Dx, CLKx, SCL_B, SDA_B, CEC_B,
HPD_B , 5V_OUT
±15000
Charged-device model (CDM), per JEDEC specification JESD22-C101
IEC 61000-4-2 Contact Discharge
±8000
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V
±1000
Dx, CLKx, SCL_B, SDA_B, CEC_B,
HPD_B , 5V_OUT
Copyright © 2011–2015, Texas Instruments Incorporated
UNIT
5
TPD12S016
SLLSE96F – SEPTEMBER 2011 – REVISED OCTOBER 2015
www.ti.com
6.3 Recommended Operating Conditions
over recommended operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCCA
Supply voltage
1.1
3.6
V
VCC5V
Supply voltage
4.5
5.5
V
SCL_A, SDA_A
VCCA =1.1 V to 3.6 V
0.7 × VCCA
VCCA
V
CEC_A
VCCA =1.1 V to 3.6 V
0.7 × VCCA
VCCA
V
CT__HPD, LS_OE
VCCA =1.1 V to 3.6 V
1.0
VCCA
V
SCL_B, SDA_B
5V_OUT = 5.0 V
0.7 × 5V_OUT
5V_OUT
V
CEC_B
5V_OUT = 5.0 V
0.7 × V3P3 (1)
V3P3
HPD_B
5V_OUT = 5.0 V
2.0
5V_OUT
SCL_A, SDA_A
VCCA =1.1 V to 3.6 V
–0.5
0.082 × VCCA
V
CEC_A
VCCA =1.1 V to 3.6 V
–0.5
0.082 × VCCA
V
CT_HPD, LS_OE
VCCA =1.1 V to 3.6 V
–0.5
0.4
V
SCL_B, SDA_B
5V_OUT = 5.0 V
–0.5
0.3 × 5V_OUT
V
CEC_B
5V_OUT = 5.0 V
–0.5
0.3 × V3P3
V
HPD_B
5V_OUT = 5.0 V
0
0.8
V
VILC
(contention) Low-level
input voltage
SCL_A, SDA_A, CEC_A
VCCA =1.1 V to 3.6 V
–0.5
0.065 × VCCA
V
VOL - VILC
Delta between VOL and
VILC
SCL_A, SDA_A, CEC_A
VCCA =1.1 V to 3.6 V
TA
Operating free-air temperature
VIH
High-level input voltage
VIL
(1)
Low-level input voltage
0.1 × VCCA
mV
–40
85
°C
The V3P3 is an internal 3.3V power supply node. The V3P3 is generated from the 5V supply pin through the on-chip LDO.
6.4 Thermal Information
TPD12S016
THERMAL METRIC (1)
RKT (UQFN)
PW (TSSOP)
UNIT
24 PINS
24 PINS
RθJA
Junction-to-ambient thermal resistance
77.9
88.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.0
26.5
°C/W
RθJB
Junction-to-board thermal resistance
29.3
43.5
°C/W
ψJT
Junction-to-top characterization parameter
0.5
1.1
°C/W
ψJB
Junction-to-board characterization parameter
29.3
43.0
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLLSE96F – SEPTEMBER 2011 – REVISED OCTOBER 2015
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.01
0.5
0.8
1.0
UNIT
HIGH SPEED ESD LINES: DX, CLKX
IIO
Current through ESD clamp ports
VCCA = 3.3 V,
VCC5V = 5.0 V,
VIO = 3.3 V
D, CLK
VDL
Diode forward voltage
ID = 8 mA
Lower clamp diode
RDYN
Dynamic resistance
I=1A
D, CLK
CIO
IO capacitance
VCC = 5 V,
VIO = 2.5 V
ƒ = 1 MHz
D, CLK
ΔCIO_TMDS
Differential capacitance for the Dx+,
Dx– lines
VCC = 5 V,
VIO = 2.5 V
ƒ = 1 MHz
D, CLK
VBR
Break-down voltage
IIO = 1 mA
PW Package
RKT Package
µA
V
Ω
1
1.0
pF
1.2
0.05
6.5
pF
9
V
LOAD SWITCH VCC5V, 5V_OUT
Supply current at VCC5V
VCC5V = 5 V, 5V OUT =Open, LS_OE = GND,
CT_HPD = GND
1
45
µA
Supply current at VCC5V
VCC5V = 5 V, 5V OUT =Open, LS_OE = GND,
CT_HPD = 3.3 V
4
50
µA
ISC
Short circuit current at 5V_OUT
VCC5V = 5 V, 5V_OUT = GND
150
200
mA
VDROP
5V_OUT output voltage drop
VCC5V = 5 V, I5V_OUT = 55 mA
35
50
mV
TON
Turn on time, VCC5V to 5V_OUT
CLOAD = 0.1 µF, RLOAD = 500 Ω
77
µs
TOFF
Turn off time, VCC5V to 5V_OUT
CLOAD = 0.1 µF, RLOAD = 500 Ω
7.0
µs
Shutdown threshold, TRIP (1)
140
ICC5V
TSHUT
Thermal Shutdown
100
HYST (2)
°C
12
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A AND x_B PORTS)
VOHA
IOH = –20 μA
VI = VIH
VCCA = 1.1 V
to 3.6 V
VOLA
IOL = 20 µA
VI = VIL
VCCA = 1.1 V
to 3.6 V
VOHB
IOH = –20 μA
VI = VIH
IOL = 3 mA
VI = VIL
VOLB
ΔVT
Hysteresis at the SDx_A (VT+ – VT–)
VCCA = 1.1 V to 3.6 V
ΔVT
Hysteresis at the SDx_B (VT+ – VT–)
VCCA = 1.1 V to 3.6 V
VCCA × 0.80
V
VCCA × 0.17
V
5VOUT ×
0.90
V
0.4
mV
400
mV
SCL_A, SDA_A
Pull-up connected to VCCA rail
10
SCL_B, SDA_B
Pull-up connected to 5-V rail
1.75
Pull-up connected to 5-V rail
15
RPU
(Internal pullup)
IPULLUPAC
Transient boosted pullup current
(rise-time accelerator)
SCL_B, SDA_B
A port
VCCA = 0 V, VI or VO = 0 to 3.6 V
VCCA = 0 V
±5
B port
5VOUT = 0 V, VI or VO = 0 to 5.5 V
VCCA = 0 V to
3.6 V
±5
B port
VO = VCCO or GND
VCCA = 1.1 V
to 3.6 V
±5
A port
VI = VCCI or GND
VCCA = 1.1 V
to 3.6 V
±5
Ioff
IOZ
(1)
(2)
V
40
kΩ
mA
μA
μA
The TPD12S016 turns off after the device temperature reaches the TRIP temperature.
After the thermal shut-down circuit turns off the load switch, the switch turns on again after the device junction temperature cools down
to a temperature equals to or less than TRIP-HYST.
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TPD12S016
SLLSE96F – SEPTEMBER 2011 – REVISED OCTOBER 2015
www.ti.com
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE LEVEL SHIFTER – CEC LINE (x_A AND x_B PORTS)
VOHA
IOH = –20 μA
VI = VIH
VCCA = 1.1 V
to 3.6 V
VOLA
IOL = 20 µA
VI = VIL
VCCA = 1.1 V
to 3.6 V
VOHB
IOH = –20 μA
VI = VIH
VOLB
IOL = 3 mA
VI = VIL
ΔVT
Hysteresis at the Sxx_A (VT+ – VT–)
VCCA = 1.1 V to 3.6 V
ΔVT
Hysteresis at the Sxx_B (VT+ – VT–)
VCCA = 1.1 V to 3.6 V
RPU
(Internal pullup)
A port
Ioff
VCCA × 0.80
V
VCCA × 0.17
V
V3P3 × 0.80
V
0.4
CEC_A
Pull-up connected to VCCA rail
CEC_B
Pull-up connected to 3.3 V rail
mV
300
mV
10
22
26
30
VCCA = 0 V, VI or VO = 0 to 3.6 V
VCCA = 0 V
B port
5VOUT = 0 V, VI or VO = 0 to 5.5 V
VCCA = 0 V to
3.6 V
±1.8
B port
VO = VCCO or GND
VCCA = 1.1 V
to 3.6 V
±5
A port
VI = VCCI or GND
VCCA = 1.1 V
to 3.6 V
±5
IOZ
V
40
kΩ
±5
μA
μA
VOLTAGE LEVEL SHIFTER – HPD LINE (x_A AND x_B PORTS)
VOHA
IOH = –3 mA
VI = VIH
VCCA = 1.1 V
to 3.6 V
VOLA
IOL = 3 mA
VI = VIL
VCCA = 1.1 V
to 3.6 V
VCCA × 0.07
V
0.4
V
ΔVT
Hysteresis (VT+ – VT–)
VCCA = 1.1 V to 3.6 V
RPD
(Internal pulldown resistor)
HPD_B
Pull-down connected to GND
Ioff
A port
VO = VCCO or GND
VCCA = 0 V
±5
μA
IOZ
A port
VI = VCCO or GND
VCCA = 3.6 V
±5
μA
VI = VCCA or GND
VCCA = 1.1 V to 3.6 V
±12
μA
Control inputs
VI = 1.89 V or GND
VCCA = 1.1 to 3.6 V; ƒ = 1 MHz
7.1
pF
A port
VO = 1.89 V or
GND
VCCA = 1.1 to 3.6 V; ƒ = 1 MHz
8.3
pF
B port
VO = 5.0 V or GND
V5VOUT = 5.0 V; ƒ = 1 MHz
15
pF
400
mV
11
kΩ
LS_OE, CT_CP_HPD
II
I/O CAPACITANCES
CI
CIO
8
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CL
PINS
TEST CONDITIONS
MIN
TYP
MAX
Bus load capacitance (B side)
750
Bus load capacitance (A side)
15
UNIT
pF
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A And x_B PORTS) VCCA = 1.2 V
tPHL
Propagation delay
tPLH
Propagation delay
tFALL
tRISE
F(MAX)
A to B
310
B to A
420
A to B
510
B to A
427
A Port fall time
A-Port
B Port fall time
B-Port
SCL/SDA channels enabled
225
A Port rise time
A-Port
315
B Port rise time
B-Port
415
Maximum switching frequency
334
400
ns
ns
ns
ns
kHz
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) VCCA = 1.2 V
tPHL
Propagation delay
tPLH
Propagation delay
tFALL
tRISE
A to B
385
B to A
526
A to B
13.8
µs
B to A
16.6
ns
CEC channel enabled
334
ns
A Port fall time
A-Port
B Port fall time
B-Port
170
A Port rise time
A-Port
315
ns
B Port rise time
B-Port
28
µs
ns
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) VCCA = 1.2 V
tPHL
Propagation delay
B to A
14.4
µs
tPLH
Propagation delay
B to A
9.2
µs
tFALL
A Port fall time
A-Port
2.1
ns
tRISE
A Port rise time
A-Port
2.1
ns
A to B
310
ns
B to A
420
ns
A to B
410
ns
425
ns
250
ns
HPD channel enabled
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A AND x_B PORTS) VCCA = 1.5 V
tPHL
tPLH
tFALL
tRISE
F(MAX)
Propagation delay
Propagation delay
B to A
A Port fall time
A-Port
SCL/SDA channels enabled
B Port fall time
B-Port
225
ns
A Port rise time
A-Port
315
ns
B Port fall time
B-Port
415
Maximum switching frequency
400
ns
kHz
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) VCCA = 1.5 V
tPHL
Propagation delay
tPLH
Propagation delay
tFALL
tRISE
A to B
380
B to A
420
A to B
13.8
µs
16.6
ns
B to A
CEC channel enabled
250
ns
A Port fall time
A-Port
B Port fall time
B-Port
170
A Port rise time
A-Port
315
ns
B Port rise time
B-Port
28
µs
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Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) VCCA = 1.5 V
tPHL
Propagation delay
B to A
14.4
µs
tPLH
Propagation delay
B to A
9.2
µs
tFALL
A Port fall time
A-Port
1.8
ns
tRISE
A Port rise time
A-Port
1.8
ns
A to B
300
ns
B to A
350
ns
A to B
400
ns
B to A
420
ns
HPD channel enabled
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A AND x_B PORTS) VCCA = 1.8 V
tPHL
tPLH
tFALL
tRISE
F(MAX)
Propagation delay
Propagation delay
A Port fall time
A-Port
210
ns
B Port fall time
B-Port
SCL/SDA channels enabled
225
ns
A Port rise time
A-Port
315
ns
B Port fall time
B-Port
415
Maximum switching frequency
400
ns
kHz
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) VCCA = 1.8 V
tPHL
Propagation delay
tPLH
Propagation delay
tFALL
tRISE
A to B
375
B to A
366
A to B
13.8
µs
B to A
16.6
ns
CEC channel enabled
210
ns
A Port fall time
A-Port
B Port fall time
B-Port
170
A Port rise time
A-Port
315
ns
B Port rise time
B-Port
28
µs
ns
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) VCCA = 1.8 V
tPHL
Propagation delay
B to A
14.2
µs
tPLH
Propagation delay
B to A
9.2
µs
tFALL
A Port fall time
A-Port
1.5
ns
tRISE
A Port rise time
A-Port
1.5
ns
HPD channels enabled
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A And x_B PORTS) VCCA = 2.5 V
tPHL
Propagation delay
tPLH
Propagation delay
tFALL
tRISE
F(MAX)
10
A to B
300
B to A
400
A to B
290
B to A
420
A Port fall time
A-Port
B Port fall time
B-Port
SCL/SDA channels enabled
225
A Port rise time
A-Port
315
B Port fall time
B-Port
415
Maximum switching frequency
170
400
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ns
ns
kHz
ns
kHz
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Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) VCCA = 2.5 V
tPHL
Propagation delay
tPLH
Propagation delay
tFALL
tRISE
A to B
375
B to A
305
A to B
13.8
µs
B to A
16.6
ns
CEC channel enabled
170
ns
A Port fall time
A-Port
B Port fall time
B-Port
170
A Port rise time
A-Port
315
ns
B Port rise time
B-Port
28
µs
ns
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) VCCA = 2.5 V
tPHL
Propagation delay
B to A
14.2
µs
tPLH
Propagation delay
B to A
9.2
µs
tFALL
A Port fall time
A-Port
1.2
ns
tRISE
A Port rise time
A-Port
1.2
ns
HPD channel enabled
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A And x_B PORTS) VCCA = 3.3 V
tPHL
Propagation delay
tPLH
Propagation delay
tFALL
tRISE
F(MAX)
A to B
300
B to A
400
A to B
260
B to A
415
A Port fall time
A-Port
SCL/SDA channels enabled
B Port fall time
B-Port
225
A Port rise time
A-Port
305
B Port fall time
B-Port
415
Maximum switching frequency
160
400
ns
ns
ns
ns
kHz
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) VCCA = 3.3V
tPHL
Propagation delay
tPLH
Propagation delay
tFALL
tRISE
A to B
375
B to A
305
A to B
13.8
µs
B to A
16.6
ns
CEC channel enabled
160
ns
A Port fall time
A-Port
B Port fall time
B-Port
170
A Port rise time
A-Port
305
ns
B Port rise time
B-Port
28
µs
ns
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) VCCA = 3.3 V
tPHL
Propagation delay
B to A
14.2
µs
tPLH
Propagation delay
B to A
9.2
µs
tFALL
A Port fall time
A-Port
1.1
ns
tRISE
A Port rise time
A-Port
1.1
ns
HPD channel enabled
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60
10
50
0
40
-10
Amplitude (V)
Amplitude (V)
6.7 Typical Characteristics
30
20
-20
-30
10
-40
0
-50
-10
-15
15
45
75
105
135
Time (nS)
165
195
-60
-15
225
75
105
135
Time (nS)
165
195
225
Figure 2. IEC Clamping Waveform –8kv Contact
VCC5V = 4.5V
VCC5V = 5.0V
VCC5V = 5.5V
0
-3
-6
-9
-12
0
0.2
0.4
0.6 0.8
1
1.2 1.4
Input Voltage, VCT_HPD (V)
1.6
1.8
-15
1E+7
2
Figure 3. CT_HPD VIH
1E+10
1000
D2+ to CLKD2+ to D2-
900
Switch Resistance (m:)
-20
1E+8
1E+9
Frequency (Hz)
Figure 4. Insertion Loss, Data Line to GND
0
Magnitude (dB)
45
3
Magnitude (dB)
V5V_OUT (V)
Figure 1. IEC Clamping Waveform +8kv Contact
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
15
-40
-60
-80
800
700
600
500
400
300
200
-100
100
-120
10000
100000 1000000 1E+7
1E+8
Frequency (Hz)
1E+9
Figure 5. Channel-to-Channel Crosstalk
12
1E+10
0
-60
-45
-30
-15
0
15
30
45
Temperature (qC)
60
75
90
Figure 6. Switch Resistance vs Temperature,
Iswitch at Approximately 55 mA
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Typical Characteristics (continued)
100
300
4.5V
5.0V
5.5V
2.5V
3.3V
5.0V
250
IIO (Leakage) Current (nA)
0
-50
-100
-150
-200
200
150
100
50
0
-250
-300
-60
-30
0
30
Temperature (qC)
60
-50
-60
90
-30
Figure 7. Load Switch Ileakage vs Temperature
4
400
3
300
2
200
1
100
0
-20
0
20
40
60
80
Time (PS)
100
120
140
Voltage (V)
700
CT_HPD
VCC5V
V5V_OUT
I5V_OUT
7.5
6
Voltage (V)
5
-1
-40
90
Figure 8. TMDS Line IIO vs Temperature
VCC5V
V5V_OUT 600
I5V_OUT
500
6
60
9
700
Current (A)
7
0
30
Temperature (qC)
600
500
4.5
400
3
300
1.5
200
0
0
100
-100
160
-1.5
-40
Figure 9. Short-Circuit Response Time (Powered-Up to
Short)
-20
0
20
40
60
80
Time (PS)
100
120
140
0
160
Figure 10. Current Limit Response Time (Switch Enabled to
Short)
0
2
IVCC5V
1.8
-2E-9
1.6
1.4
-4E-9
Current (A)
Capacitance (pF)
Current (mA)
IOUT (Leakage) Current (nA)
50
1.2
1
0.8
-6E-9
-8E-9
0.6
0.4
-1E-8
0.2
-1.2E-8
0
0
0.5
1
1.5
2
2.5
3
3.5
Bias Voltage (V)
4
4.5
Figure 11. Capacitance vs Bias Voltage
5
5.5
0
1
2
3
V5V_OUT (V)
4
5
Figure 12. Load Switch ILEAKAGE_REVERSE vs V5V_OUT
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7 Detailed Description
7.1 Overview
The TPD12S016 is a single-chip HDMI interface device with auto-direction sensing I2C voltage level shifting
buffers, a load switch, and integrated high-speed ESD protection clamps. The device pin mapping matches the
HDMI connector with four differential pairs and control lines. This device offers eight low-capacitance ESD
clamps, allowing HDMI 1.4 data rates. The integrated ESD circuits provides matching between each differential
signal pair, which allows an advantage over discrete ESD solutions where variations between ESD protection
clamps degrade the differential signal quality. The TPD12S016 provides a current limited 5-V output (5V_OUT)
for sourcing the HDMI power line. The current limited 5-V output supplies up to 55 mA to the HDMI receiver. The
control of 5V_OUT and the hot plug detect (HPD) circuitry is independent of the LS_OE control signal, and is
controlled by the CT_HPD pin. This independent CT_HPD control enables the detection scheme (5V_OUT and
HPD) to be active before enabling the HDMI link. An internal 3.3 V node powers the CEC pin eliminating the
need for a 3.3 V supply on board.
The TPD12S016 integrates all the external termination resistors at the HPD, CEC, SCL, and SDA lines. There
are three non-inverting bidirectional voltage level translation (VLT) circuits for the SDA, SCL, and CEC lines.
Each have a common power rail (VCCA) on the A side from 1.1 V to 3.6V. On the B side, the SCL_B and SDA_B
each have an internal 1.75 kΩ pull up connected to the 5-V rail (5V_OUT). The SCL and SDA pins meet the I2C
specification and drive up to 750-pF capacitive loads exceeding the HDMI 1.4 specifications. The CEC_B pin has
an internal 27-kΩ pull up resistor to the internal 3.3-V supply rail. The HPD_B port has a glitch filter to avoid false
detection due to plug bouncing during the HDMI connector insertion.
The TPD12S016 offers a reverse current blocking feature at the 5V_OUT pin. In the fault conditions, such as
when two HDMI transmitters connect to the same HDMI cable, the TPD12S016 ensures that the system is safe
from powering up through an external HDMI transmitter. The SCL_B, SDA_B, CEC_B pins also feature reversecurrent blocking when the system is powered off.
7.2 Functional Block Diagram
VCC5V
VCCA
5 V_OUT
55
55mA
mA
Load
Load Switch
Switch
CT_HPD 1
CLK-
CLK+
D2-
D2+
D1-
D1+
D0-
D0+
470 kW
LS_OE 1
LDO
VCCA
5 V_OUT
VCCA
SCL_A
HPD_A
SCL_B
3.3 V (internal) 2
5 V_OUT
10 kW
CEC_A
ERC
26 kW
CEC_B
ERC
10 kW
1.75 kW
SDA_B
LDO
1. LS_OE & CT_HPD are active high signal
LS_OE 1
2. ‘3.3
‘
V (Internal)’ is an internally generated
voltage node for the CEC_B output buffer
supply reference. An LDO generates this
3.3 V from 5VOUT when LS_OE = H &
CT_CP_HPD = H.
470 kW
14
HPD_B
10 kW
1.75 kW
VCCA
SDA_A
5 V_OUT
ERC
10 kW
VCCA
3.3 V (internal) 2
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7.3 Feature Description
7.3.1 Conforms to HDMI Compliance Tests Without any External Components
The TPD12S016 has integrated pullup or pulldown resistors on the DDC, CEC, and HPD lines that conform to
the HDMI 7.13 and 7.15 Compliance Tests without the designer needing to use any external components to
TPD12S016.
7.3.2 IEC 61000-4-2 ESD Protection
In many cases, the core ICs, such as the scalar chipset, may not have robust ESD cells to sustain system-level
ESD strikes. In these cases, the TPD12S016 provides the desired system-level ESD protection, such as the IEC
61000-4-2 Level 4 ESD protection of ±8-kV Contact rating by absorbing the energy associated with the ESD
strike.
7.3.3 Supports HDMI 1.4 Data Rate
The high-speed TMDS pins of the TPD12S016 add only 1.0-pF (for PW package) or 1.2-pF (for RKT package) of
capacitance to the TMDS lines. An Insertion Loss –3 dB point that is greater than 3 GHz provides enough
bandwidth to pass HDMI 1.4 TMDS data rates.
7.3.4 Matches Class D and Class C Pin Mapping
The PW and RKT packages offer seamless layout routing options to eliminate the routing glitch for the differential
signal pairs. The pin mapping follows the same order as the HDMI connector pin mapping.
7.3.5 8-Channel ESD Lines for Four Differential Pairs with Ultra-low Differential Capacitance Matching
(0.05 pF)
Excellent intra-pair capacitance matching of 0.05 pF provides ultra low intra-pair skew, which allows an
advantage over discrete ESD solutions where variations between ESD protection clamps can degrade the
differential signal quality.
7.3.6 On-Chip Load Switch With 55-mA Current Limit Feature at the HDMI 5V_OUT Pin
The TPD12S016 provides a current limited 5-V output (5V_OUT) for sourcing the HDMI power line. The current
limited 5-V output supplies up to 55 mA to the HDMI receiver. The control of 5V_OUT and the HPD circuitry is
independent of the LS_OE control signal, and is controlled by the CT_HPD pin. This independent CT_HPD
control enables the detection scheme (5V_OUT and HPD) to be active before enabling the HDMI link.
7.3.7 Auto-direction Sensing I2C Level Shifter With One-Shot Circuit to Drive a Long HDMI Cable (750-pF
Load)
The TPD12S016 contains three bidirectional open-drain buffers specifically designed to support uptranslation/down-translation between the low voltage, VCCA side DDC-bus and the 5-V DDC-bus or 3.3-V CEC
line. The HDMI cable side of the DDC lines incorporates rise-time accelerators to support a high capacitive load
on the HDMI cable side. The rise time accelerators boost the cable side DDC signal independent of which side of
the bus is releasing the signal.
7.3.8 Back-Drive Protection on HDMI Connector Side Ports
The TPD12S016 offers a reverse current blocking feature at the 5V_OUT pin. In fault conditions, such as when
two HDMI transmitters connect to the same HDMI cable, the TPD12S016 ensures that the system is safe from
powering up through an external HDMI transmitter. The SCL_B, SDA_B, CEC_B pins also feature reversecurrent blocking when the system is powered off.
7.3.9 Integrated Pullup and Pulldown Resistors per HDMI Specification
The system is designed to work properly according to the HDMI 1.4 specification with no external pullup resistors
on the DDC, CEC, and HPD lines.
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Feature Description (continued)
7.3.10 Space Saving 24-Pin RKT Package and 24-TSSOP Package
When compared to discrete ESD solutions, the fully integrated port protection offered by TPD12S016 reduces
the overall area required to fully protect an HDMI transmitter port.
7.3.11 DDC/CEC LEVEL SHIFT Circuit Operation
The TPD12S016 enables DDC translation from VCCA (system side) voltage levels to 5-V (HDMI cable side)
voltage levels without degradation of system performance. The TPD12S016 contains two bidirectional open-drain
buffers specifically designed to support up-translation/down-translation between the low voltage, VCCA side DDCbus and the 5-V DDC-bus. The port B I/Os are over-voltage tolerant to 5.5 V, even when the device is unpowered. After power-up and with the LS_OE and CT_HPD pins HIGH, a LOW level on port A (below
approximately VILC = 0.08 × VCCA V) turns the corresponding port B driver (either SDA or SCL) on and drives port
B down to VOLB V. When port A rises above approximately 0.10 × VCCA V, the port B pulldown driver is turned off
and the internal pullup resistor pulls the pin HIGH. When port B falls first and goes below 0.3 × 5 VOUT V, a
CMOS hysteresis input buffer detects the falling edge, turns on the port A driver, and pulls port A down to
approximately VOLA = 0.16 × VCCA V. The port B pulldown is not enabled unless the port A voltage goes below
VILC. If the port A low voltage goes below VILC, the port B pulldown driver is enabled until port A rises above (VILC
+ ΔVT-HYSTA), then port B, if not externally driven LOW, will continue to rise being pulled up by the internal pullup
resistor.
5 VOUT
VCCA
CMP2
IACCEL
CMP1
RPUA
RPUB
150 mV
ACCEL
GLITCH
FILTER
Port B
l
DDC
Lines
Only
Port A
700 mV
300 mV
Figure 13. DDC/CEC Level Shifter Block Diagram
7.3.12 DDC/CEC Level Shifter Operational Notes For VCCA = 1.8 V
•
•
•
•
•
•
•
•
16
The threshold of CMP1 (see Figure 13) is approximately 150 mV ± the 40 mV of total hysteresis.
The comparator will trip for a falling waveform at approximately 130 mV.
The comparator will trip for a rising waveform at approximately 170 mV.
To be recognized as a zero, the level at Port A must first go below 130 mV (VILC in spec) and then stay below
170 mV (VILA in spec).
To be recognized as a one, the level at A must first go above 170 mV and then stay above 130 mV.
VILC is set to 117 mV in Electrical Characteristics Table to give some margin to the 130 mV.
VILA is set to 148 mV in the Electrical Characteristics table to give some margin to the 170 mV.
VIHA is set to 70% of VCCA to be consistent with standard CMOS levels.
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Feature Description (continued)
6
5.5
B Port
5
4.5
4
Voltage (V)
3.5
3
2.5
A Port
2
1.5
1
0.5
0
-0.5
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
t - Time (Ps)
Figure 14. DDC Level Shifter Operation (B To A Direction)
7.3.13 Rise-Time Accelerators
The HDMI cable side of the DDC lines incorporates rise-time accelerators to support high capacitive load (up to
750 pF) on the HDMI cable side. The rise time accelerators boost the cable side DDC signal independent of
which side of the bus is releasing the signal.
7.3.14 Noise Considerations
Ground offset between the TPD12S016 ground and the ground of devices on port A of the TPD12S016 must be
avoided. The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of sinking 3 mA of
current at 0.4 V will have an output resistance of 133 Ω or less (R = E / I). Such a driver will share enough
current with the port A output pulldown of the TPD12S016 to be seen as a LOW as long as the ground offset is
zero. If the ground offset is greater than 0 V, then the driver resistance must be less. Since VILC can be as low as
90 mV at cold temperatures and the low end of the current distribution, the maximum ground offset should not
exceed 50 mV. Bus repeaters that use an output offset are not interoperable with the port A of the TPD12S016
as their output LOW levels will not be recognized by the TPD12S016 as a LOW. If the TPD12S016 is placed in
an application where the VIL of port A of the TPD12S016 does not go below its VILC it will pull port B LOW initially
when port A input transitions LOW but the port B will return HIGH, so it will not reproduce the port A input on port
B. Such applications should be avoided. Port B is interoperable with all I2C-bus slaves, masters and repeaters.
7.3.15 Resistor Pullup Value Selection
The system is designed to work properly with no external pullup resistors on the DDC, CEC, and HPD lines.
7.4 Device Functional Modes
The LS_OE and CT_HPD are active-high enable pins. They control the TPD12S016 power saving options
according to Table 1.
Table 1. Power Saving Options (1)
LS_OE CT_HPD
(1)
VCCA
VCC5V
A-SIDE
PULL-UPS
DDC, BSIDE
PULL-UPS
CEC_B
PULLUPS
CEC
LDO
LOAD SW
AND HPD
DDC/ CEC
VLTs
ICCA
TYP
ICC5V
TYP
COMMENTS
L
L
1.8 V
5.0 V
Off
Off
Off
Off
Off
Off
1 µA
1 µA
Fully Disabled
L
H
1.8 V
5.0 V
On
On
Off
Off
On
Off
1 µA
30 µA
Load Switch on
H
L
1.8 V
5.0 V
Off
Off
Off
Off
Off
Off
1 µA
1 µA
Not a Valid State
H
H
1.8 V
5.0 V
On
On
On
On
On
On
13 µA
200 µA
Fully On
X
X
0V
0V
High-Z
High-Z
High-Z
Off
Off
Off
0
0
Power Down
X
X
1.8 V
0V
High-Z
High-Z
High-Z
Off
Off
Off
0
0
Power Down
X
X
0V
5.0 V
High-Z
High-Z
High-Z
Off
Off
Off
0
0
Power Down
X = Don’t Care, H = Signal High, and L = Signal Low
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
TPD12S016 provides IEC 61000-4-2 Level 4 Contact ESD rating to the HDMI 1.4 transmitter port. Buffered VLT's
translate DDC and CEC channels bidirectionally. The system is designed to work properly with no external pullup
resistors on the DDC, CEC, and HPD lines. The CEC line has an integrated 3.3-V rail, eliminating the need for a
3.3-V supply on board.
8.2 Typical Application
The TPD12S016 is placed as close as possible to the HDMI connector to provide voltage level translation,
5V_OUT current limiting and overall ESD protection for the HDMI controller.
8.2.1 Example 1: HDMI Controller Using One Control Line
In the example shown in Figure 15, the HDMI driver chip is controlling the TPD12S016 through only one control
line, CT_HPD. In this mode the HPD_A to LS_OE pin are connected as shown in the oval dotted line of
Figure 15. To fully enable TPD12S016, set CT_HPD above VIH. To fully disable TPD12S016, set CT_HPD below
VIL.
1.2 V to 3.3 V
HDMI Connector
0.1 mF
VCCA CT_HPD LS_OE
HOT PLUG 1
UTILITY 2
TMDS_D2+ 3
GND 4
TMDS_D2- 5
TMDSD1+ 6
GND 7
TMDSD1- 8
HPD_B
TMDS_D0+ 9
GND 10
D0+
TMDS_D0- 11
TMDS_CLK+ 12
GND 13
TMDS_CLK-14
D0-
HPD_A
D2+
D2D1+
D1-
HDMI Controller
TPD12S016
CLK+
CLK-
CEC 15
GND 16
SCL 17
CEC_B
SCL_B
SCL_A
SDA 18
P5V 19
GND 20
SDA_B
SDA_A
5V_OUT
VCC5V
CEC_A
0.1 mF
0.1 mF
-
Figure 15. TPD12S016 with an HDMI Controller Using One GPIO for HDMI Interface Control
18
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Typical Application (continued)
8.2.1.1 Design Requirements
For this example, use the following table as input parameters:
Table 2. HDMI Controller Using One Control Line Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Voltage on VCCA
1.8 V
Voltage on VCC5V
5.0 V
Drive CT_HPD low (disabled)
–0.5 V to 0.4 V
Drive CT_HPD high (enabled)
A to B
Drive a logical 1
B to A
A to B
Drive a logical 0
B to A
1.0 V to 1.8 V
SCL and SDA
1.26 V to 1.8 V
CEC
SCL and SDA
3.5 V to 5.0 V
CEC
2.31 V to 3.3 V
SCL and SDA
–0.5 V to 0.117 V
CEC
SCL and SDA
–0.5 V to 1.5 V
CEC
–0.5 V to 0.99 V
8.2.1.2 Detailed Design Procedure
To begin the design process, the designer needs to know the VCC5V voltage range and the logic level, VCCA,
voltage range.
8.2.1.3 Application Curves
Figure 16. Eye Diagram Using EVM Without TPD12S016 for
the TMDS Lines at 1080p, 340 MHz Pixel Clock, 3.4 Gbps
Figure 17. Eye Diagram Using EVM With TPD12S016 for
the TMDS Lines at 1080p, 340 MHz Pixel Clock, 3.4 Gbps
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8.2.2 Example 2: HDMI Controller Using CT_HPD and LS_OE
Some HDMI driver chips may have two GPIOs to control the HDMI interface chip. In this case a flexible power
saving mode can be implemented. The load switch can be activated by CT_HPD while the level shifters are
inactive, using LS_OE. This results in TPD12S016 drawing only approximately 30 µA, a reduction of 170 µA from
being fully on. After a hot plug is detected, the HDMI controller can enable the rest of the HDMI interface chip
using LS_OE.
1.2 V to 3.3 V
0.1 mF
HOT PLUG 1
VCCA CT_HPD LS_OE
HPD_B
HPD_A
UTILITY 2
TMDS_D2+ 3
D2+
GND 4
D2-
H D M I C o n ne c to r
TMDS_D2- 5
TMDSD1+ 6
D1+
GND 7
TMDSD1- 8
D1TPD12S016
TMDS_D0+ 9
HDMI Controller
D0+
GND 10
TMDS_D0 - 11
D0-
TMDS_CLK+ 12
CLK+
GND 13
TMDS_CLK - 14
CLK-
CEC 15
CEC_B
CEC_A
SCL_A
GND 16
SCL 17
SCL_B
SDA 18
SDA_B
SDA_A
P5V 19
5V_OUT
VCC5V
GND 20
0.1 mF
0.1 mF
Figure 18. TPD12S016 with an HDMI Controller Using Two GPIOs For HDMI Interface Control
8.2.2.1 Design Requirements
For this example, use Table 3 for input parameters:
Table 3. HDMI Controller Using CT_HPD and LS_OE Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Voltage on VCCA
3.3 V
Voltage on VCC5V
5.0 V
Drive CT_HPD low (disabled)
–0.5 V to 0.4 V
Drive LS_OE low (disabled)
Drive CT_HPD high (enabled)
1.0 V to 3.3 V
Drive LS_OE high (enabled)
A to B
Drive a logical 1
B to A
A to B
Drive a logical 0
B to A
20
SCL and SDA
2.31 V to 3.3 V
CEC
SCL and SDA
3.5 V to 5.0 V
CEC
2.31 V to 3.3 V
SCL and SDA
–0.5 V to 0.214 V
CEC
SCL and SDA
–0.5 V to 1.5 V
CEC
–0.5 V to 0.99 V
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8.2.2.2 Detailed Design Procedure
To begin the design process, the designer needs to know the VCC5V voltage range and the logic level, VCCA,
voltage range.
8.2.2.3 Application Curves
Refer to Application Curves for related application curves.
9 Power Supply Recommendations
TPD12S016 has two power input pins: VCC5V and VCCA. It can operate normally with VCC5V between 4.5 V and
5.5 V; and VCCA between 1.1 V and 3.6 V. Thus, the power supply (with a ripple of VRIPPLE) requirement for
TPD12S016 for VCC5V is between 4.5 V + VRIPPLE and 5.5 V – VRIPPLE; and for VCCA it is between 1.1 V + VRIPPLE
and 3.6 V – VRIPPLE.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures. Therefore, the PCB designer needs to minimize the possibility of EMI
coupling by keeping any unprotected traces away from the protected traces which are between the TVS
and the connector.
Route the protected traces as straight as possible.
Avoid using VIAs between the connecter and an I/O protection pin on TPD12S016.
Avoid 90º turns in traces.
– Electric fields tend to build up on corners, increasing EMI coupling.
Minimize impedance on the path to GND for maximum ESD dissipation.
The capacitors on VBUS and VOTG_IN should be placed close to their respective pins on TPD12S016.
10.2 Layout Examples
10.2.1 TPD12S016RKT
TPD12S016
LEGEND
VCCA
CEC_A
VIA to Power Ground Plane
Pin to Ground
SCL_A
SDA_A
HPD_A
LS_OE
Signal VIA
Top Layer
copper
Mid Layer copper
HDMI Conn.
D2
D2+
1
D2D1+
D1
D1D0+
D0
D0CLK+
Bottom Layer copper
VCC5V CLK
CLKCEC_B
Reserved*
SCL_B
SDA_B
CT_HPD
5V_OUT
HPD_B
* If unused, tie Reserve Pin to Ground with 75Ω resistor
Figure 19. TPD12S016RKT Layout Example
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Layout Examples (continued)
Routing with TPD12S016RKT requires three layers. Vias are an integral part of layout for such a design. Proper
placement of vias can eliminate exposing the system unnecessarily to an ESD event. The example shown above
routes the TMDS lines directly from the connector to the protection pins before using vias to an internal layer.
This helps promote ESD energy dissipation at the TPD12S016 protection pins. Note that while there is a via
between the connector and the DDC/CEC/HPD lines, the traces terminate at the protection pins, leaving no other
path for ESD energy to dissipate except at the TPD12S016 protection pins. All ground pins should have a large
via near them connecting to as many internal and external ground planes as possible to reduce any impedance
between TPD12S016 and ground. Tenting of VIAs near to SMD pads should be done to eliminate any solderwicking during PCB assembly.
10.2.2 TPD12S016PW
D2+
D2-
LEGEND
VIA to 5 V Power Plane
D1+
D1-
VIA to Power Ground Plane
D0+
D0-
Signal VIA
Pin to Ground
Top Layer copper
Bottom Layer copper
CLK+
CLKCEC
SCL
D2+
SDA
D2D1+
HPD
LS_OE
D1D0+
D0CLK+
CLKCEC
Reserved*
SCL
SDA
VCC5V
CT_HPD
+5 V
HPD
TPD12S016
HDMI Conn.
* If unused, tie Reserve Pin to Ground with 75Ω resistor
Figure 20. TPD12S016PW Layout Example
The TPD12S016PW can be routed on a single layer. HDMI connector pin matching has been arranged to allow
for a flow through routing style. All ground pins should have a large via near them connecting to as many internal
and external ground planes as possible to reduce any impedance between TPD12S016 and ground. Tenting of
vias near to SMD pads should be done to eliminate any solder-wicking during PCB assembly.
22
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD12S016PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PN016
TPD12S016RKTR
ACTIVE
UQFN
RKT
24
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
PN016
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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