TPD12S520DBTR

Sample & Buy Product Folder Technical Documents Support & Community Tools & Software TPD12S520 SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 TPD12S520 Single-Chip HDMI Receiver Port Protection and Interface Device 1 Features 3 Description • The TPD12S520 is a single-chip electro-static discharge (ESD) circuit protection device for the highdefinition multimedia interface (HDMI) receiver port. While providing ESD protection with transient voltage suppression (TVS) diodes, the TVS protection adds little or no additional glitch in the high-speed differential signals. The high-speed transition minimized differential signaling (TMDS) ESD protection lines add only 0.8-pF capacitance. 1 • • • • • • • • • IEC 61000-4-2 Level 4 ESD Protection – ±8-kV Contact Discharge on External Lines Single-Chip ESD Solution for HDMI Driver 12 Channel ESD Protection Diodes Supports All HDMI 1.3 and HDMI 1.4b Data Rates (–3 dB Frequency > 3 GHz) 0.8-pF Capacitance for the High Speed TMDS Lines 0.05-pF Matching Capacitance Between the Differential Signal Pair 38-Pin TSSOP Provides Seamless Layout Option with HDMI Connector 24-Pin WQFN Package for Space Constrained Applications Backdrive Protection Lead-Free Package 2 Applications • • • • Video Interface Consumer Electronics Displays and Digital Televisions Handheld Displays The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage levelshifter IC. The control line TVS diodes add 3.5-pF capacitance to the control lines. The 38-pin DBT package offers a seamless layout routing option to eliminate the routing glitch for the differential signal pairs. The DBT package pitch (0.5 mm) matches with the HDMI connector pitch. In addition, the pin mapping follows the same order as the HDMI connector pin mapping. This HDMI receiver port protection and interface device is designed specifically for HDMI receiver-interface protection. The 24-pin RMN package offers flow through routing using only two layers for highly integrated, spaceefficient full HDMI protection. Device Information(1) DEVICE NAME PACKAGE TPD12S520 BODY SIZE (NOM) TSSOP (38) 6.40 mm × 9.70 mm WQFN (24) 4.50 mm × 1.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Circuit Protection Scheme VLV VLV 100 kW VLV 47 kW VLV 47 kW VLV 5V VLV 47 kW 5V 10 kW 47 kW 5V_SUPPLY 0.1 uF 0.1 uF LV_SUPPLY 5V 47 kW 3.3 V 27 kW NC ESD_BYP 0.1 uF D0+ GND D0D1+ GND D1- Core Scalar Chip D2+ GND D2D3+ GND CEC_IN DCLK_IN DDAT_IN HPD_IN CEC_OUT DCLK_OUT DDAT_OUT HPD_OUT 1 kW D3CE_R NC D_CLK D_DAT GND 5V HTP_D 0.1 uF 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD12S520 SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 7.3 Feature Description................................................... 8 7.4 Device Functional Modes.......................................... 8 8 Application and Implementation .......................... 9 8.1 Application Information.............................................. 9 8.2 Typical Application ................................................... 9 9 Power Supply Recommendations...................... 10 10 Layout................................................................... 11 10.1 Layout Guidelines ................................................. 11 10.2 Layout Example .................................................... 11 11 Device and Documentation Support ................. 12 Detailed Description .............................................. 7 11.1 Trademarks ........................................................... 12 11.2 Electrostatic Discharge Caution ............................ 12 11.3 Glossary ................................................................ 12 7.1 Overview ................................................................... 7 7.2 Functional Block Diagram ......................................... 7 12 Mechanical, Packaging, and Orderable Information ........................................................... 12 4 Revision History Changes from Revision E (September 2014) to Revision F Page • Added clarification to HDMI data rates................................................................................................................................... 1 • Added clarification to HDMI data rates................................................................................................................................... 8 Changes from Revision D (December 2013) to Revision E • Page Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 Changes from Revision C (April 2009) to Revision D Page • Added new application to Applications section. .................................................................................................................... 1 • Added RMN Package to Datasheet. ..................................................................................................................................... 1 • Updated RMN Package. ........................................................................................................................................................ 1 • Updated Pin Description Table. ............................................................................................................................................. 4 • Added additonal graphs to Typical Performance section. ..................................................................................................... 6 2 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 TPD12S520 www.ti.com SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 5 Pin Configuration and Functions Pin Functions TYPE ESD LEVEL 12 PWR 2 kV (1) Bias for TMDS protection 2 13 PWR 2 kV (1) Bias for CE/DDC/HOTPLUG level shifters GND, TMDS_GND 3, 5, 8, 11,14, 25, 28, 31, 34, 36 6, 9, 10, 14, 17 GND NA TMDS_D2+ 4, 35 18 IO 8 kV (3) TMDS 0.8-pF ESD protection (4) IO 8 kV (3) TMDS 0.8-pF ESD protection (4) 8 kV (3) TMDS 0.8-pF ESD protection (4) (3) TMDS 0.8-pF ESD protection (4) NAME DBT RMN 5V_SUPPLY 1 LV_SUPPLY TMDS_D2– TMDS_D1+ 15 IO 16 IO 8 kV TMDS_D0+ 10, 29 8 IO 8 kV (3) TMDS 0.8-pF ESD protection (4) IO 8 kV (3) TMDS 0.8-pF ESD protection (4) (3) TMDS 0.8-pF ESD protection (4) TMDS 0.8-pF ESD protection (4) 12, 27 7 TMDS_CK+ 13, 26 5 IO 8 kV TMDS_CK– 15, 24 4 IO 8 kV (3) (1) LV_SUPPLY referenced logic level into ASIC CE_REMOTE_IN 16 20 IO 2 kV DDC_CLK_IN 17 21 IO 2 kV (1) LV_SUPPLY referenced logic level into ASIC DDC_DAT_IN 18 22 IO 2 kV (1) LV_SUPPLY referenced logic level into ASIC IO 2 kV (1) LV_SUPPLY referenced logic level into ASIC 8 kV (3) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD (5) to connector HOTPLUG_DET_OUT (4) (5) 7, 32 19 TMDS ESD and parasitic GND return (2) 9, 30 HOTPLUG_DET_IN (2) (3) 6, 33 DESCRIPTION TMDS_D1– TMDS_D0– (1) PIN NO. 19 20 23 24 IO Human body model (HBM) per MIL-STD-883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-μF ceramic capacitor connected to GND. These pins should be routed directly to the associated GND pins on the HDMI connector, with single-point ground vias at the connector. Standard IEC 61000-4-2, CDISCHARGE = 150 pF, RDISCHARGE = 330 Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-μF ceramic capacitor connected to GND. These two pins must be connected together inline on the PCB. This output can be connected to an external 0.1-μF ceramic capacitor, resulting in an increased ESD withstand voltage rating. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 3 TPD12S520 SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 www.ti.com Pin Functions (continued) PIN NO. TYPE ESD LEVEL 1 IO 8 kV (3) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector 22 2 IO 8 kV (3) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector CE_REMOTE_OUT 23 3 IO 8 kV (3) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector ESD_BYP 37 11 IO 2 kV (1) ESD bypass. This pin must be connected to a 0.1-μF ceramic capacitor. NC 38 NAME DBT RMN DDC_DAT_OUT 21 DDC_CLK_OUT NA DESCRIPTION No connection 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX Supply voltage –0.3 6 VI/O DC voltage at any channel input –0.5 6 V TA Operating Free Air Temperature –40 85 °C Tstg Storage temperature range –65 150 °C V5V_SUPPLY VLV_SUPPLY (1) UNIT V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per MIL-STD883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ (1) See Pin Configuration and Functions ±2000 IEC 61000-4-2 Contact Discharge (2) See Pin Configuration and Functions ±8000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TA Operating free-air temperature 5V_SUPPLY Operating supply voltage LV_SUPPLY Bias supply voltage 4 TYP –40 Submit Documentation Feedback MAX UNIT 85 °C GND 5 5.5 V 1 3.3 5.5 V Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 TPD12S520 www.ti.com SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 6.4 Thermal Information TPD12S520 THERMAL METRIC (1) DBT RMN 38 PINS 24 PINS RθJA Junction-to-ambient thermal resistance 83.6 80.8 RθJC(top) Junction-to-case (top) thermal resistance 29.8 36.4 RθJB Junction-to-board thermal resistance 44.7 27.1 ψJT Junction-to-top characterization parameter 2.9 1.4 ψJB Junction-to-board characterization parameter 44.1 27.0 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) TYP MAX I5V PARAMETER Operating supply current 5V_SUPPLY = 5 V TEST CONDITIONS MIN 1 5 UNIT µA ILV Bias supply current LV_SUPPLY = 3.3 V 1 2 mA IOFF OFF-state leakage current, level-shifting NFET LV_SUPPLY = 0 V 0.1 1 µA 0.1 5 µA 95 140 mV TMDS_D[2:0]+/–, IBACK DRIVE Current conducted from output pins to V_SUPPLY rails when powered down TMDS_CK+/–, 5V_SUPPLY < VCH_OUT CE_REMOTE_OUT, DDC_DAT_OUT, DDC_CLK_OUT, HOTPLUG_DET_OUT VON Voltage drop across level-shifting NFET when ON VF Diode forward voltage VCL Channel clamp voltage at ±8 kV HBM ESD TA = 25°C (1) (2) RDYN Dynamic resistance I = 1 A, TA = 25°C (3) ILEAK TMDS channel leakage current TA = 25°C (1) TMDS channel input capacitance 5V_SUPPLY= 5 V, Measured at 1 MHz, TMDS channel input capacitance matching 5V_SUPPLY= 5 V, Measured at 1 MHz, CMUTUAL Mutual capacitance between signal pin and adjacent signal pin 5V_SUPPLY= 0 V, Measured at 1 MHz, CIN Level-shifting input capacitance, capacitance to GND 5V_SUPPLY= 0 V, Measured at 100 KHz, CIN, TMDS ΔCIN, TMDS (1) (2) (3) (4) LV_SUPPLY = 2.5 V, VS = GND, IDS = 3 mA 75 IF = 8 mA, Top diode 1 TA = 25°C (1) Bottom diode 1 Positive transients 9 Negative transients -9 Positive transients 0.6 Negative transients 0.5 VBIAS = 2.5 V (1) VBIAS = 2.5 V (1) (4) VBIAS = 2.5 V (1) VBIAS = 2.5 V (1) V V Ω 0.01 1 µA 0.8 1.0 pF 0.05 pF 0.07 pF DDC 3.5 4 CEC 3.5 4 HP 3.5 4 pF This parameter is specified by design and verified by device characterization Human-Body Model (HBM) per MIL-STD-883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ These measurements performed with no external capacitor on ESD_BYP. Intrapair matching, each TMDS pair (i.e., D+, D–) Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 5 TPD12S520 SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 www.ti.com 6.6 Typical Characteristics 10 80 0 70 ±10 60 ±20 50 ±30 Voltage (V) Voltage (V) 90 40 30 ±40 ±50 20 ±60 10 ±70 0 ±80 ±10 ±90 ±15 0 15 30 45 60 75 90 105 120 135 150 165 -15 180 0 15 30 45 60 75 Time (nS) 90 105 120 135 150 165 180 Time (nS) C001 C002 Figure 1. TPD12S520RMN IEC Clamping Waveforms +8kV Contact Figure 2. TPD12S520RMN IEC Clamping Waveforms -8kV Contact 500 1.2 450 1.1 1 400 0.9 350 Capacitance (pF) Current (nA) 0.8 300 250 200 0.7 0.6 0.5 0.4 150 0.3 100 0.2 50 0.1 0 0 -50 -35 -20 -5 10 25 40 55 70 85 0 0.5 1 1.5 2 Temperature (ƒC) 2.5 3 3.5 4 4.5 5 Bias Voltage (V) C007 C005 Figure 3. ILEAK vs. Temperature VIN = 5.0V Figure 4. Capacitance vs. VBIAS 3 0 ±3 ±6 Gain (dB) ±9 ±12 ±15 ±18 ±21 ±24 ±27 ±30 ±33 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) C004 Figure 5. Insertion Loss Performance Across Frequency 6 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 TPD12S520 www.ti.com SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 7 Detailed Description 7.1 Overview The TPD12S520 is a single-chip ESD solution for the HDMI receiver port. In many cases the core ICs, such as the scalar chipset, may not have robust ESD cells to sustain system-level ESD strikes. In these cases, the TPD12S520 provides the desired system-level ESD protection, such as the IEC61000-4-2 (Level 4) ESD, by absorbing the energy associated with the ESD strike. While providing the ESD protection, the TPD12S520 adds little or no additional glitch in the high-speed differential signals (see Figure 7 and Figure 8). The high-speed TMDS lines add only 0.8-pF capacitance to the lines. In addition, the monolithic integrated circuit technology ensures that there is excellent matching between the two-signal pair of the differential line. This is a direct advantage over discrete ESD clamp solutions where variations between two different ESD clamps may significantly degrade the differential signal quality. The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line ESD clamps add 3.5-pF capacitance to the control lines. The 38-pin DBT package offers a seamless layout routing option to eliminate the routing glitch for the differential signal pairs. DBT package pitch (0.5 mm) matches with HDMI connector pitch. In addition, pin mapping follows the same order as the HDMI connector pin mapping. The 24-pin RMN package offers flow through routing using only two layers for highly integrated, space-efficient full HDMI protection. 7.2 Functional Block Diagram ESD_BYP 5V_SUPPLY TMDS_D2+ TMDS_D1+ TMDS_D0+ TMDS_CK+ TMDS_GND TMDS_GND TMDS_GND TMDS_GND TMDS_D2– TMDS_D1– TMDS_D0– TMDS_CK– LV Supply CE_REMOTE_IN LV Supply CE_REMOTE_OUT LV Supply DDC_CLK_IN DDC_DAT_IN DDC_DAT_OUT LV Supply DDC_CLK_OUT HOTPLUG_DET_IN HOTPLUG_DET_OUT Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 7 TPD12S520 SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 www.ti.com 7.3 Feature Description 7.3.1 ±8-kV Contact ESD Protection on External Lines In many cases, the core ICs, such as the scalar chipset, may not have robust ESD cells to sustain system-level ESD strikes. In these cases, the TPD12S520 provides the desired system-level ESD protection, such as the IEC61000-4-2 (Level 4) ESD, by absorbing the energy associated with the ESD strike. 7.3.2 Single-Chip ESD Solution for HDMI Driver TPD12S520 provides a complete ESD protection scheme for an HDMI 1.4 compliant port. The monolithic integrated circuit technology ensures that there is excellent matching between the two-signal pair of the differential line. This is a direct advantage over discrete ESD clamp solutions where variations between two different ESD clamps may significantly degrade the differential signal quality. The 38-pin DBT package offers a seamless layout routing option to eliminate the routing glitch for the differential signal pair. 7.3.3 Supports All HDMI 1.3 and HDMI 1.4b Data Rates The high-speed TMDS pins of the TPD12S520 add only 0.8 pF of capacitance to the TMDS lines. Excellent intrapair capacitance matching of 0.05 pF provides ultra low intra-pair skew. Insertion loss -3 dB point > 3 GHz provides enough bandwidth to pass all HDMI 1.4b TMDS data rates. 7.3.4 38-Pin TSSOP Provides Seamless Layout Option With HDMI Connector The 38-pin DBT package offers seamless layout routing option to eliminate the routing glitch for the differential signal pair. DBT package pitch (0.5 mm) matches with HDMI connector pitch. In addition, pin mapping follows the same order as the HDMI connector pin mapping. This HDMI receiver port protection and interface device is specifically designed for next-generation HDMI receiver protection. 7.3.5 24-Pin WQFNPackage for Space Constrained Applications The 24-pin RMN package offers flow through routing using only two layers for highly integrated, space-efficient full HDMI protection. 7.3.6 Integrated Level Shifting for the Control Lines The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line ESD clamps add 3.5-pF capacitance to the control lines. 7.3.7 Backdrive Protection Backdrive protection is offered on the connector side pins. 7.3.8 Lead-Free Package Lead-Free Package for RoHS Compliance. 7.4 Device Functional Modes TPD12S520 is active with the conditions in the Recommended Operating Conditions met. The bi-directional voltage-level translators provide non-inverting level shifting from either 5V (for SDA , SCL, HPD), or 3.3 V (for CEC) on the connector side to VLV on the system side. Each connector side pin has an ESD clamp that triggers when voltages are above VBR or below the lower diode's Vf. During ESD events, voltages as high as ±8-kV (contact ESD) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below these trigger levels (usually within 10's of nano-seconds), these pins revert to a non-conductive state. 8 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 TPD12S520 www.ti.com SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information TPD12S520 provides IEC61000-4-2 Level 4 Contact ESD rating to the HDMI 1.4 receiver port. Integrated voltage-level shifting reduces the board space needed to implement the control lines. 8.2 Typical Application TPD12S520 is designed to protect a typical HDMI 1.4 receiver port. Refer to Figure 6 for a typical schematic. The eight TMDS data lines (D2+/-, D1+/-, D0+/-, CLK+/-) each have two pins on TPD12S520 to connect to. The TMDS data lines flow through their respective pin pairs, attaching to the passive ESD protection circuitry. VLV 100 kO 5V 3.3 V 10 kO 27 kO 5V 47 kO 47 kO 5V_SUPPLY NC LV_SUPPLY ESD_BYP 47 kO TMDS LINES HDMI Receiver HDMI Connector TMDS LINES TPD12S520 TPD12S521 CEC NC CEC DCLK DDAT HPD CEC_IN CEC_OUT DCLK_IN DCLK_OUT DDAT_IN DDAT_OUT HPD_IN HPD_OUT 0.1 …F 0.1 …F 0.1 …F 1 kO DCLK DDAT 5V HPD 0.1 …F Figure 6. TPD12S520 Configured with an HDMI 1.4 Receiver Port 8.2.1 Design Requirements For this example, use the following table as input parameters: DESIGN PARAMETERS EXAMPLE VALUE Voltage on 5V_SUPPLY 4.5 V - 5.5 V Voltage on LV_SUPPLY 1.7 V - 1.9 V Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 9 TPD12S520 SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 www.ti.com 8.2.2 Detailed Design Procedure To begin the design process the designer needs to know the 5V_SUPPLY voltage range and the logic level, LV_SUPPLY, voltage range. 8.2.3 Application Curves Figure 7. HDMI 1.65Gbps Eye Diagram With TPD12S520 on a Test Board Figure 8. HDMI 1.65Gbps Eye Diagram Without TPD12S520 on a Test Board Figure 9. Test Board to Measure Eye Diagram for the TPD12S520 (Refer to Eye Diagram Plot) 9 Power Supply Recommendations This device is designed to operate from an input voltage range of between 1.0 V and 5.5 V. This input supply should be well regulated. If the input supply is more than a few inches from TPD12S520 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. Otherwise, the device is a passive ESD protection device and there is no need to power it. Care should be taken to not violate the maximum voltage specifications to ensure that the device functions properly. The 5V_SUPPLY TVS diode can tolerate up to 6 V. 10 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 TPD12S520 www.ti.com SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example HDMI Connector 1 TPD12S520 Legend VIA to GND Plane VIA to 5V Plane VIA to 3.3V Plane VIA to LV Plane Pin to GND Figure 10. TPD12S520DBT Layout Example Use external and internal ground planes and stitch them together with VIAs as close to the GND pins of TPD12S520 as possible. This allows for a low impedance path to ground so that the device can properly dissipate an ESD event. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 11 TPD12S520 SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 www.ti.com 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPD12S520 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD12S520DBTR ACTIVE TSSOP DBT 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PN520 TPD12S520RMNR ACTIVE WQFN RMN 24 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 P520S (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of