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TPD1E01B04
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
TPD1E01B04 适用于 USB Type-C 和 Thunderbolt 3 的单通道 ESD 保护
二极管
1 特性
•
1
•
•
•
•
•
•
•
•
•
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
– ±15kV 接触放电
– ±17kV 气隙放电
IEC 61000-4-4 瞬态放电 (EFT) 保护
– 80A (5/50ns)
IEC 61000-4-5 浪涌保护
– 2.5A (8/20µs)
IO 电容：
– 0.18pF（典型值）
– 0.2pF（最大值）
直流击穿电压：6.4V（典型值）
超低泄漏电流：10nA（最大值）
低静电放电 (ESD) 钳位电压：16A 传输线路脉冲
(TLP) 时为 15V
低插入损耗：26.9GHz（–3dB 带宽）
支持速率高达 20Gbps 的高速接口
工业温度范围：-40°C 至 +125°C
超小型 0201 封装
2 应用
•
•
终端设备
– 便携式计算机和台式机
– 手机和平板电脑
– 机顶盒
– 电视和监视器
– USB 软件狗
– 扩展坞
接口
– USB Type-C
– Thunderbolt 3
– USB 3.1 第 2 代
– 高清多媒体接口 (HDMI) 2.0/1.4
– USB 3.0
– DisplayPort 1.3
– PCI Express 3
3 说明
TPD1E01B04 是一款适用于 USB Type-C 和
Thunderbolt 3 电路保护的双向 TVS ESD 保护二极管
阵列。TPD1E01B04 的额定 ESD 冲击消散值等于
IEC 61000-4-2（4 级）国际标准中规定的最高水平。
此器件 特有 一个 0.18pF（典型值）IO 电容，适用于
保护速率高达 20Gbps 的高速接口（例如 USB 3.1
Gen2 和 Thunderbolt 3）。低动态电阻和低钳位电压
可针对瞬变事件提供系统级保护。
TPD1E01B04 采用符合工业标准的 0201 (DPL) 封
装。
器件信息(1)
器件型号
TPD1E01B04
封装
封装尺寸（标称值）
X2SON (2)
0.60mm x 0.30mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
典型应用
USB Type-C
Connector
SSRX1P
SSRX1N
TPD1E01B04 (x4)
SSTX1P
SSTX1N
TPD4E05U06
VBUS
SBU2
CC1
DPT
DMT
TPD4E05U06
DMB
DPB
SBU1
CC2
VBUS
SSRX2N
SSRX2P
SSTX2N
TPD1E01B04 (x4)
SSTX2P
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDG3
TPD1E01B04
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
ESD Ratings—IEC Specification ..............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 13
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 13
11 器件和文档支持 ..................................................... 14
11.1
11.2
11.3
11.4
11.5
文档支持................................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
14
14
14
14
14
12 机械、封装和可订购信息 ....................................... 14
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (March 2016) to Revision B
•
Page
更改了Electrical Characteristics表。更新了 VHOLD 限值 ......................................................................................................... 1
Changes from Original (March 2016) to Revision A
Page
•
器件状态从产品预览改为量产数据 .......................................................................................................................................... 1
2
版权 © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
5 Pin Configuration and Functions
DPL Package
2-Pin X2SON
Top View
1
2
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
IO
I/O
ESD Protected Channel. If used as ESD IO, connect pin 2 to ground
2
IO
I/O
ESD Protected Channel. If used as ESD IO, connect pin 1 to ground
Copyright © 2016, Texas Instruments Incorporated
3
TPD1E01B04
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Electrical fast transient
Peak pulse
MAX
UNIT
80
A
IEC 61000-4-5 power (tp - 8/20 µs)
27
W
IEC 61000-4-5 current (tp - 8/20 µs)
2.5
A
IEC 61000-4-5 (5/50 ns)
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
155
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 contact discharge
±15000
IEC 61000-4-2 air-gap discharge
±17000
UNIT
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIO
Input pin voltage
–3.6
3.6
UNIT
V
TA
Operating free-air temperature
–40
125
°C
6.5 Thermal Information
TPD1E01B04
THERMAL METRIC
(1)
DPL (X2SON)
UNIT
2 PINS
RθJA
Junction-to-ambient thermal resistance
582
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
264.5
°C/W
Junction-to-board thermal resistance
394.4
°C/W
ψJT
Junction-to-top characterization parameter
36.4
°C/W
ψJB
Junction-to-board characterization parameter
394.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VRWM
Reverse stand-off voltage
IIO < 10 nA
VBRF
Breakdown voltage, IO pin to GND
VBRR
Breakdown voltage, GND to IO pin
Measured as the maximum voltage
before device snaps back into VHOLD
voltage
VHOLD
Holding voltage
IIO = 1 mA, TA = 25°C
VCLAMP
ILEAK
RDYN
CL
Clamping voltage
Leakage current, IO to GND
Dynamic resistance
Line capacitance
Copyright © 2016, Texas Instruments Incorporated
MIN
TYP
–3.6
5
MAX
3.6
UNIT
V
6.4
V
–6.4
V
5.9
IPP = 1 A, TLP, from IO to GND
7
IPP = 5 A, TLP, from IO to GND
9.2
IPP = 16 A, TLP, from IO to GND
15
IPP = 1 A, TLP, from GND to IO
7
IPP = 5 A, TLP, from GND to IO
9.2
IPP = 16 A, TLP, from GND to IO
15
VIO = ±2.5 V
6.5
V
10
IO to GND
0.57
GND to IO
0.57
VIO = 0 V, f = 1 MHz, IO to GND
TA = 25°C
0.18
V
nA
Ω
0.20
pF
5
TPD1E01B04
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
www.ti.com.cn
30
30
27
27
24
24
21
21
18
18
Current (A)
Current (A)
6.7 Typical Characteristics
15
12
9
15
12
9
6
6
3
3
0
0
-3
-3
0
3
6
9
12
15
Voltage (V)
18
21
24
0
27
3
6
9
12
15
Voltage (V)
D001
Figure 1. Positive TLP Curve
18
21
24
27
D002
Figure 2. Negative TLP Curve
110
10
100
0
90
-10
80
-20
Voltage (V)
Voltage (V)
70
60
50
40
30
-30
-40
-50
20
-60
10
-70
0
-10
-10
0
10
20
30
40 50
Time (ns)
60
70
80
90
-80
-10
100
0
10
0
5
40 50
Time (ns)
60
70
80
90
100
D004
0.4
0.35
0.3
Capacitance (pF)
3.6
Power 3.3
Current
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-0.3
10 15 20 25 30 35 40 45 50 55 60
Time (Ps)
D005
Figure 5. Surge Curve (tp = 8/20µs), IO pin to GND
6
30
Figure 4. –8-kV IEC Waveform
Current (A)
Power (W)
Figure 3. 8-kV IEC Waveform
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
5
2.5
0
-2.5
-5
20
D003
0.25
0.2
0.15
0.1
-40qC
25qC
85qC
125qC
0.05
0
0
0.4
0.8
1.2
1.6
2
2.4
Voltage Bias (V)
2.8
3.2
3.6
D006
Figure 6. Capacitance vs. Bias Voltage
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
Typical Characteristics (continued)
1
1000
0.8
0.6
0.4
Current (mA)
Leakage Current (pA)
800
600
400
0.2
0
-0.2
-0.4
-0.6
200
-0.8
0
-40
-1
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
-7
110 125
0.3
0.5
0.27
0
0.24
-0.5
0.21
0.18
0.15
0.12
0.09
-1 0 1
Voltage (V)
2
3
4
5
6
7
D001
-2.5
0.03
0
27
-2
-2
-3
22
-3
-1
-3.5
12
17
Frequency (GHz)
-4
-1.5
0.06
7
-5
Figure 8. DC Voltage Sweep I-V Curve
Insertion Loss (dB)
Capacitance (pF)
Figure 7. Leakage Current vs. Temperature
2
-6
D007
30
D009
-4
0.05
0.1
1
Frequency (GHz)
10
40
D010
Figure 9. Capacitance vs. Frequency
Figure 10. Insertion Loss
Figure 11. USB3.1 Gen 2 10-Gbps Eye Diagram (Bare Board)
Figure 12. USB3.1 Gen 2 10-Gbps Eye Diagram (with
TPD1E01B04)
Copyright © 2016, Texas Instruments Incorporated
7
TPD1E01B04
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPD1E01B04 device is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can
dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultralow capacitance makes this device ideal for protecting any super high-speed signal pins including Thunderbolt 3.
The low capacitance allows for extremely low losses even at RF frequencies such as USB 3.1 Gen 2,
Thunderbolt 3, or antenna applications.
7.2 Functional Block Diagram
IO
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±15-kV contact and ±17-kV air gap. An ESD-surge clamp diverts
the current to ground.
7.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2.5 A and 27 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 0.18 pF (typical) and 0.20 pF (maximum). This device
supports data rates up to 20 Gbps.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is ±6.4 V (typical). This ensures that sensitive equipment is protected
from surges above the reverse standoff voltage of ±3.6 V.
7.3.6 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.2 V (IPP = 5 A).
7.3.8 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 20 Gbps, because of the extremely low IO
capacitance.
7.3.9 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
8
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
Feature Description (continued)
7.3.10 Easy Flow-Through Routing Package
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPD1E01B04 device is a passive integrated circuit that triggers when voltages are above VBRF or below
VBRR. During ESD events, voltages as high as ±17 kV (air) can be directed to ground via the internal diode
network. When the voltages on the protected line fall below the trigger levels of TPD1E01B04 (usually within 10s
of nano-seconds) the device reverts to passive.
Copyright © 2016, Texas Instruments Incorporated
9
TPD1E01B04
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD1E01B04 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on
high-speed signal lines between a human interface connector and a system. As the current from ESD passes
through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the
protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
USB Type-C
Connector
SSRX1P
SSRX1N
TPD1E01B04 (x4)
SSTX1P
SSTX1N
TPD4E05U06
VBUS
SBU2
CC1
DPT
DMT
TPD4E05U06
DMB
DPB
SBU1
CC2
VBUS
SSRX2N
SSRX2P
SSTX2N
TPD1E01B04 (x4)
SSTX2P
Copyright © 2016, Texas Instruments Incorporated
Figure 13. USB Type-C for Thunderbolt 3 ESD Schematic
8.2.1 Design Requirements
For this design example eight TPD1E01B04 devices and two TPD4E05U06 devices are being used in a USB
Type-C for Thunderbolt 3 application. This provides a complete ESD protection scheme.
Given the Thunderbolt 3 application, the parameters listed in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on superspeed Lines
0 V to 3.6 V
Operating frequency on superspeed Lines
up to 10 GHz
Signal range on CC, SBU, and DP/DM Lines
0 V to 5 V
10
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
Typical Application (continued)
Table 1. Design Parameters (continued)
DESIGN PARAMETER
VALUE
Operating frequency on CC, SBU, and
DP/DM Lines
up to 480 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD1E01B04 supports signal ranges between –3.6 V and 3.6 V, which supports the SuperSpeed pairs on
the USB Type-C application. The TPD4E05U06 supports signal ranges between 0 V and 5.5 V, which supports
the CC, SBU, and DP-DM lines.
8.2.2.2 Operating Frequency
The TPD1E01B04 has a 0.18 pF (typical) capacitance, which supports the Thunderbolt 3 data rates of 20 Gbps.
The TPD4E05U06 has a 0.5-pF (typical) capacitance, which easily supports the CC, SBU, and DP-DM data
rates.
8.2.3 Application Curves
Figure 14. USB 3.1 Gen 2 10-Gbps Eye Diagram (Bare
Board)
Copyright © 2016, Texas Instruments Incorporated
Figure 15. USB 3.1 Gen 2 10-Gbps Eye Diagram (with
TPD1E01B04)
11
TPD1E01B04
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
www.ti.com.cn
0.5
0
Insertion Loss (dB)
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
0.05
0.1
1
Frequency (GHz)
10
40
D010
Figure 16. Insertion Loss
12
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
TPD1E01B04 (x4)
Top and bottom layer
TPD4E05U06
TPD4E05U06
TPD1E01B04 (x4)
Top and bottom layer
10.2 Layout Example
Legend
Top Layer
Bottom Layer
Pin to GND
VIA to VBUS Plane
VIA to other layer
VIA to GND Plane
Figure 17. USB Type-C Mid-Mount, Hybrid Connector ESD Layout
版权 © 2016, Texas Instruments Incorporated
13
TPD1E01B04
ZHCSF79B – MARCH 2016 – REVISED MAY 2016
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
相关文档请参见以下部分：
用户指南《TPD1E01B04 评估模块》，SLVUAN5
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
14
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPD1E01B04DPLR
ACTIVE
X2SON
DPL
2
15000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7
Samples
TPD1E01B04DPLT
ACTIVE
X2SON
DPL
2
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7
Samples
TPD1E01B04DPYR
ACTIVE
X1SON
DPY
2
10000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(5C, A5)
Samples
TPD1E01B04DPYT
ACTIVE
X1SON
DPY
2
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(5C, A5)
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
