TPD2E007DCKR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPD2E007 SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016 TPD2E007 2-Channel ESD Protection Array for AC-Coupled/Negative-Rail Data Interfaces 1 Features 3 Description • This device is a transient voltage suppressor (TVS) based electrostatic discharge (ESD) protection device designed to offer system level ESD solutions for wide range of portable and industrial applications. The back-to-back diode array allows AC-coupled or negative-going data transmission (audio interface, LVDS, RS-485, RS-232, and so forth) without compromising signal integrity. This device exceeds the IEC 61000-4-2 (Level 4) ESD protection and is ideal for providing system level ESD protection for the internal ICs when placed near the connector. 1 • • • • IEC 61000-4-2 Level 4 ESD Protection – ±8-kV IEC 61000-4-2 Contact Discharge – ±15-kV IEC 61000-4-2 Air-Gap Discharge IEC 61000-4-5 Surge Protection – 4.5-A Peak Pulse Current (8/20-µs Pulse) IO Capacitance 15 pF (Max) Low 50-nA Leakage Current Space-Saving PicoStar™ and SOT Package 2 Applications • • • • Cell Phones Audio Interface Connections Consumer Electronics (DVR, Set-Top Box, TV) Industrial Interfaces (RS-232, RS-485, RS-422, LVDS) The TPD2E007 is offered in a 4-bump PicoStar and 3-pin SOT (DGK) packages. The PicoStar package (YFM), with only 0.15 mm (Max) package height, is recommended for ultra space saving application where the package height is a key concern. The PicoStar package can be used in either embedded PCB board applications or in surface mount applications. The industry standard SOT package offers straightforward board layout option in legacy designs. Device Information(1) PART NUMBER TPD2E007 PACKAGE BODY SIZE (NOM) SOT (3) 2.00 mm x 1.25 mm PicoStar (4) 0.77 mm x 0.77 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Example Schematic Equivalent Schematic Representation IO1 RXd GND 1 TPD2E007 2 RS232 Transceiver RS232 Connector TXd IO2 GND 3 GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD2E007 SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 4 5 5 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. ESD Ratings: Surge Protection................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 6 7.1 Overview ................................................................... 6 7.2 Functional Block Diagram ......................................... 6 7.3 Feature Description................................................... 6 7.4 Device Functional Modes.......................................... 6 8 Application and Implementation .......................... 7 8.1 Application Information.............................................. 7 8.2 Typical Application ................................................... 7 9 Power Supply Recommendations........................ 8 10 Layout..................................................................... 8 10.1 Layout Guidelines ................................................... 8 10.2 Layout Example ...................................................... 8 11 Device and Documentation Support ................... 9 11.1 11.2 11.3 11.4 Community Resources............................................ Trademarks ............................................................. Electrostatic Discharge Caution .............................. Glossary .................................................................. 9 9 9 9 12 Mechanical, Packaging, and Orderable Information ............................................................. 9 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (January 2016) to Revision I • Made changes to ESDS section ............................................................................................................................................ 1 Changes from Revision G (December 2015) to Revision H • Page Page Updated the break-down voltage for clarity ........................................................................................................................... 5 Changes from Revision F (August 2014) to Revision G Page • Updated the Handling Ratings table to an ESD Ratings table and moved Tstg to the Absolute Maximum Ratings table ....................................................................................................................................................................................... 4 • Added ƒ = 10 MHz to the Channel input capacitance test condition in the Electrical Characteristics table ......................... 5 • Added Community Resources ............................................................................................................................................... 9 Changes from Revision E (August 2010) to Revision F • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 Changes from Revision D (October 2009) to Revision E • 2 Page Page Added max continuous power dissipation value for DCK package........................................................................................ 4 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD2E007 TPD2E007 www.ti.com SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016 5 Pin Configuration and Functions DCK Package 3-Pin SOT Top View IO1 1 GND 3 IO2 2 YFM Package 4-Pin PicoStar Bottom View GND B1 B2 GND IO1 A1 A2 IO2 0.8 mm × 0.8 mm (0.4 mm pitch) Pin Functions PIN I/O DESCRIPTION DCK NO. YFM NO. GND 3 B1, B2 G Ground IO1 1 A1 IO ESD protected channel IO2 2 A2 IO ESD protected channel NAME Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD2E007 3 TPD2E007 SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VIO Continuous power dissipation (TA = 70°C) MAX UNIT 13.5 V YFM package 270 DCK package 218 Operating temperature TJ MIN –13.5 –40 Junction temperature Bump temperature (soldering) (1) 85 °C 150 °C Infrared (15 s) 220 Vapor phase (60 s) 215 Lead temperature (soldering, 10 s) Tstg Storage temperature –65 mW °C 300 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±15000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings: Surge Protection VALUE Electrostatic discharge V(ESD) IEC 61000-4-2 ESD ratings Contact ±8000 Air gap ±15000 UNIT V 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIO NOM MAX UNIT Operating voltage –13 13 V Operating temperature –40 85 °C 6.5 Thermal Information TPD2E007 THERMAL METRIC (1) DCK (SOT) YFM (PicoStar) 3 PINS 4 PINS UNIT RθJA Junction-to-ambient thermal resistance 251.9 175.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 115.4 39.2 °C/W RθJB Junction-to-board thermal resistance 42.4 28.7 °C/W ψJT Junction-to-top characterization parameter 9.4 8.3 °C/W ψJB Junction-to-board characterization parameter 42.2 28.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD2E007 TPD2E007 www.ti.com SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016 6.6 Electrical Characteristics TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS TYP (1) MIN VBRF Break-down voltage, pin 1 or 2 to GND IIO = 10 mA 14 VBRR Break-down voltage, GND to pin 1 or 2 IIO = 10 mA 14 IIO Channel leakage current 20 Rd Dynamic resistance 3.5 CIN Channel input capacitance (1) MAX UNIT V V VIO = 2.5 V; ƒ = 10 MHz 10 50 nA Ω 15 pF Typical values are at VCC = 5 V and TA = 25°C. 6.7 Typical Characteristics IEC Clamping Waveforms (20 ns/div) 40 280 20 240 0 –20 200 –40 Amplitude (V) Amplitude (V) –60 160 120 80 –80 –100 –120 –140 –160 –180 40 –200 –220 0 –240 –260 –40 –280 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 Time (ns) 80 100 120 Time (ns) 140 160 180 200 Figure 2. –8-kV Contact Figure 1. 8-kV Contact 1.5E-11 1.50E-01 1.4E-11 1.25E-01 1.3E-11 1.00E-01 1.2E-11 7.50E-02 5.00E-02 1.0E-11 2.50E-02 9.0E-12 Amps Capacitance (F) 1.1E-11 8.0E-12 7.0E-12 0.00E+00 –2.50E-02 Device 2 6.0E-12 –5.00E-02 Device 1 5.0E-12 –7.50E-02 4.0E-12 Device 1 –1.00E-01 3.0E-12 Device 2 –1.25E-01 2.0E-12 1.0E-12 4.5 5.0 Input Voltage (V) 7. 5 10 .0 12 .5 15 .0 17 .5 20 .0 4.0 5 3.5 0 3.0 5. 2.5 0 2.0 2. 1.5 0. 1.0 –2 0.5 0. 0 –1 7. 5 –1 5. 0 –1 2. 5 –1 0. 0 –7 .5 –5 .0 -2 .5 –1.50E-01 0.0 Volts Figure 3. Capacitance vs Input Voltage at TA = 27°C Figure 4. Diode Breakdown Voltage Data at TA = 27°C Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD2E007 5 TPD2E007 SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPD2E007 an ESD protection device designed to offer system level ESD solutions for wide range of portable and industrial applications. The back-to-back diode array allows AC-coupled or negative-going data transmission (audio interface, LVDS, RS-485, RS-232, etc.) without compromising signal integrity. The PicoStar package is intended to be embedded inside the printed circuit board which saves board space in portable applications. This device exceeds the IEC 61000-4-2 (Level 4) ESD protection and is ideal for providing system level ESD protection for the internal ICs when placed near the connector. 7.2 Functional Block Diagram IO1 IO2 GND Figure 5. Equivalent Schematic Representation 7.3 Feature Description The TPD2E007 an ESD protection device designed to offer system level ESD solutions for wide range of portable and industrial applications. The back-to-back diode array allows AC-coupled or negative-going data transmission (audio interface, LVDS, RS-485, RS-232, etc.) without compromising signal integrity. The PicoStar package is intended to be embedded inside the printed circuit board which saves board space in portable applications. This device exceeds the IEC 61000-4-2 (Level 4) ESD protection and is ideal for providing system level ESD protection for the internal ICs when placed near the connector. 7.3.1 IEC 61000-4-2 Level 4 ESD Protection The I/O pins can withstand ESD events up to ±12-kV contact and ±15 kV-air. An ESD/surge clamp diverts the current to ground. 7.3.2 IEC 61000-4-5 Surge Protection The I/O pins can withstand surge events up to 4.5 A (8/20 µs waveform). An ESD/surge clamp diverts this current to ground. 7.3.3 IO Capacitance The capacitance between each I/O pin to ground is 15 pF. 7.3.4 Low 50-nA Leakage Current The I/O pins feature a low 50-nA (max) leakage current. 7.3.5 Space-Saving PicoStar and SOT Package This device is offered in both a space-saving PicoStar package, as well as a standard DCK package. 7.4 Device Functional Modes TPD2E007 is a passive integrated circuit that triggers when voltages are above or below VBR. During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD2E007 (usually within 10’s of nano-seconds) the device reverts to passive. 6 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD2E007 TPD2E007 www.ti.com SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information TPD2E007 is a diode type TVS which is typically used to provide a path to ground for dissipating ESD events on signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. 8.2 Typical Application RS232 Transceiver RS232 Connector TXd RXd 1 GND 2 TPD2E007 3 GND Figure 6. Example Schematic 8.2.1 Design Requirements For this design example, a single TPD2E007 is used to protect an RS232 3-wire connector. Given the application, the following parameters are known. Table 1. Design Parameters DESIGN PARAMETER VALUE Signal range on all pins except GND –12 V to 12 V Surge Withstand - IEC 61000-4-5 150 W 8.2.2 Detailed Design Procedure To begin the design process, some parameters must be decided upon; the designer needs to know the following: • • Signal voltage range on all protected lines Surge Withstand 8.2.2.1 Signal Range on IO1 and IO2 Pins The TPD2E007 has 2 IO pins which can support up to ±13 V. 8.2.2.2 Surge Withstand The TPD2E007 can withstand up to 170W of IEC 61000-4-5 8/20-µs surge. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD2E007 7 TPD2E007 SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016 www.ti.com 8.2.3 Application Curve 180 5 160 Current (A) 4 140 Power (W) 100 80 2 Power (W) Current (A) 120 3 60 40 1 20 0 0 0 10 20 30 40 50 Time (µs) C014 Figure 7. Surge Pulse Waveform 9 Power Supply Recommendations This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended I/O specification (±13 V) to ensure the device functions properly. 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example IO1 GND IO2 = VIA to GND Figure 8. Layout Recommendation 8 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD2E007 TPD2E007 www.ti.com SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks PicoStar, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD2E007 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD2E007DCKR ACTIVE SC70 DCK 3 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 45U TPD2E007YFMRG4 ACTIVE DSLGA YFM 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 45 T TPD2E007YFMTG4 ACTIVE DSLGA YFM 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 45 T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of