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TPD2E007
SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016
TPD2E007 2-Channel ESD Protection Array for AC-Coupled/Negative-Rail Data Interfaces
1 Features
3 Description
•
This device is a transient voltage suppressor (TVS)
based electrostatic discharge (ESD) protection device
designed to offer system level ESD solutions for wide
range of portable and industrial applications. The
back-to-back diode array allows AC-coupled or
negative-going data transmission (audio interface,
LVDS, RS-485, RS-232, and so forth) without
compromising signal integrity. This device exceeds
the IEC 61000-4-2 (Level 4) ESD protection and is
ideal for providing system level ESD protection for the
internal ICs when placed near the connector.
1
•
•
•
•
IEC 61000-4-2 Level 4 ESD Protection
– ±8-kV IEC 61000-4-2 Contact Discharge
– ±15-kV IEC 61000-4-2 Air-Gap Discharge
IEC 61000-4-5 Surge Protection
– 4.5-A Peak Pulse Current (8/20-µs Pulse)
IO Capacitance 15 pF (Max)
Low 50-nA Leakage Current
Space-Saving PicoStar™ and SOT Package
2 Applications
•
•
•
•
Cell Phones
Audio Interface Connections
Consumer Electronics (DVR, Set-Top Box, TV)
Industrial Interfaces (RS-232, RS-485, RS-422,
LVDS)
The TPD2E007 is offered in a 4-bump PicoStar and
3-pin SOT (DGK) packages. The PicoStar package
(YFM), with only 0.15 mm (Max) package height, is
recommended for ultra space saving application
where the package height is a key concern. The
PicoStar package can be used in either embedded
PCB board applications or in surface mount
applications. The industry standard SOT package
offers straightforward board layout option in legacy
designs.
Device Information(1)
PART NUMBER
TPD2E007
PACKAGE
BODY SIZE (NOM)
SOT (3)
2.00 mm x 1.25 mm
PicoStar (4)
0.77 mm x 0.77 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Example Schematic
Equivalent Schematic Representation
IO1
RXd
GND
1
TPD2E007
2
RS232
Transceiver
RS232
Connector
TXd
IO2
GND
3
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD2E007
SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
ESD Ratings: Surge Protection.................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 6
7.1 Overview ................................................................... 6
7.2 Functional Block Diagram ......................................... 6
7.3 Feature Description................................................... 6
7.4 Device Functional Modes.......................................... 6
8
Application and Implementation .......................... 7
8.1 Application Information.............................................. 7
8.2 Typical Application ................................................... 7
9 Power Supply Recommendations........................ 8
10 Layout..................................................................... 8
10.1 Layout Guidelines ................................................... 8
10.2 Layout Example ...................................................... 8
11 Device and Documentation Support ................... 9
11.1
11.2
11.3
11.4
Community Resources............................................
Trademarks .............................................................
Electrostatic Discharge Caution ..............................
Glossary ..................................................................
9
9
9
9
12 Mechanical, Packaging, and Orderable
Information ............................................................. 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (January 2016) to Revision I
•
Made changes to ESDS section ............................................................................................................................................ 1
Changes from Revision G (December 2015) to Revision H
•
Page
Page
Updated the break-down voltage for clarity ........................................................................................................................... 5
Changes from Revision F (August 2014) to Revision G
Page
•
Updated the Handling Ratings table to an ESD Ratings table and moved Tstg to the Absolute Maximum Ratings
table ....................................................................................................................................................................................... 4
•
Added ƒ = 10 MHz to the Channel input capacitance test condition in the Electrical Characteristics table ......................... 5
•
Added Community Resources ............................................................................................................................................... 9
Changes from Revision E (August 2010) to Revision F
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision D (October 2009) to Revision E
•
2
Page
Page
Added max continuous power dissipation value for DCK package........................................................................................ 4
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5 Pin Configuration and Functions
DCK Package
3-Pin SOT
Top View
IO1
1
GND
3
IO2
2
YFM Package
4-Pin PicoStar
Bottom View
GND
B1
B2
GND
IO1
A1
A2
IO2
0.8 mm × 0.8 mm (0.4 mm pitch)
Pin Functions
PIN
I/O
DESCRIPTION
DCK
NO.
YFM
NO.
GND
3
B1, B2
G
Ground
IO1
1
A1
IO
ESD protected channel
IO2
2
A2
IO
ESD protected channel
NAME
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TPD2E007
SLVS796I – SEPTEMBER 2008 – REVISED MARCH 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VIO
Continuous power dissipation
(TA = 70°C)
MAX
UNIT
13.5
V
YFM package
270
DCK package
218
Operating temperature
TJ
MIN
–13.5
–40
Junction temperature
Bump temperature (soldering)
(1)
85
°C
150
°C
Infrared (15 s)
220
Vapor phase (60 s)
215
Lead temperature (soldering, 10 s)
Tstg
Storage temperature
–65
mW
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±15000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings: Surge Protection
VALUE
Electrostatic
discharge
V(ESD)
IEC 61000-4-2 ESD ratings
Contact
±8000
Air gap
±15000
UNIT
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIO
NOM
MAX
UNIT
Operating voltage
–13
13
V
Operating temperature
–40
85
°C
6.5 Thermal Information
TPD2E007
THERMAL METRIC
(1)
DCK (SOT)
YFM (PicoStar)
3 PINS
4 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
251.9
175.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
115.4
39.2
°C/W
RθJB
Junction-to-board thermal resistance
42.4
28.7
°C/W
ψJT
Junction-to-top characterization parameter
9.4
8.3
°C/W
ψJB
Junction-to-board characterization parameter
42.2
28.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.6 Electrical Characteristics
TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP (1)
MIN
VBRF
Break-down voltage, pin 1 or 2 to GND
IIO = 10 mA
14
VBRR
Break-down voltage, GND to pin 1 or 2
IIO = 10 mA
14
IIO
Channel leakage current
20
Rd
Dynamic resistance
3.5
CIN
Channel input capacitance
(1)
MAX
UNIT
V
V
VIO = 2.5 V; ƒ = 10 MHz
10
50
nA
Ω
15
pF
Typical values are at VCC = 5 V and TA = 25°C.
6.7 Typical Characteristics
IEC Clamping Waveforms (20 ns/div)
40
280
20
240
0
–20
200
–40
Amplitude (V)
Amplitude (V)
–60
160
120
80
–80
–100
–120
–140
–160
–180
40
–200
–220
0
–240
–260
–40
–280
0
20
40
60
80
100
120
140
160
180
200
0
20
40
60
Time (ns)
80
100
120
Time (ns)
140
160
180
200
Figure 2. –8-kV Contact
Figure 1. 8-kV Contact
1.5E-11
1.50E-01
1.4E-11
1.25E-01
1.3E-11
1.00E-01
1.2E-11
7.50E-02
5.00E-02
1.0E-11
2.50E-02
9.0E-12
Amps
Capacitance (F)
1.1E-11
8.0E-12
7.0E-12
0.00E+00
–2.50E-02
Device 2
6.0E-12
–5.00E-02
Device 1
5.0E-12
–7.50E-02
4.0E-12
Device 1
–1.00E-01
3.0E-12
Device 2
–1.25E-01
2.0E-12
1.0E-12
4.5
5.0
Input Voltage (V)
7.
5
10
.0
12
.5
15
.0
17
.5
20
.0
4.0
5
3.5
0
3.0
5.
2.5
0
2.0
2.
1.5
0.
1.0
–2
0.5
0.
0
–1
7.
5
–1
5.
0
–1
2.
5
–1
0.
0
–7
.5
–5
.0
-2
.5
–1.50E-01
0.0
Volts
Figure 3. Capacitance vs Input Voltage at TA = 27°C
Figure 4. Diode Breakdown Voltage Data at TA = 27°C
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7 Detailed Description
7.1 Overview
The TPD2E007 an ESD protection device designed to offer system level ESD solutions for wide range of
portable and industrial applications. The back-to-back diode array allows AC-coupled or negative-going data
transmission (audio interface, LVDS, RS-485, RS-232, etc.) without compromising signal integrity. The PicoStar
package is intended to be embedded inside the printed circuit board which saves board space in portable
applications. This device exceeds the IEC 61000-4-2 (Level 4) ESD protection and is ideal for providing system
level ESD protection for the internal ICs when placed near the connector.
7.2 Functional Block Diagram
IO1
IO2
GND
Figure 5. Equivalent Schematic Representation
7.3 Feature Description
The TPD2E007 an ESD protection device designed to offer system level ESD solutions for wide range of
portable and industrial applications. The back-to-back diode array allows AC-coupled or negative-going data
transmission (audio interface, LVDS, RS-485, RS-232, etc.) without compromising signal integrity. The PicoStar
package is intended to be embedded inside the printed circuit board which saves board space in portable
applications. This device exceeds the IEC 61000-4-2 (Level 4) ESD protection and is ideal for providing system
level ESD protection for the internal ICs when placed near the connector.
7.3.1 IEC 61000-4-2 Level 4 ESD Protection
The I/O pins can withstand ESD events up to ±12-kV contact and ±15 kV-air. An ESD/surge clamp diverts the
current to ground.
7.3.2 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 4.5 A (8/20 µs waveform). An ESD/surge clamp diverts this
current to ground.
7.3.3 IO Capacitance
The capacitance between each I/O pin to ground is 15 pF.
7.3.4 Low 50-nA Leakage Current
The I/O pins feature a low 50-nA (max) leakage current.
7.3.5 Space-Saving PicoStar and SOT Package
This device is offered in both a space-saving PicoStar package, as well as a standard DCK package.
7.4 Device Functional Modes
TPD2E007 is a passive integrated circuit that triggers when voltages are above or below VBR. During ESD
events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. Once the
voltages on the protected line fall below the trigger levels of TPD2E007 (usually within 10’s of nano-seconds) the
device reverts to passive.
6
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
TPD2E007 is a diode type TVS which is typically used to provide a path to ground for dissipating ESD events on
signal lines between a human interface connector and a system. As the current from ESD passes through the
TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
8.2 Typical Application
RS232
Transceiver
RS232
Connector
TXd
RXd
1
GND
2
TPD2E007
3
GND
Figure 6. Example Schematic
8.2.1 Design Requirements
For this design example, a single TPD2E007 is used to protect an RS232 3-wire connector.
Given the application, the following parameters are known.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on all pins except GND
–12 V to 12 V
Surge Withstand - IEC 61000-4-5
150 W
8.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon; the designer needs to know the following:
•
•
Signal voltage range on all protected lines
Surge Withstand
8.2.2.1 Signal Range on IO1 and IO2 Pins
The TPD2E007 has 2 IO pins which can support up to ±13 V.
8.2.2.2 Surge Withstand
The TPD2E007 can withstand up to 170W of IEC 61000-4-5 8/20-µs surge.
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8.2.3 Application Curve
180
5
160
Current (A)
4
140
Power (W)
100
80
2
Power (W)
Current (A)
120
3
60
40
1
20
0
0
0
10
20
30
40
50
Time (µs)
C014
Figure 7. Surge Pulse Waveform
9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (±13 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
IO1
GND
IO2
= VIA to GND
Figure 8. Layout Recommendation
8
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
PicoStar, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-May-2025
PACKAGING INFORMATION
Orderable part number
(1)
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
TPD2E007DCKR
Active
Production
SC70 (DCK) | 3
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
45U
TPD2E007DCKR.A
Active
Production
SC70 (DCK) | 3
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
45U
TPD2E007DCKR.B
Active
Production
SC70 (DCK) | 3
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
45U
TPD2E007YFMTG4
Obsolete
Production
DSLGA (YFM) | 4
-
-
Call TI
Call TI
-40 to 85
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2024
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
TPD2E007DCKR
Package Package Pins
Type Drawing
SC70
DCK
3
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
179.0
8.4
Pack Materials-Page 1
2.4
B0
(mm)
K0
(mm)
P1
(mm)
2.4
1.19
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
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20-Apr-2024
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD2E007DCKR
SC70
DCK
3
3000
213.0
191.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0003A
SOT-SC70 - 1.1 max height
SCALE 5.600
SMALL OUTLINE TRANSISTOR SC70
C
2.4
1.8
1.4
1.1
PIN 1
INDEX AREA
0.1 C
B
1.1 MAX
A
1
0.65
1.3
3
2.15
1.85
2
3X
0.1
0.30
0.15
C A B
4X 0 -12
(0.9)
0.1
TYP
0.0
4X 4 -15
0.15
0.22
TYP
0.08
GAGE PLANE
8
TYP
0
0.46
TYP
0.26
SEATING PLANE
4220745/F 11/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.25mm per side
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EXAMPLE BOARD LAYOUT
DCK0003A
SOT-SC70 - 1.1 max height
SMALL OUTLINE TRANSISTOR SC70
3X (0.95)
3X (0.4)
PKG
1
SYMM
(1.3)
3
(0.65)
2
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220745/F 11/2024
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0003A
SOT-SC70 - 1.1 max height
SMALL OUTLINE TRANSISTOR SC70
PKG
3X (0.95)
3X (0.4)
1
SYMM
(1.3)
3
(0.65)
2
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4220745/F 11/2024
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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