TPD2E2U06-Q1
SLLSEJ9E – DECEMBER 2014 – REVISED OCTOBER 2022
TPD2E2U06-Q1 Automotive Dual-Channel High-Speed ESD Protection Device
1 Features
3 Description
•
•
The TPD2E2U06-Q1 is a Transient Voltage
Suppressor (TVS) Electrostatic Discharge (ESD)
protection diode array with low capacitance. This
dual-channel ESD protection diode is rated to
dissipate ESD strikes above the maximum level
specified in the IEC 61000-4-2 international standard.
The 1.5-pF line capacitance of the TPD2E2U06-Q1
makes it ideal for protecting interfaces such as USB
2.0, Ethernet, LVDS, antenna, and I2C.
•
•
•
•
•
•
Package Information(1)
PART NUMBER
TPD2E2U06-Q1
2 Applications
•
(1)
End equipment:
– Head units
– Rear seat entertainment
– Telematics
– Navigation modules
– Media interfaces
Interfaces:
– USB 2.0
– Ethernet™
– Antenna
– LVDS
– I2C
BODY SIZE (NOM)
DBZ (SOT23, 3)
2.92 mm × 1.30 mm
DCK (SC70, 3)
2.00 mm × 1.25 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Power
Supply
Vbus
D+
USB 2.0
Connector
•
PACKAGE
D-
1
TPD2E2U06-Q1
2
USB 2.0
Transceiver
•
AEC-Q101 qualified
IEC 61000-4-2 Level 4 ESD protection
– ±25-kV (contact discharge)
– ±30-kV (air-gap discharge)
ISO 10605 (330 pF, 330 Ω) ESD protection
– ±20-kV (contact discharge)
– ±25-kV (air-gap discharge)
IO capacitance 1.5-pF (typical)
DC breakdown voltage 6.5 V (minimum)
Ultra-low leakage current 10-nA (maximum)
Low ESD clamping voltage
Industrial temperature range: –40°C to +125°C
Small easy-to-route DBZ and DCK packages
3
GND
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD2E2U06-Q1
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SLLSEJ9E – DECEMBER 2014 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings—AEC Specification............................... 4
6.3 ESD Ratings—IEC Specification................................ 4
6.4 ESD Ratings—ISO Specification................................ 4
6.5 Recommended Operating Conditions.........................4
6.6 Thermal Information....................................................5
6.7 Electrical Characteristics.............................................5
6.8 Typical Characteristics................................................ 6
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................9
8 Application and Implementation.................................. 10
8.1 Application Information............................................. 10
8.2 Typical Application.................................................... 10
9 Power Supply Recommendations................................11
10 Layout...........................................................................12
10.1 Layout Guidelines................................................... 12
10.2 Layout Example...................................................... 12
11 Device and Documentation Support..........................13
11.1 Documentation Support.......................................... 13
11.2 Receiving Notification of Documentation Updates.. 13
11.3 Support Resources................................................. 13
11.4 Trademarks............................................................. 13
11.5 Electrostatic Discharge Caution.............................. 13
11.6 Glossary.................................................................. 13
12 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2016) to Revision E (October 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the Surge Curve (tp = 8/20 μs) IO to GND figure................................................................................. 6
Changes from Revision C (March 2016) to Revision D (May 2016)
Page
• Updated Features, Applications, and Description ..............................................................................................1
• Updated the ESD Ratings—AEC Specification table ........................................................................................ 1
Changes from Revision B (December 2014) to Revision C (March 2016)
Page
• Added DCK package.......................................................................................................................................... 1
• Added DCK thermal data in the Thermal Information table................................................................................ 1
Changes from Revision A (December 2014) to Revision B (December 2014)
Page
• Added temperature specification to VBR TEST CONDITIONS. ......................................................................... 5
Changes from Revision * (December 2014) to Revision A (December 2014)
Page
• Initial release of full document. .......................................................................................................................... 1
2
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5 Pin Configuration and Functions
IO1
1
3
IO2
GND
2
Figure 5-1. DBZ Package, 3-Pin SOT23 (Top View)
IO1
1
3
IO2
GND
2
Figure 5-2. DCK Package, 3-Pin SC70 (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
IO1
1
I/O
IO2
2
I/O
The IO1 and IO2 pins are an ESD protected channel. Connect these pins to the data
line as close to the connector as possible.
GND
3
G
The GND (ground) pin is connected to ground.
(1)
I = input, O = output, G = ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MAX
UNIT
Peak pulse current (tp = 8/20 μs)
MIN
5.5(2)
A
PPP
Peak pulse power (tp = 8/20 μs)
75(2)
W
TJ
Junction temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
IPP
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Measured at 25°C.
6.2 ESD Ratings—AEC Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1)
±10000
Charged device model (CDM), per AEC Q100-011
±1000
UNIT
V
AAEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2
Contact discharge
±25000
Air-gap discharge
±30000
UNIT
V
6.4 ESD Ratings—ISO Specification
VALUE
V(ESD)
Electrostatic discharge
ISO 10605 (330 pF, 330 Ω)
Contact discharge
±20000
Air-gap discharge
±25000
UNIT
V
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4
VIO
Input pin voltage
TA
Operating free air temperature
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MAX
UNIT
0
5.5
V
–40
125
℃
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6.6 Thermal Information
TPD2E2U06-Q1
THERMAL
METRIC(1)
DBZ (SOT23)
DCK (SC70)
3 PINS
3 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
439.5
308.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
194.9
170.7
°C/W
RθJB
Junction-to-board thermal resistance
173.9
89.2
°C/W
ψJT
Junction-to-top characterization parameter
53.7
34.2
°C/W
ψJB
Junction-to-board characterization parameter
172
88.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VRWM
Reverse stand-off voltage
TEST CONDITIONS
MIN
TYP
IIO < 10 µA
5.5
TLP(1) (3)
9.7
IPP = 5 A, TLP(1) (3)
12.4
IPP = 1 A, TLP(1) (3)
1.9
IPP = 5 A, TLP(1) (3)
4
IPP = 1 A,
MAX
VCLAMP
IO to GND
VCLAMP
GND to IO
RDYN
Dynamic resistance
CL
Line capacitance
f = 1 MHz, VBIAS = 2.5 V(3)
1.5
1.9
CCROSS
Channel-to-channel input
capacitance
Pin 3 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between
channel pins(3)
0.02
0.03
∆CL
Variation of channel input
capacitance
Pin 3 = 0 V, f = 1 MHz, VBIAS = 2.5 V,
Pin 1 to GND – Pin 2 to GND(3)
0.03
0.1
VBR
Break-down voltage
IIO = 1 mA(3)
ILEAK
Leakage current
VIO = 2.5 V
(1)
(2)
(3)
IO to GND(2) (3)
0.6
GND to IO(2) (3)
0.4
6.5
1
UNIT
V
V
V
Ω
pF
pF
pF
8.5
V
10
nA
Transmission Line Pulse with 10-ns rise time, 100-ns width.
Extraction of RDYN Using least squares fit of TLP characteristics between I = 20 A and I = 30 A.
Measured at 25°C.
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6.8 Typical Characteristics
30
30
25
25
20
20
Current (A)
Current (A)
Measured at TA = 25°C unless otherwise specified
15
15
10
10
5
5
0
0
0
5
10
15
20
25
30
35
40
45
Voltage (V)
50
0
5
120
15
105
0
90
±15
75
±30
Voltage (V)
Voltage (V)
20
25
30
35
40
45
50
C002
Figure 6-2. TLP, GND to Data
60
45
30
±45
±60
±75
15
±90
0
±105
±15
±120
0
25
50
75
100
125
150
175
Time (ns)
200
0
25
50
75
100
125
150
175
Time (ns)
C003
Figure 6-3. IEC 61000-4-2 Clamping Voltage, 8-kV Contact
200
C004
Figure 6-4. IEC 61000-4-2 Clamping Voltage, –8-kV Contact
500
0.001
400
Current (pA)
0.0005
Current (A)
15
Voltage (V)
Figure 6-1. TLP, Data to GND
0
-0.0005
300
200
100
0
-0.001
±2
±1
0
1
2
3
4
5
6
7
Voltage (V)
8
9
10
±40
±15
10
35
60
85
110
Temperature (ƒC)
C005
Figure 6-5. IV Curve, TA = 25°C
6
10
C001
135
C006
Figure 6-6. ILEAK vs Temperature, VIN = 2.5 V
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6.8 Typical Characteristics (continued)
7
2.4
6
2.0
5
75
4
60
3
45
0.8
2
30
0.4
1
15
1.6
1.2
105
Current
Power 90
0
0.0
0
1
2
3
4
0
5
Voltage (V)
10
20
30
40
Time (s)
50
60
Power (W)
2.8
Current (A)
Capacitance (pF)
Measured at TA = 25°C unless otherwise specified
0
70
Figure 6-8. Surge Curve (tp = 8/20 μs) IO to GND
C007
Figure 6-7. Capacitance Across VBIAS f = 1 MHz
0
Insertion Loss (dB)
±3
±6
±9
±12
±15
±18
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
Frequency (Hz)
1.E+10
C009
Figure 6-9. Insertion Loss
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7 Detailed Description
7.1 Overview
The TPD2E2U06-Q1 device is a TVS ESD protection diode array with low capacitance. It is rated to dissipate
ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The 1.5-pF line
capacitance makes it ideal for protecting interfaces such as USB 2.0, LVDS, antenna, and I2C.
7.2 Functional Block Diagram
IO1
IO2
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
The TPD2E2U06-Q1 device is a TVS ESD protection diode array with low capacitance. It is rated to dissipate
ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The 1.5-pF line
capacitance makes it ideal for protecting interfaces such as USB 2.0, LVDS, antenna, and I2C.
7.3.1 AEC-Q101 Qualified
This device is qualified to AEC-Q101 standards. It passes HBM H3B (±8 kV) and CDM C5 (±1 kV) ESD ratings
and is qualified to operate from –40°C to +125°C.
7.3.2 IEC 61000-4-2 Level 4
The I/O pins can withstand ESD events up to ±25-kV contact and ±30-kV air. An ESD-surge clamp diverts the
current to ground.
7.3.3 IO Capacitance
The capacitance between each I/O pin to ground is 1.5 pF. These capacitances support data rates in excess of
1.5 Gbps.
7.3.4 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of 6.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 5.5 V.
7.3.5 Ultra-Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (Maximum) with a bias of 2.5 V.
7.3.6 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.7 V (IPP = 1 A).
7.3.7 Industrial Temperature Range
This device is designed to operate from –40°C to +125°C.
7.3.8 Small Easy-to-Route Packages
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offer
flow-through routing, requiring minimal modification to an existing layout.
8
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7.4 Device Functional Modes
The TPD2E2U06-Q1 device is a passive integrated circuit that triggers when voltages are above VBR or below
the lower diodes Vf (–0.6 V). During ESD events, voltages as high as ±30 kV (air) can be directed to ground
through the internal diode network. When the voltages on the protected line fall below the trigger levels of the
TPD2E2U06-Q1 (usually within 10s of nano-seconds) the device reverts to passive.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPD2E2U06-Q1 device is a diode type TVS which is typically used to provide a path to ground for
dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the
current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the
voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe
level for the protected IC.
8.2 Typical Application
Power
Supply
Vbus
USB 2.0
Transceiver
USB 2.0
Connector
D+
D-
1
TPD2E2U06-Q1
2
3
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Typical USB Application Diagram
8.2.1 Design Requirements
For this design example, one TPD2E2U06-Q1 device will be used in a USB 2.0 application. This will provide
complete port protection.
Given the USB 2.0 application, the parameters listed in Table 8-1 are known.
Table 8-1. Design Parameters
10
DESIGN PARAMETER
VALUE
Signal range on pins 1 or 2
0 V to 3.3 V
Operating frequency
240 MHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD2E2U06-Q1 device has 2 identical protection channels for signal lines. The symmetry of the device
provides flexibility when selecting which of the 2 I/O channels will protect which signal lines. Any I/O will support
a signal range of 0 to 5.5 V.
8.2.2.2 Operating Frequency
The TPD2E2U06-Q1 device has a capacitance of 1.5 pF (typical), supporting USB 2.0 data rates.
8.2.3 Application Curve
1
0
Insertion Loss (dB)
±1
±2
±3
±4
±5
±6
±7
±8
±9
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
Frequency (Hz)
1.E+10
C010
Figure 8-2. Insertion Loss Graph
9 Power Supply Recommendations
This device is a passive ESD protection device and there is no need to power it. Make sure that the maximum
voltage specifications for each line are not violated.
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10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
This application is typical of a differential data pair application, such as USB 2.0.
IO1
GND
IO2
= VIA to GND
Figure 10-1. Routing with DBZ Package
12
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
•
•
Texas Instruments, Reading and Understanding an ESD Protection Data Sheet application report
Texas Instruments, ESD Protection Layout Guide application report
Texas Instruments, TPD4E02B04EVM user's guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
Ethernet™ is a trademark of Fuji Xerox Co., Ltd.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD2E2U06QDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
22U6Q
TPD2E2U06QDCKRQ1
ACTIVE
SC70
DCK
3
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11X
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of