TPD3F303DQDR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPD3F303 SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 TPD3F303 ESD Protection and EMI Filter for SIM Card Interface 1 Features 3 Description • The TPD3F303 device is a highly-integrated device that provides a three-channel Electromagnetic Interference (EMI) filter and a Transient Voltage Suppressor (TVS) based ESD protection diode array. The C-R-C based low-pass filter provides EMI protection for the data, clock, and reset lines of a SIM Card interface. Furthermore, the four-channel TVS Diode array provides IEC 61000-4-2 level 4 ESD protection for the previously mentioned signals (data, clock, reset) and the VCC power line. The TPD3F303 contains a 47-Ω termination resistor for the clock line and 100-Ω termination resistor for both the data and reset lines. The high level of integration offered by the TPD3F303 makes the device well-suited for applications like cell phones, tablets, hotspots, and PDAs. 1 • • • • • • Bidirectional EMI Filtering and Line Termination With Integrated ESD Protection – –3-dB Bandwidth 300 MHz IEC 61000-4-2 Level 4 ESD Protection – ±15-kV Contact Discharge – ±15-kV Air Gap Discharge DC Breakdown Voltage: 6 V (Minimum) Low Leakage Current: 0.1 µA (Maximum) Low Noise C-R-C Filter Topology Integrated VCC Clamp Eliminates the Need for External ESD Protection Space-Saving DPV (0.5-mm Pitch), DQD Packages (0.4-mm Pitch) Device Information(1) 2 Applications • • PART NUMBER End Equipment – Cell Phones – Tablets – PDAs – Hotspots Interfaces – SIM Cards TPD3F303 PACKAGE BODY SIZE (NOM) WSON (8) 1.35 mm × 1.70 mm USON (8) 1.60 mm × 2.10 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic Vcc SIM Card Socket Reset Reset 1 TPD3F303 8 CLK 2 7 3 6 4 5 CLK I/O GND I/O SIM Controller Vcc GND GND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD3F303 SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 3 3 4 4 4 4 5 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ ESD Ratings – Surge Protection............................... Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 6 7.1 Overview ................................................................... 6 7.2 Functional Block Diagram ......................................... 6 7.3 Feature Description................................................... 6 7.4 Device Functional Modes.......................................... 6 8 Application and Implementation .......................... 7 8.1 Application Information.............................................. 7 8.2 Typical Application ................................................... 7 9 Power Supply Recommendations........................ 9 10 Layout..................................................................... 9 10.1 Layout Guidelines ................................................... 9 10.2 Layout Example ...................................................... 9 11 Device and Documentation Support ................. 10 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 10 10 10 10 10 12 Mechanical, Packaging, and Orderable Information ........................................................... 10 4 Revision History Changes from Original (January 2011) to Revision A • 2 Page Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPD3F303 TPD3F303 www.ti.com SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 5 Pin Configuration and Functions DQD or DPV Package 8-Pin WSON or USON Top View DATA1_OUT 1 CLK_OUT 2 8 DATA1_IN 7 CLK_IN GND DATA2_OUT 3 6 DATA2_IN NC 4 5 V CC   Pin Functions PIN NAME NO. TYPE CLK_OUT 2 Output CLK_IN 7 Input DATA1_IN 8 DATA2_IN 6 DATA1_OUT 1 DATA2_OUT 3 GND GND NC 4 VCC 5 6 Input Output Ground No Connect DESCRIPTION Clock Input and Output signals. Data and Rest signals Input, Output pins. The DATA1 and DATA2 are symmetric circuits. They can be used interchangeably for either DATA or RESET pins based off board layout scheme. Ground connection for the EMI filter. It is very important to connect the device GND to the printed circuit board ground plane through Vias directly under the package. Not connected to any internal circuit. Leave this pin floating. Power Clamp ESD Clamp circuit for the VCC pin. Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN I/O voltage tolerance MAX 5.5 V TA Operating free-air temperature –40 85 °C Tstg Storage temperature –55 155 °C (1) I/O pins UNIT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) VALUE UNIT ±15000 V ±1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPD3F303 3 TPD3F303 SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 www.ti.com 6.3 ESD Ratings – Surge Protection VALUE V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±15000 IEC 61000-4-2 air-gap discharge ±15000 UNIT V 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIO Input pin voltage TA Operating free-air temperature MIN MAX 0 5.5 UNIT V –40 85 °C 6.5 Thermal Information TPD3F303 THERMAL METRIC (1) DPV (USON) DQD (WSON) 8 PINS 8 PINS 90 92.1 °C/W UNIT RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 93.4 103.3 °C/W RθJB Junction-to-board thermal resistance 41.1 36 °C/W ψJT Junction-to-top characterization parameter 7.9 6.5 °C/W ψJB Junction-to-board characterization parameter 41 35.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 15.6 16.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.6 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±10 V 0.1 µA 55 Ω Vclamp Clamp voltage II/O = ±2 A I/O pin to ground II Leakage current RPU = Open I/O pin to ground RCLK CLK series resistors 40 47 RDAT_RST Data/RST series resistors 85 100 115 Ω CTotal IO Capacitance VI/O = 0 V 16 20 24 pF VBR Break-down Voltage II/O = 1 mA F–3dB Z = 50 Ω –3-dB BW for DATA/RESET line SOURCE ZLOAD = 50 Ω 294 MHz F–3dB –3-dB BW for CLK line ZSOURCE = 50 Ω ZLOAD = 50 Ω 308 MHz 4 I/O Pins to GND Submit Documentation Feedback 6 V Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPD3F303 TPD3F303 www.ti.com SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 6.7 Typical Characteristics 100 1.0 90 0.8 80 0.6 IIO - Input Offset Current - mA IIO - Input Offset Current - pA VIO = 2.5 V 70 60 50 40 0.2 0.0 -0.2 30 -0.4 20 -0.6 10 0 -40 0.4 tA = 25°C -0.8 -15 10 35 60 TA - Free-Air Temperature - °C -1.0 -2 85 -1 0 1 2 3 4 5 6 VIO - Input Offset Voltage - V 7 8 VIO = 2.5 V Figure 1. IIO vs Temperature Figure 2. IIO vs VIO -0 0 0 V Bias -10 -5 -20 -10 CLK DATA -30 CLK_IN to DATA2_OUT -40 -15 Loss - dB Loss - dB -50 -20 -25 -30 -60 -70 -80 -90 -35 -100 -40 -110 DATA1_IN to DATA2_OUT -120 DATA1_IN to CLK_OUT -45 -50 1.0E+05 -130 1.0E+06 1.0E+07 1.0E+08 f - Frequency - Hz 1.0E+09 -140 1.0E+05 1.0E+10 1.0E+06 1.0E+07 1.0E+08 f - Frequency - Hz 1.0E+09 1.0E+10 Figure 4. Channel-to-Channel Crosstalk Figure 3. Frequency Response Data (0-V Bias) 35 TA = 25°C 30 Capacitance - pF 25 20 Data CLK 15 10 VCC 5 0 0 0.5 1 1.5 2 2.5 3 3.5 VBIAS - V 4 4.5 5 5.5 TA = 25°C Figure 5. Capacitance vs VBIAS Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPD3F303 5 TPD3F303 SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPD3F303 is a highly-integrated three-channel EMI filter and unidirectional TVS based protection diode array. This device can be used for a range of applications such as cell phones, tablets, hotspots, and PDAs. 7.2 Functional Block Diagram 45 Ω Pin 7 GND Schematic for CLK Line Pin 2 Pin 5 100 Ω Pin 6,8 GND Schematic for VCC Pin 1,3 GND Schematic for DATA1, DATA2 Lines Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Bidirectional EMI Filtering and Line Termination With Integrated ESD Protection This device provides bidirectional EMI filtering, integrated line-termination resistors, and integrated ESD protection. 7.3.2 IEC 61000-4-2 ESD Protection The ESD protection on all pins exceeds the IEC 61000-4-2 level 4 standard. Contact and air-gap ESD is rated at ±15 kV. 7.3.3 DC Breakdown Voltage The DC breakdown voltage of this device is 6 V minimum. 7.3.4 Low Leakage Current The I/O pins of this device feature a low leakage current of 0.1-µA maximum. 7.3.5 Low Noise C-R-C Filter Topology This device has a C-R-C filter topology composed of a series resistor with two capacitors in parallel with the I/O pins. The typical resistor value for the DATA1 and DATA2 pins is 100 Ω and 45 Ω for the CLK pins. The typical capacitance on all lines is 20 pF when biased at 0 V. 7.3.6 Integrated VCC Clamp This device integrates an ESD clamp for the VCC pin, which eliminates the need for additional components. 7.3.7 Space-Saving Packages The layout of this device makes it easy to add protection to existing layouts. The packages offer flow-through routing which requires minimal changes to existing layout for addition of these devices. Additionally, the device is offered in two small space-saving packages that take up minimal footprint on the board. 7.4 Device Functional Modes The TPD3F303 is a passive integrated circuit that triggers when voltages are above VBR or below Vf (–0.7 V). During ESD events, voltages as high as ±15 kV (air or contact) can be directed to ground through the internal diode network. When the voltages on the protected line fall below the trigger levels of TPD3F303 (usually within 10s of nanoseconds) the device reverts to passive. 6 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPD3F303 TPD3F303 www.ti.com SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPD3F303 is a diode type TVS + EMI filter which is used to provide a path to ground for dissipating ESD events on signal lines between a SIM card slot and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC across the termination resistors. 8.2 Typical Application Vcc SIM Card Socket Reset Reset 1 TPD3F303 8 CLK 2 7 3 6 4 5 CLK I/O SIM Controller Vcc GND I/O GND GND Copyright © 2016, Texas Instruments Incorporated Figure 6. Typical SIM Card Application 8.2.1 Design Requirements For this design example, one TPD3F303 is used to protect a SIM card interface. Table 1 lists the parameters for Figure 6. Table 1. Design Parameters PARAMETER VALUE Signal Range on Protected Lines 0 V to 5 V Required Level of IEC ESD Protection ±15-kV Contact, ±15-kV Air Gap 8.2.2 Detailed Design Procedure To begin the design process, some parameters must be decided upon; the designer must know the following: • Voltage range of the signal on all protected lines • Required ESD protection needed Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPD3F303 7 TPD3F303 SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 www.ti.com 8.2.2.1 Signal Range The TPD3F303 supports signal ranges from 0 V to 5.5 V, which supports the SIM card application 8.2.2.2 Required ESD Protection The TPD3F303 is rated to withstand up to ±15-kV contact and ±15-kV air gap IEC ESD. This meets the IEC ESD design target. 220 80 200 60 180 40 160 20 140 0 120 Amplitude - V Amplitude - V 8.2.3 Application Curves DATA_In 100 80 60 DATA_Out 40 -80 -100 -140 -20 -160 -40 -180 -60 -200 50 75 100 125 t - Time - nS 150 175 -220 0 200 220 220 200 200 180 180 160 160 50 75 100 125 t - Time - nS 150 175 200 Amplitude - V 140 120 DATA_In 100 80 60 DATA_Out 40 20 120 DATA_In 100 80 60 DATA_Out 40 20 0 0 -20 -20 -40 -40 -60 -60 -80 0 25 Figure 8. -15-kV IEC Contact, DATA1_In Stressed 140 Amplitude - V -60 -120 Figure 7. +15-kV IEC Contact, DATA1_In Stressed 25 50 75 100 125 t - Time - nS 150 175 200 Figure 9. +15-kV IEC Contact, CLK_In Stressed 8 -40 0 25 DATA_Out -20 20 -80 0 DATA_In -80 0 25 50 75 100 125 t - Time - nS 150 175 200 Figure 10. -15-kV IEC Contact, CLK_In Stressed Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPD3F303 TPD3F303 www.ti.com SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 9 Power Supply Recommendations This device is a passive ESD device, so there is no need to power it. Take care not to violate the recommended I/O specification (0 V to 5.5 V) to ensure the device functions properly. 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example To Controller To SIM Socket I/O I/O CLK CLK RESET RESET VCC VCC = Thermal Pad = VIA to GND Copyright © 2016, Texas Instruments Incorporated Figure 11. Typical SIM Card Layout Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPD3F303 9 TPD3F303 SLVSAM5A – JANUARY 2011 – REVISED APRIL 2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation, see the following: • ESD Protection Layout Guide, SLVA680 • Reading and Understanding an ESD Protection Datasheet, SLLA305 • Design Considerations for System-Level ESD Circuit Protection , SLYT492 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPD3F303 PACKAGE OPTION ADDENDUM www.ti.com 13-May-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD3F303DPVR ACTIVE USON DPV 8 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 6SS TPD3F303DQDR ACTIVE WSON DQD 8 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 6SS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of