TPD3S714-Q1
TPD3S714-Q1
SLVSCG4C – JANUARY 2016 – REVISED
AUGUST 2020
SLVSCG4C – JANUARY 2016 – REVISED AUGUST 2020
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TPD3S714-Q1 Automotive USB 2.0 Interface Protection With Short-to-Battery and
Short-Circuit Protection
1 Features
3 Description
•
The TPD3S714-Q1 is a single-chip solution for shortto-battery, short-circuit, and ESD protection for the
USB connector’s VBUS and data lines in automotive
USB hubs, head units, rear seat entertainment,
telematics, and media interface applications. The
integrated data switches provide best-in-class
bandwidth for minimal signal degradation during USB
short-to-battery events. The high bandwidth of 1 GHz
allows for a clean USB 2.0 high-speed (480 Mbps)
eye diagram with the long captive cables that are
common in the automotive USB environment
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified (Grade 1)
– Operating Temperature Range : –40°C to
+125°C
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Short-to-Battery (up to 18 V) and Short-to-Ground
Protection on VBUS_CON
Short-to-Battery (up to 18 V) and Short-to-VBUS
Protection on VD+, VD–
IEC 61000-4-2 ESD Protection on VBUS_CON,
VD+, VD–
– ±8-kV Contact Discharge
– ±15-kV Air Gap Discharge
ISO 10605 330-pF, 330-Ω ESD Protection on
VBUS_CON, VD+, VD–
– ±8-kV Contact Discharge
– ±15-kV Air Gap Discharge
Low RON nFET VBUS Switch (63-mΩ Typical)
High Speed Data Switches (1-GHz, –3-dB
Bandwidth)
Hiccup Current Limit
– 550-mA Overcurrent Limit (Minimum)
Fast Overvoltage Response Time
– 2-µs Typical (VBUS Switch)
– 200-ns Typical (Data Switches)
Integrated Input Enable for VBUS, VD+, VD–
Fault Output Signal
Thermal Shutdown Feature
16-Pin SSOP Package (4.9 mm × 3.9 mm)
2 Applications
•
•
End Equipment
– Head Units
– Rear Seat Entertainment
– Telematics
– USB Hub
– Navigation Modules
– Media Interface
Interfaces
– USB 2.0
The short-to-battery protection isolates the internal
system circuits from any overvoltage conditions at the
VBUS_CON, VD+, and VD– pins. On these pins, the
TPD3S714-Q1 can handle overvoltages up to 18 V for
hot plug and DC events. The overvoltage protection
circuit provides the most reliable short-to-battery
isolation in the industry, shutting off the switches and
protecting the upstream transceiver from harmful
voltage and current spikes. The VBUS_CON pin also
provides an accurate current limited load switch up to
0.5 A. The overcurrent protection automatically limits
current to prevent drooping of the upstream rail during
short-to-ground events. Additionally, this device also
integrates system level IEC 61000-4-2 and ISO 10605
ESD protection on VBUS_CON, VD+, and VD– pins
which removes the need to provide external highvoltage, low capacitance ESD diodes
Device Information (1)
PART NUMBER
TPD3S714-Q1
(1)
PACKAGE
BODY SIZE (NOM)
SSOP (16)
4.90 mm × 3.90 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
5V
VBUS
1 µF
100 V
X7R
VBUS_CON
VBUS_SYS
100 µF
7V
10 NŸ
FLT
D±
VDt
D±
VD+
D+
USB
Transceiver
10 nH
D+
USB2.0
CMC
10 nH
EN
GND
From Processor
GND
TPD3S714-Q1
VIN
3.3 V
1 µF
7V
Copyright © 2016, Texas Instruments Incorporated
Typical Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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© 2020 Texas
Instruments
Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings—AEC Specification............................... 4
6.3 ESD Ratings—IEC Specification................................ 4
6.4 ESD Ratings—ISO Specification................................ 4
6.5 Recommended Operating Conditions.........................4
6.6 Thermal Information....................................................5
6.7 Electrical Characteristics.............................................5
6.8 Timing Requirements.................................................. 8
6.9 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 12
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................16
9 Application and Implementation.................................. 17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................20
10.1 VBUS Path................................................................20
10.2 VIN Pin.....................................................................20
11 Layout........................................................................... 21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Documentation Support.......................................... 22
12.2 Receiving Notification of Documentation Updates..22
12.3 Support Resources................................................. 22
12.4 Trademarks............................................................. 22
12.5 Electrostatic Discharge Caution..............................22
12.6 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2017) to Revision C (August 2020)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
• Added functional safety link to the Features section.......................................................................................... 1
Changes from Revision A (April 2016) to Revision B (August 2017)
Page
• Updated ESD Protection on VBUS_CON, VD+, VD– section...............................................................................15
Changes from Revision * (January 2016) to Revision A (April 2016)
Page
• Updated Typical Application Schematic, Figure 7-1 and Figure 7-2 ..................................................................1
• Updated Electrical Characteristics table............................................................................................................. 1
• Added content to Short-to-Battery Tolerance .....................................................................................................1
• Updated IEC waveform graphs with cleaner data in Typical Characteristics .....................................................1
2
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5 Pin Configuration and Functions
NC
V
V
1
16
NC
2
15
V
3
14
V
GND
4
13
GND
VD–
5
12
GND
VD+
6
11
EN
D-
7
10
FLT
D+
8
9
BUS_CON
BUS_CON
V
BUS_SYS
BUS_SYS
IN
Figure 5-1. DBQ Package 16-Pin SSOP Top View
Pin Functions
PIN
NO.
1
NAME
TYPE
DESCRIPTION
NC
NC
VBUS_CON
O
GND
Ground
5
VD–
I/O
Connect to USB connector D–; provides IEC 61000-4-2 ESD protection
6
VD+
I/O
Connect to USB connector D+; provides IEC 61000-4-2 ESD protection
7
D–
I/O
Connect to internal D– transceiver
8
VD+
I/O
Connect to internal D+ transceiver
2
3
4
No connect, leave floating or connect to ground. Do not connect to VBUS_CON
Connect to USB connector VBUS_CON; provides IEC 61000-4-2 ESD protection
Connect to PCB ground plane
9
VIN
I
Connect to 3.3-V I/O. Controls the OVP threshold for VD+/VD–
10
FLT
O
Open-Drain fault pin. Refer device description for operation
11
EN
I
Enable Active-Low Input. Drive EN low to enable the device. Drive EN high to disable the
device
GND
Ground
Connect to PCB ground plane
VBUS_SYS
I
Connect to internal VBUS plane
NC
NC
12
13
14
15
16
No connect, leave floating or connect to ground. Do not connect to VBUS_CON
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
Supply voltage from USB connector
–0.3
18
V
VBUS_SYS
Internal supply DC voltage rail on the PCB
–0.3
6
V
VD+, VD–
Voltage range from connector-side USB data lines
–0.3
18
V
VBUS_CON
UNIT
D+, D–
Voltage range for internal USB data lines
–0.3
VIN + 0.3
V
VIN
Voltage range for VIN supply input
–0.3
4
V
EN
Voltage on enable pin
7
V
TA
Operating free air temperature
–40
125
°C
TSTG
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
6.2 ESD Ratings—AEC Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
IEC 61000-4-2, VBUS_CON, VD
+, VD– pins
discharge(1)
±8000
Air-gap discharge(1)
±15000
Contact
UNIT
V
See the ESD System Test Setup diagram for details on system level ESD testing setup.
6.4 ESD Ratings—ISO Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
ISO 10605 (330 pF, 330 Ω),
VBUS_CON, VD+, VD– pins
Contact discharge(1)
±8000
Air-gap discharge(1)
±15000
UNIT
V
See the ESD System Test Setup diagram for details on system level ESD testing setup.
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VBUS_CON
MAX
UNIT
5.25
V
VBUS_SYS
Internal supply DC voltage rail on the PCB
4.75
5.25
V
VD+, VD–
Voltage range from connector-side USB data lines
0
VIN + 0.3
V
D+, D–
Voltage range for internal USB data lines
0
VIN + 0.3
V
VIN
Voltage range for VIN supply
3
3.6
V
IBUS
Current through VBUS switch
500
mA
EN
Voltage range for enable
5.9
V
CSYS
4
NOM
Supply voltage from USB connector
Input
capacitance(1)
0
VBUS_SYS pin
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6.5 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
CLOAD
CVIN
(1)
Output load capacitance(1)
VIN
capacitance(1)
NOM
MAX
UNIT
VBUS_CON pin
1
µF
VIN pin
1
µF
See Figure 9-1 for configuration details
6.6 Thermal Information
TPD3S714-Q1
THERMAL METRIC(1)
DBQ (SSOP)
UNIT
16 PINS
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance
ψJT
ψJB
θJCbot
(1)
98.8
°C/W
48
°C/W
41.6
°C/W
Junction-to-top characterization parameter
8.5
°C/W
Junction-to-board characterization parameter
41.2
°C/W
Junction-to-case (bottom) thermal resistance
N/A
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Electrical Characteristics
over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON =
float (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT CONSUMPTION
IVBUS_SLEEP
VBUS sleep current consumption
Measured at VBUS_SYS pin, EN = 5 V
IVBUS
VBUS operating current consumption
Measured at VBUS_SYS pin
45
150
µA
285
380
µA
IVIN
Leakage current for VIN
Measured at VIN pin, VIN = 3.6 V
ION(LEAK)
Leakage through VBUS while shorted to battery
and powered on
Measured flowing in to VBUS_SYS pin, VBUS_SYS
= 5 V, VBUS_CON = 18 V
12
25
µA
120
µA
IOFF(LEAK)
Leakage through VBUS while shorted to battery
and unpowered
Measured flowing out of VBUS_SYS pin,
VBUS_SYS = 0 V, VBUS_CON = 18 V
50
µA
IVD(OFF_LEAK)
Leakage into data path while shorted to battery
and unpowered
Measured flowing in to VD+ or VD– pins,
VBUS_SYS = 0 V, VD+ or VD– = 18 V, VIN = 0 V,
D+/D– = 0 V
80
µA
IVD(ON_LEAK)
Leakage into data path while shorted to battery
and powered on
Measured flowing in to VD+ or VD– pins,
VBUS_SYS = 5 V, VD+ or VD– = 18 V, D+/D– = 0
V
80
µA
Undervoltage lockout rising for
VIN
Ramp VIN down until FLT is deasserted, EN = 5
V
2.6
2.7
2.9
Ramp VIN until FLT is asserted, EN = 5 V
2.5
2.6
2.8
1.2
VIN PIN
VUVLO(RISING)
VUVLO(FALLING)
Undervoltage lockout falling
for VIN
VIN
V
EN, FLT PINS
VIH
High-level input voltage
EN
Set EN = 0 V; Sweep EN to 1.4 V; Measure
when FLT is asserted
VIL
Low-level input voltage
EN
Set EN = 3.3 V; Sweep EN from 3.3 V to 0.5 V;
Measure when FLT is deasserted
IIL
Input leakage current
EN
V(EN) = 3.3 V ; Measure Current into EN pin
VOL
Low-level output voltage
FLT
IOL = 3 mA
VBUS
Progressively load VBUS_CON until device
asserts FLT
V
0.8
V
1
µA
0.4
V
850
mA
OCP CIRCUIT—VBUS
ILIM
Overcurrent limit
550
700
OVERTEMPERATURE PROTECTION
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6.7 Electrical Characteristics (continued)
over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON =
float (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TSD(RISING)
The rising overtemperature protection shutdown
threshold
VBUS_SYS = 5 V, EN = 0 V, No Load on
VBUS_CON, TA stepped up until FLT is asserted
150
165
180
℃
TSD(FALLING)
The falling overtemperature protection shutdown
threshold
VBUS_SYS = 5 V, EN = 0 V, No Load on
VBUS_CON, TA stepped down from TSD(RISING)
until FLT is deasserted
125
130
140
℃
TSD(HYST)
The overtemperature protection shutdown
threshold hysteresis
TSD(RISING) – TSD(FALLING)
10
35
55
℃
5.4
5.6
5.8
V
OVP CIRCUIT—VBUS
VOVP(RISING)
Input overvoltage protection
threshold
VBUS_CON
Increase VBUS_CON from 5 V to 7 V. Measure
when FLT is asserted
VHYS(OVP)
Hysteresis on OVP
VBUS_CON
Difference between rising and falling OVP
thresholds on VBUS_CON
TOVP(FALLING)
Input overvoltage protection
threshold
VBUS_CON
Decrease VBUS_CON from 7 V to 5 V. Measure
when FLT is deasserted
VUVLO(SYS_RISING)
Undervoltage lockout rising for
VBUS_SYS
VBUS_SYS
VBUS_SYS voltage rising from 0 V to 5 V
3.1
VHYS(UVLO_SYS)
VBUS_SYS UVLO hysteresis
VBUS_SYS
Difference between rising and falling UVLO
thresholds on VBUS_SYS
VUVLO(SYS_FALLING)
Undervoltage lockout falling
for VBUS_SYS
VBUS_SYS
VBUS_SYS voltage falling from 7 V to 3 V
VSHRT(RISING)
Short-to-ground comparator
rising threshold
VBUS_CON
VSHRT(FALLING)
Short-to-ground comparator
falling threshold
VSHRT(HYST)
ISHRT
50
5.36
mV
5.74
V
3.3
3.6
V
50
75
100
mV
3
3.2
3.5
V
Increase VBUS_CON voltage from 0 V until the
device transitions from the short-circuit to overcurrent mode of operation
2.5
2.6
2.7
V
VBUS_CON
Set VBUS_SYS = 5 V; VIN = 3.3 V; EN = 0 V;
Decrease VBUS_CON voltage from 5 V until the
device transitions from the overcurrent to shortcircuit mode of operation
2.4
2.5
2.6
V
Short-to-ground comparator
hysteresis
VBUS_CON
Difference between VSHRT(RISING) and
VSHRT(FALLING)
100
125
150
mV
Short-to-ground current
source
VBUS_CON
Current sourced from VBUS_SYS when device is
in short-circuit mode
150
350
mA
VIN +
0.6
OVP CIRCUIT—VD+/VD–
VOVP(RISING)
Input overvoltage protection
threshold
VD+/VD–
Increase VD+ or VD– (with D+ and D–) from
3.3 V to 4.5 V. Measure the value at which FLT
is asserted
VHYS(OVP)
Hysteresis on OVP
VD+/VD–
Difference between rising and falling OVP
thresholds on VD+/VD–
VOVP(FALLING)
Input overvoltage protection
threshold
VD+/VD–
Decrease VD+ or VD– (with D+ or D–) from 4.5
V to 2 V. Measure the value at FLT is
deasserted
VIN +
0.8
VIN + 1
50
VIN +
0.525
VIN +
0.75
V
mV
VIN +
0.975
V
18
V
18
V
SHORT-TO-BATTERY
V(VBUS_STB)
VBUS hotplug short-to-battery
tolerance
VBUS_CON
V(DATA_STB)
Data line hotplug short-tobattery tolerance
VD+/VD–
Charge battery-equivalent capacitor to test
voltage then discharge to pin under test
through a 1-meter, 18-gauge wire. (See Figure
7-1 for more details)
DATA LINE SWITCHES—VD+ to D+ or VD–to D–
6
CON
Equivalent on capacitance
Capacitance of D+/D– switches when enabled measure on connector side across bias voltage
0 V to 0.4 V
RON
On resistance
Measure resistance between D+ and VD+ or
D– and VD–, voltage between 0 and 0.4 V
RON(Flat)
On resistance flatness
BWON
On bandwidth (–3 dB)
6.2
pF
4
6.5
Ω
Measure resistance between D+ and VD+ or
D– and VD–, sweep voltage between 0 V and
0.4 V
0.2
1
Ω
Measure S21 bandwidth from D+ to VD+ or D–
to VD– with voltage swing = 400 mVpp, VCM=
0.2 V
860
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6.7 Electrical Characteristics (continued)
over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON =
float (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BWON_DIFF
On bandwidth (–3 dB)
Measure SDD21 bandwidth from D+ to VD+ and
D– to VD– with voltage swing = 800 mVpp
differential, VCM = 0.2 V
1050
MHz
Xtalk
Crosstalk
Measure S21 bandwidth from D+ to VD– or D–
to VD+ with voltage swing = 400 mVpp. Be
sure to terminate open sides to 50 ohms. f =
480 MHz
–34
dB
nFET SWITCH—VBus
R(DISCHARGE)
Output discharge resistance
EN = 5 V, Set VBUS_CON = 5 V and measure
current flow to ground
RON
Switch ON resistance
VBUS_CON = 5 V, IOUT = 0.5 A
12500
63
150
Ω
mΩ
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6.8 Timing Requirements
over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON =
float (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE PIN
tON
Enable on time
Time between enable device until FLT deasserts
13
ms
OVERCURRENT PROTECTION
tBLANK
Overcurrent blanking time
Time from overcurrent condition until FLT assertion and
VBUS FET turnoff
tRETRY
Overcurrent retry time
Time from overcurrent FET shut off until FET turns back
on
tRECV
Overcurrent recovery time
2
ms
100
ms
Time from end of tRETRY until FLT deassertion if
overcurrent condition is removed
8
ms
OVERVOLTAGE PROTECTION
tOVP_response
OVP response time – VBUS
Measured from OVP Condition to FET turnoff
2
tOVP_response
OVP response time – data
switches
Measured from OVP Condition to FET turnoff
200
4
µs
ns
SHORT-TO-GROUND PROTECTION
tSHRT
8
Short to ground response time
CLOAD = 0 uF, Time from short condition until current falls
below 120% of ISHRT
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2
4
µs
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6.9 Typical Characteristics
120
40
VDD-
100
0
Vonltage (V)
Voltage (V)
80
60
40
-20
-40
20
-60
0
-80
-20
-15
0
15
30
45
Time (ns)
60
75
90
-100
-15
0
30
45
60 75
Time (ns)
90
105 120 135 150
D002
Figure 6-2. –8-kV IEC Contact Waveform
8
0.75
7
0.50
6
0.25
5
Voltage (V)
1.00
0.00
-0.25
Vbus_con
EN
FLT
4
3
2
-0.50
VD-
-0.75
1
VD+
0
-1.00
0
±5
5
10
15
20
Voltage (V)
0
25
5
10
15
20
Time (ms)
C003
C004
Figure 6-4. VBUS tON Time
Figure 6-3. Data Line I-V Curve
125
6
5
100
Leakage Current (nA)
Current (µA)
15
D001
Figure 6-1. 8-kV IEC Contact Waveform
Current (mA)
VDD-
20
4
3
2
75
50
25
1
0
0
±40
±20
0
20
40
60
Temperature (ƒC)
80
100
120
±40
Figure 6-5. VD± Short-to-5 V (while Enabled)
Across Temperature
±20
0
20
40
60
Temperature (ƒC)
C005
80
100
120
C006
Figure 6-6. VD± Short-to-5 V (while Unpowered)
Across Temperature
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100
6
5
Leakage Current (µA)
80
4
RON (Ÿ)
60
40
3
2
-40C
25C
85C
125C
1
Powered, Enabled
Unpowered
0
0
±20
0
20
40
60
80
100
120
Temperature (ƒC)
Figure 6-7. VD± Short-to-18 V Across Temperature
0.1
0.2
6
Vbus_con
FLT
1400
I_Vbus_sys
1200
5
1000
4
800
3
600
2
400
1
200
0.4
C008
Figure 6-8. Data Switch RON vs Bias Voltage
1600
7
0.3
Bias Voltage (V)
8
1600
Vbus_con
FLT
I_Vbus_sys
7
6
Voltage (V)
8
Voltage (V)
0
C007
1400
1200
5
1000
4
800
3
600
2
400
1
200
0
0
0
0
0.2
0.4
0.6
0.8
1
Time (ms)
1.2
1.4
0
0
1.8
1.6
Voltage (V) or Current (A) on VBUS_CON
Voltage (V) or Current (A)
6
5
4
3
2
1
0
100 120 140 160 180 200
C010
10
Vbus_con
I_Vbus_con
Vbus_sys
FLT
40
8
30
6
20
4
10
2
0
0
-2
±10
-4
0
5
10
15
20
Time (µs)
25
30
35
40
C011
Figure 6-11. VBUS Short-to-Ground Response
Waveform
10
80
±20
±1
±2
0
60
50
Vbus_con
I_Vbus_con
Vbus_sys
FLT
7
40
Figure 6-10. Overcurrent tBLANK_RETRY Response
Waveform
Figure 6-9. Overcurrent tBLANK Response
Waveform
8
20
Time (ms)
D009
Current (mA)
±40
Voltage (V) on VBUS_SYS and FLT
20
5
10
15
20
25
30
Time (µs)
C012
Figure 6-12. VBUS Short-to-18 V Response
Waveform
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10
8
6
6
4
4
2
2
0
0
-2
±2
0
0.5
1
1.5
20
10
15
7.5
10
5
5
2.5
0
0
-2.5
±5
0
2
Time (µs)
12.5
VDI_VDFLT
D-
Voltage (V) on D- and FLT
8
Voltage (V) or Current (A) on VD-
10
25
12
VDI_VDFLT
D-
Voltage (V) on D- and FLT
Voltage (V) or Current (A) on VD-
12
0.5
1
1.5
2
Time (µs)
C013
C014
Figure 6-13. Data Switch Short-to-5 V Response
Waveform
Figure 6-14. Data Switch Short-to-18 V Response
Waveform
Figure 6-15. USB2.0 Eye Diagram (No TPD3S714Q1)
Figure 6-16. USB2.0 Eye Diagram (With TPD3S714Q1)
0
0
Insertion Loss (dB)
Insertion Loss (dB)
±1
±2
±3
±4
±3
±6
±9
±5
±6
1.E+07
1.E+08
Frequency (Hz)
±12
1.E+07
1.E+09
Figure 6-17. Data Switch Differential Bandwidth
1.E+08
Frequency (Hz)
C015
1.E+09
C016
Figure 6-18. Data Switch Single-Ended Bandwidth
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0
D- to VD+
D+ to VD-
Crosstalk (dB)
±10
±20
±30
±40
±50
±60
0.E+00
1.E+09
2.E+09
3.E+09
Frequency (Hz)
C017
Figure 6-19. Data Switch Crosstalk
7 Parameter Measurement Information
5V
VBUS_CON
STB Strike Output
100 µF
7V
10 NŸ
FLT
VDt
D±
VD+
D+
GND
EN
10 nH
1 m cable
DC Power
Supply
VBUS_SYS
1 µF
100 V
X7R
USB2.0
CMC
STB
Strike
Output
22 mF
35 V
10 nH
45 Ÿ
45 Ÿ
From GPIO
TPD3S714-Q1
VIN
3.3 V
1 µF
7V
STB Test Aparatus
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. Short-to-Battery System Test Setup
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5V
ESD Strike Points
1 µF
100 V
X7R
VBUS_CON
VBUS_SYS
10 NŸ
100 µF
7V
FLT
VDt
D±
10 nH
USB2.0
CMC
10 nH
45 Ÿ
D+
VD+
45 Ÿ
EN
GND
From GPIO
TPD3S714-Q1
VIN
3.3 V
1 µF
7V
Copyright © 2016, Texas Instruments
Incorporated
Figure 7-2. ESD System Test Setup
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8 Detailed Description
8.1 Overview
The TPD3S714-Q1 provides a single-chip ESD protection and overvoltage protection solution for automotive
USB interfaces. It offers short to battery protection up to 18 V and short to ground protection on VBUS_CON. The
TPD3S714-Q1 also provides a FLT pin that indicates to the system if a fault condition has occurred. The
TPD3S714-Q1 offers ESD clamps on the VBUS_CON, VD+, and VD– pins, thus eliminating the need for external
TVS clamp circuits in the application.
The TPD3S714-Q1 has internal circuitry that controls the turnon of the internal nFET switches. An internal
oscillator controls the timers that enable the switches and resets the open-drain FLT output. If VBUS_CON is less
than VOVP, the switches are enabled. After an internal delay, the charge-pump starts-up, turns on the internal
nFET switch through a soft start. Once the nFET is completely turned ON, TPD3S714-Q1 releases FLT pin to
HIGH. At any time, if any of the external pins rise above VOVP, FLT pin is pulled LOW. The nFET switches are
turned OFF.
8.2 Functional Block Diagram
BUS_SYS
BUS_CON
ESD
Clamp
ShorttoGround
Detection
UVLO
+
Overcurrent
Detection
Control
Logic
Overvoltage
Protection
FLT
EN
VIN
VD+
D+
ESD Clamps
D±
VD±
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 AEC-Q100 Qualified
The TPD3S714-Q1 is an automotive qualified device according to the AEC-Q100 standards. This device is
qualified to operate from –40 to +125°C ambient temperature.
8.3.2 Short-to-Battery and Short-to-Ground Protection on VBUS_CON
The VBUS_CON pin is protected against shorts to battery and shorts to ground.
Once a voltage on VBUS_CON is detected as too low (below the VSHRT threshold) after the device is enabled, the
device enters short-circuit protection mode and assert FLT. It sources the ISHRT current until it detects the
voltage rising above the VSHRT threshold, where it resumes standard operating mode and deassert FLT.
14
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Once a voltage above the VOVP threshold is detected by the device, it shuts off all FETs and asserts a fault on
the FLT pin. Once the excessive voltage is removed, the device automatically re-enables and FLT deasserts
(see the Timing Requirements table for more details).
8.3.3 Short-to-Battery and Short-to-VBUS Protection on VD+, VD–
The VD+ and VD– pins are protected against shorts to battery and shorts to bus. The OVP threshold on the VD+
and VD– pins is low enough that it protects against shorts to VBUS.
Once a voltage above the VOVP threshold is detected by the device, it shuts off all FETs and asserts a fault on
the FLT pin. Once the excessive voltage is removed, the device automatically re-enables and FLT deasserts.
8.3.4 ESD Protection on VBUS_CON, VD+, VD–
The protected pins (VBUS_CON, VD+, VD–) are tested to pass the IEC 61000-4-2 ESD standard up to Level 4
ESD protection. Additionally, these pins are tested against ISO 10605 with the 330-pF, 330-Ω equivalent
network. This guarantees passing of at least ±8-kV contact discharge and ±15-kV air gap discharge according to
both standards using test setup shown in Figure 7-2.
8.3.5 Low RON nFET VBUS Switch
The VBUS switch has a low RON that provides minimal voltage droop from system to connector. Typical
resistance is 63 mΩ and is specified for 150 mΩ at 125°C ambient temperature.
8.3.6 High Speed Data Switches
The D+ and D– switches have a very low capacitance and a high bandwidth (1-GHz typical), allowing for a clean
USB 2.0 eye diagram.
8.3.7 Hiccup Current Limit
The VBUS path of this device has an integrated overcurrent protection circuit. Above the overcurrent threshold
(550-mA minimum), the device goes into a fault state where it limits current to the threshold. After a short
blanking time, the device cycles on and off to try to check if the connected device is still in overcurrent.
8.3.8 Fast Overvoltage Response Time
The overvoltage FETs are designed to have a fast turnoff time to protect the upstream SoC as quickly as
possible. Typical response time for complete turnoff is 2 µs for the VBUS path and 200 ns for the data path.
8.3.9 Integrated Input Enable
The TPD3S714-Q1 has an enable input to turn on and off the device. The EN pin disables and enables the VBUS
and data paths.
8.3.10 Fault Output Signal
The TPD3S714-Q1 has a fault pin, FLT that indicates when there is any sort of fault condition because of OVP,
OCP, or short-circuit.
8.3.11 Thermal Shutdown Feature
In the event that the device exceeds the maximum allowable junction temperature, it shuts down the device to
prevent damage to itself and indicate via the fault pin.
8.3.12 16-pin SSOP Package
This device is packaged in a standard 16-pin SSOP leaded package.
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8.4 Device Functional Modes
8.4.1 Normal Operation
The TPD3S714-Q1 operates normally (all FETs on) when enabled, both VBUS_SYS and VIN are above their UVLO
thresholds, and the device is not in any fault conditions.
8.4.2 Overvoltage Condition
When the VD+, VD–, or VBUS_CON pins exceed their OVP threshold, the device enters the overvoltage state. All
FETs are disabled and the FLT pin is asserted. Once the protected pins drop below their OVP threshold, the
device automatically turns back on.
8.4.3 Overcurrent Condition
When the current through the VBUS path exceeds the ILIM current threshold, the device enters into the
overcurrent state. The TPD3S714-Q1 limits current to the ILIM threshold by dropping voltage across the VBUS
FET to maintain constant current. Once it continues to sense an overcurrent condition for the blanking time
tBLANK, the device disables itself for the retry time, tRETRY and then retry automatically for the retry time,
tBLANK_RETRY. In the event that the current is below the overcurrent threshold, the device deasserts fault and
resumes normal operation.
8.4.4 Short-Circuit Condition
When the voltage on the VBUS_CON side drops below the VSHRT threshold while enabled, the TPD3S714-Q1
enters the short-circuit mode. It sources a constant current of ISHRT until it rises above the VSHRT threshold. Once
that occurs, the device automatically re-enters normal operation and deasserts fault.
8.4.5 Device Logic Tables
Table 8-1 shows the TPD3S714-Q1 VBUS Logic Table.
Table 8-1. TPD3S714-Q1 VBUS Logic Table
VOLTAGE CONDITION
CURRENT CONDITION
VBUS_CON
VBUS_SYS
EN
CURRENT FLOW
X
UVLO
Low
VBUS_SYS to VBUS_CON
X
>UVLO
High
No Flow
COMMENT
FLT PIN
Switch off because of UVLO
High-Z
Current flows through the switch, normal host
mode
High-Z
Switch off
Low
Low
UVLO
Low
VBUS_SYS to VBUS_CON
Current flow through switch, device detects short
circuit, current limited to ISHRT
X
X
Low
>OCP
Device switches off because of overcurrent limit,
auto-retrys until OVP
>UVLO
Low
No Flow
Switch off because of OVP
Low
X
X
X
No Flow
Thermal Shutdown Condition
Low
Table 8-2 shows the TPD3S714-Q1 Data Line Logic Table
Table 8-2. TPD3S714-Q1 Data Line Logic Table
VOLTAGE CONDITION
VD+/VD–
16
CURRENT CONDITION
EN
SWITCHES ON?
COMMENT
OVP
Low
No
Switches off because of OVP limit
Low
X
X
No
Thermal Shutdown Condition
Low
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FLT PIN
High-Z
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TPD3S714-Q1 offers fully featured automotive USB2.0 protection including short-to-battery, overcurrent,
and ESD protection. Care must be taken during the implementation to make sure the device provides adequate
protection to the system.
9.2 Typical Application
Figure 9-1 shows a fully featured USB2.0 high speed port, with an 18-V short-to-battery requirement on the
connector side.
5V
VBUS
VBUS_CON
1 µF
100 V
X7R
VBUS_SYS
100 µF
7V
10 NŸ
FLT
D±
VDt
D±
VD+
D+
USB
Transceiver
10 nH
D+
10 nH
USB2.0
CMC
EN
GND
From Processor
GND
TPD3S714-Q1
VIN
3.3 V
1 µF
7V
Copyright © 2016, Texas Instruments Incorporated
Figure 9-1. Typical Application Configuration for TPD3S714-Q1
9.2.1 Design Requirements
For this design example, the input parameters shown in Table 9-1 are used:
Table 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Short-to-battery tolerance on VD+, VD–, VBUS_CON
18 V
Maximum current in normal operation on VBUS
500 mA
USB data rate
480 Mbps
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9.2.2 Detailed Design Procedure
To begin the design process, the designer must know the following parameters:
• Short-to-Battery tolerance on connector pins
• Maximum current in normal operation on VBUS
• USB Data Rate
9.2.2.1 Short-to-Battery Tolerance
The TPD3S714-Q1 is capable of handling up to 18-V DC on the VD+, VD–, and VBUS_CON pins. In the event of a
short-to-battery on VBUS_CON, significant ringing is expected because of the hot plug-like nature of the short-tobattery event. In typical ceramic capacitor configurations, a standard RLC response is expected which results in
a ringing of nearly two times the applied DC voltage. The TPD3S714-Q1 is capable of withstanding the transient
ringing from hot plug-like events, assuming some precautions are taken.
Careful capacitor selection on the VBUS_CON pin must be observed. A capacitor with a low derating percentage
under the applied voltages must be used to prevent excess ringing. In the example, a 1-µF 100-V tolerant
ceramic X7R capacitor is used. It is best practice to carefully select the capacitors used in this circuit to prevent
derating-based voltage spikes under hot plug events. See the application example graphs, Figure 9-4 and Figure
9-5 to compare ringing of a 100-V capacitor to a 50-V capacitor. Figure 9-6 shows the 100-V capacitor with the
TPD3S714-Q1 installed.
Another alternative to a high rated ceramic capacitor is to implement either a standard R-C snubber circuit, or a
small external TVS diode. Depending on the short-to-battery tolerance needed, no special precautions may be
needed.
For more information on this topic, see the white paper Designing USB for short-to-battery tolerance in
automotive environments.
9.2.2.2 Maximum Current on VBUS
The TPD3S714-Q1 is capable of operating up to 5500 mA of current (minimum) until going into current limit
mode. In this example, the maximum current for USB2.0 of 500 mA has been chosen.
9.2.2.3 USB Data Rate
The TPD3S714-Q1 is capable of operating at the maximum USB2.0 High Speed data rate of 480 Mbps because
of the high data switch bandwidth of 1 GHz (typical). In this design example the maximum data rate of 480 Mbps
has been chosen.
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9.2.3 Application Curves
Figure 9-2. USB2.0 Eye Diagram (Board Only,
Through Path)
Figure 9-3. USB2.0 Eye Diagram (System from
Typical Application Schematic)
40
60
Voltage
Voltage
Current
Voltage (V) or Current (A)
Voltage (V) or Current (A)
50
40
30
20
10
0
Current
30
20
10
0
±10
±10
±20
±20
±10
0
10
20
30
40
50
60
70
Time (µs)
0
±10
20
30
40
Time (µs)
Figure 9-4. 50-V, 1-µF X7R Ceramic Shorted to 18-V
(Not Recommended)
50
60
70
C019
Figure 9-5. 100-V, 1-µF X7R Ceramic Shorted to 18
V
40
Voltage (V) or Current (A)
10
C018
Voltage
Current
30
20
10
0
±10
±20
±10
0
10
20
30
40
50
Time (µs)
60
70
C020
Figure 9-6. TPD3S714-Q1 and 100-V, 1-µF X7R Shorted to 18 V (Powered Off)
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10 Power Supply Recommendations
10.1 VBUS Path
The VBUS_SYS pins provide power to the chip and supply current through the load switch to VBUS_CON. A 100-µF
bulk capacitor is recommended on VBUS_SYS to supply the USB port and maintain compliance. A 1-µF capacitor
is recommended on the VBUS_CON pin with adequate voltage rating to tolerate short-to-battery conditions. A
supply voltage above the UVLO threshold for VBUS_SYS must be supplied for the device to power on.
10.2 VIN Pin
The VIN pin provides a voltage reference for the data switch OVP level as well as a bypass for ESD clamping. A
1-µF capacitor must be placed as close to the pin as possible and the supply must be set to be above the UVLO
threshold for VIN.
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11 Layout
11.1 Layout Guidelines
Proper routing and placement maintains signal integrity for high-speed signals. The following guidelines apply to
the TPD3S714-Q1:
• Place the bypass capacitors as close as possible to the VIN, VBUS_SYS, and VBUS_CON pins. Capacitors must
be attached to a solid ground. This minimizes voltage disturbances during transient events such as short-tobattery, ESD, or overcurrent conditions.
• High speed traces (data switch path) must be routed as straight as possible and any sharp bends must be
minimized.
Our standard ESD recommendations apply to the VD+, VD–, and VBUS_CON pins as well:
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
Figure 11-1 shows a full layout for a standard USB2.0 port. A common mode choke and inductors are used on
the high speed data lines, and the requisite bypassing caps are placed on VBUS_CON, VBUS_SYS, and VIN.
VBUS
N.C.
D-
N.C.
VBUS_CON
VBUS_SYS
VBUS_CON
VBUS_SYS
GND
GND
TPD3S714-Q1
D+
Legend
GND
USB2.0 Connector
VD-
GND
VD+
EN
To Processor
D-
FLT
To Transceiver
D+
VIN
Pin to GND
VIA to 3.3V Plane
VIA to 5V Plane
VIA to GND Plane
To Transceiver
To Transceiver
Figure 11-1. Typical Layout Example for TPD3S714-Q1
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
TPD3S714-Q1EVM User’s Guide
Reading and Understanding an ESD Protection Datasheet
ESD Layout Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
16
1
14X .0250
[0.635]
2X
.175
[4.45]
.189-.197
[4.81-5.00]
NOTE 3
8
9
B
16X .008-.012
[0.21-0.30]
.150-.157
[3.81-3.98]
NOTE 4
.007 [0.17]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[ 0.11 -0.25]
0 -8
.016-.035
[0.41-0.88]
(.041 )
[1.04]
DETAIL A
TYPICAL
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
24
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPD3S714-Q1
TPD3S714-Q1
www.ti.com
SLVSCG4C – JANUARY 2016 – REVISED AUGUST 2020
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPD3S714-Q1
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD3S714QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RJ714Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
