TPD4E110DPWR

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software TPD4E110 SLVSC54B – JULY 2013 – REVISED APRIL 2014 TPD4E110 4 Channel Protection Solution for Super-Speed (Up to 6 GBPS) Interface 1 Features 3 Description • The TPD4E110 is a uni-directional Electrostatic Discharge (ESD) protection device with ultra-low capacitance. The device is constructed with a central ESD clamp and features two hiding diodes per channel to reduce the capacitive loading. Each channel is rated to dissipate ESD strikes above the maximum level specified in the IEC61000-4-2 level 4 international standard. The TPD4E110's ultra-low loading capacitance makes the device ideal for protecting high-speed signal pins. 1 • • • • • • • • Provides System Level ESD Protection for LowVoltage IO Interface IO Capacitance 0.45pF (Typ) IEC 61000-4-2 Level 4 – ±12kV (Contact Discharge) – ±15kV (Air Gap Discharge) IEC61000-4-5 (Surge): 2.5A (8/20 µs) DC Breakdown Voltage 6.5V (Min) Ultra Low Leakage Current 1nA (Max) Low ESD Clamping Voltage Industrial Temperature Range: –40°C to 125°C Space Minimizing 0.8mm x 0.8mm DPW Package Device Information ORDER NUMBER TPD4E110DPW PACKAGE X2SON (4) BODY SIZE 0,8 mm x 0,8 mm white space 2 Applications white space • • • • • • white space USB 3.0 HDMI 2.0 LVDS DisplayPort PCI Express eSata Interfaces white space white space Circuit Protection Scheme IO1 IO3 IO2 IO4 4 Simplified Schematic Insertion Loss 1 Tx 0 GND 3 4 Gain (dB) 2 System Connector -1 1 -2 -3 -4 -5 Rx -6 100000 1000000 1E+7 1E+8 Frequency (Hz) 1E+9 1E+10 D003 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD4E110 SLVSC54B – JULY 2013 – REVISED APRIL 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Terminal Configuration and Functions................ Specifications......................................................... 1 1 1 1 2 3 3 7.1 7.2 7.3 7.4 7.5 7.6 3 3 3 4 4 5 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 7 8.1 Overview ................................................................... 7 8.2 Functional Block Diagram ......................................... 7 8.3 Feature Description................................................... 7 8.4 Device Functional Modes.......................................... 7 9 Applications and Implementation ........................ 8 9.1 Application Information.............................................. 8 9.2 Typical Application ................................................... 8 10 Layout................................................................... 10 10.1 Layout Guidelines ................................................. 10 10.2 Layout Example .................................................... 10 11 Device and Documentation Support ................. 12 11.1 Trademarks ........................................................... 12 11.2 Electrostatic Discharge Caution ............................ 12 11.3 Glossary ................................................................ 12 12 Mechanical, Packaging, and Orderable Information ........................................................... 12 5 Revision History Changes from Revision A (March 2014) to Revision B Page • Fixed Ultra Low Leakage Current typo................................................................................................................................... 1 • Updated ILEAK max value. ....................................................................................................................................................... 4 Changes from Original (July 2013) to Revision A • 2 Page Updated 1 page datasheet to full version............................................................................................................................... 1 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 TPD4E110 www.ti.com SLVSC54B – JULY 2013 – REVISED APRIL 2014 6 Terminal Configuration and Functions 4 Terminal DPW Package Bottom View 1 2 GND 3 4 Terminal Functions TERMINAL TYPE DESCRIPTION 1, 2, 3, 4 IO ESD-protected channel 5 G Ground NAME NO. IOX GND 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Operating temperature range MIN MAX UNIT -40 125 °C IPP Peak pulse current (tp = 8/20μs) 2.5 A PPP(forward) Peak pulse power (tp = 8/20μs) 35 W PPP(reverse) Peak pulse power (tp = 8/20μs) 18 W (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 Handling Ratings MIN MAX Tstg Storage temperature ESD (1) (1) –65 UNIT 155 °C IEC 61000-4-2 contact ESD ±12 kV IEC 61000-4-2 air-gap ESD ±15 kV Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX VIO TA Operating free-air temperature 5.5 V –40 125 °C Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 UNIT 0.0 3 TPD4E110 SLVSC54B – JULY 2013 – REVISED APRIL 2014 www.ti.com 7.4 Thermal Information TPD4E110 THERMAL METRIC (1) DPW (4 TERMINALS) RθJA Junction-to-ambient thermal resistance 291.8 RθJC(top) Junction-to-case (top) thermal resistance 224.2 RθJB Junction-to-board thermal resistance 245.8 ψJT Junction-to-top characterization parameter 31.4 ψJB Junction-to-board characterization parameter 245.6 RθJC(bot) Junction-to-case (bottom) thermal resistance 195.4 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics TA = 25°C (unless otherwise noted) PARAMETER VRWM Reverse stand-off voltage VCLAMP Clamp voltage with ESD strike TEST CONDITION MIN UNIT V I = 1A, TLP, I/O to GND 10 V I = 5A, TLP, I/O to GND 13 V I = 1A, TLP, GND to I/O 3 V I = 5A, TLP, GND to I/O 6 V Break-down voltage IIO = 1mA ILEAK Leakage current VIO = 2.5V RDYN Dynamic resistance CL Line capacitance VIO = 2.5V, f = 1MHz, I/O to GND CCROSS Channel to channel input capacitance GND Terminal = 0V, f = 1MHz, VBIAS = 2.5 V, between channel terminals ΔCIO-TO-GND Variation of channel input capacitance GND Terminal = 0V, f = 1MHz, VBIAS = 2.5 V, Channel_x terminal to GND – Channel_y terminal to GND 4 MAX 5.5 VBR (1) TYP IIO = 10 μA 6.5 7.5 8.5 V 0.02 1 nA Any I/O to GND Terminal (1) 0.8 Ω GND to any I/O Terminal (1) 0.7 Ω 0.45 0.55 pF 0.003 pF 0.05 pF Extraction of RDYN using least squares fit of TLP characteristics between I = 10A and I = 20A. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 TPD4E110 www.ti.com SLVSC54B – JULY 2013 – REVISED APRIL 2014 7.6 Typical Characteristics At TA = 25°C, unless otherwise noted 120 0 100 -20 Voltage (V) Voltage (V) 80 60 -40 -60 40 -80 20 0 -100 0 25 50 75 Time (ns) 100 125 150 0 25 50 D001 Figure 1. IEC 61000-4-2 Clamping Voltage, +8kV Contact 75 Time (ns) 100 125 150 D002 Figure 2. IEC 61000-4-2 Clamping Voltage, -8kV Contact 1 1E-3 8E-4 0 6E-4 4E-4 Current (A) Gain (dB) -1 -2 -3 2E-4 0 -2E-4 -4E-4 -4 -6E-4 -5 -6 100000 -8E-4 1000000 1E+7 1E+8 Frequency (Hz) 1E+9 -1E-3 -1 1E+10 0 1 2 D003 Figure 3. Insertion Loss 3 4 Voltage (V) 5 6 7 8 D009 Figure 4. IV Curve 6E-10 20 15 5E-10 5 Leakage (A) Current (A) 10 0 -5 4E-10 3E-10 2E-10 -10 1E-10 -15 -20 -30 -25 -20 -15 -10 -5 0 5 Voltage (V) 10 15 20 25 30 0 -40 -20 D004 Figure 5. TLP, tPW = 100 nS, tRISE = 10 nS 0 20 40 60 Temperature (ºC) 80 100 Product Folder Links: TPD4E110 D005 Figure 6. Leakage vs Temperature Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated 120 5 TPD4E110 SLVSC54B – JULY 2013 – REVISED APRIL 2014 www.ti.com Typical Characteristics (continued) 2.7 40 Current 36 Power 2.7 40 Current 36 Power 2.4 32 2.4 32 2.1 28 2.1 28 1.8 24 1.8 24 1.5 20 1.5 20 1.2 16 12 0.9 12 0.6 8 0.6 8 0.3 4 0.3 4 0 45 0 0 50 1.2 16 0.9 0 -5 0 5 10 15 20 25 Time (µs) 30 35 40 3 Power (W) Current (A) Current (A) 3 -5 0 5 10 15 20 25 Time (µs) 30 35 40 D006 45 Power (W) At TA = 25°C, unless otherwise noted D008 Figure 8. Surge Curves, GND to IO Figure 7. Surge Curves, IO to GND 0.8 Capacitance (pF) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 Voltage (V) 4 5 D007 Figure 9. IO Terminal Capacitance vs VBIAS 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 TPD4E110 www.ti.com SLVSC54B – JULY 2013 – REVISED APRIL 2014 8 Detailed Description 8.1 Overview TPD4E110DPW is a uni-directional ESD protection device with ultra-low capacitance. The device is constructed with a central ESD clamp that features two hiding diodes per channel to reduce the capacitive loading. Each channel is rated to dissipate ESD strikes above the maximum level specified in the IEC61000-4-2 level 4 international standard. The TPD4E110DPW's ultra-low loading capacitance makes the device ideal for protecting high-speed signal terminals. The 0.8 mm x 0.8 mm package is designed for space saving designs. The pinout allows for straight through routing of 2 differential pairs when PCB manufacturing which feature sizes of 2.8 mils (0.071 mm). 8.2 Functional Block Diagram IO1 IO3 IO2 IO4 8.3 Feature Description TPD4E110 is a uni-directional Electrostatic Discharge (ESD) protection device with ultra-low capacitance. The device is constructed with a central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. Each line is rated to dissipate ESD strikes above the maximum level specified in the IEC61000-4-2 level 4 international standard. The TPD4E110's ultra-low loading capacitance makes it ideal for protecting high-speed signal terminals. 8.4 Device Functional Modes TPD4E110 is a passive integrated circuit that activates whenever voltages above VBR or below the lower diodes Vforward (–0.6V) are present upon the circuit being protected. During ESD events, voltages as high as ±15 kV can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD4E110 (usually within 10’s of nano-seconds) the device reverts to passive. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 7 TPD4E110 SLVSC54B – JULY 2013 – REVISED APRIL 2014 www.ti.com 9 Applications and Implementation 9.1 Application Information TPD4E110 is a diode array type Transient Voltage Suppressor (TVS) which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a tolerable level to the protected IC. 9.2 Typical Application 1 2 System Connector Tx GND 3 4 Rx Figure 10. Protecting a Pair of Super-Speed Data Lines 9.2.1 Design Requirements For this design example, use the following as the input parameters. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Signal range on Pin 1, 2, 3, or 4 0V to 5.5V Operating Frequency 3.0 GHz 9.2.2 Detailed Design Procedure To begin the design process some parameters must be decided upon. The designer needs to know the following: • Signal range on all the protected lines • Operating frequency 9.2.2.1 Signal range on Terminal 1, 2, 3, or 4 TPD4E110 has 4 identical protection channels for signal lines. The symmetry of TPD4E110 provides flexibility when selecting which of the 4 IO channels will protect which signal lines. Any IO will support a signal range of 0V to 5.5V. 9.2.2.2 Operating Frequency The 0.45pF capacitance of each IO channel supports data rates up to 6Gbps. 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 TPD4E110 www.ti.com SLVSC54B – JULY 2013 – REVISED APRIL 2014 9.2.3 Application Curves Figure 11. Eye Diagram for USB 3.0 Super-Speed Data Lines Using Single Layer Routing with Device Installed Figure 12. Eye Diagram for USB 3.0 Super-Speed Data Lines Using Single Layer Routing without Device Installed Figure 13. Eye Diagram for USB 3.0 Super-Speed Data Lines Using Double Layer Routing with Device Installed Figure 14. Eye Diagram for USB 3.0 Super-Speed Data Lines Using Double Layer Routing with Device Installed Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 9 TPD4E110 SLVSC54B – JULY 2013 – REVISED APRIL 2014 www.ti.com 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example 10.2.1 Single Layer Routing PCB manufacturing technologies allowing 2.8 mil (0.071 mm) clearances can route two Super-Speed data line pairs through TPD4E110 on a single layer. 1 USB 3.0 Type A Connector PCB Footprint TPD4E110DPW SSTX+ VBUS SSTX- D- D+ SSRX+ SSRX- 2 Figure 15. Example Layout for USB 3.0 Type A connector using two TPD4E110s In Figure 15, Figure 16 and Figure 17 an example layout shows the use of two TPD4E110s to protect the USB 3.0 port. TPD4E110 Number 1 is protecting the two Super-Speed data pairs used for Super Speed data transfer, and TPD4E110 Number 2 protects the USB 2.0 D+/D– Hi-Speed data lines. Number 2 uses two channels to protect each line in the pair, thus affording a more robust protection and simpler layout. 10 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 TPD4E110 www.ti.com SLVSC54B – JULY 2013 – REVISED APRIL 2014 Layout Example (continued) Figure 16. Close-up of Routing for TPD4E110 for Super-Speed Data Lines Figure 17. Close-up of Routing for TPD4E110 for USB 2.0 D+/D– Hi-Speed Data Lines 10.2.2 Double Layer Routing PCB manufacturing technologies allowing 4.0 mil (0.1 mm) clearances can route two Super-Speed data line pairs through TPD4E110 using two layers. Figure 18. Example Layout for USB 3.0 Type A Connector Using Two TPD4E110s In Figure 18 an example layout shows the use of two TPD4E110s to protect the USB 3.0 port. TPD4E110 Number 1 is protecting the two Super-Speed data pairs used for high speed data transfer, and TPD4E110 Number 2 protects the USB 2.0 D+/D– Hi-Speed lines. Number 2 uses two channels to protect each line in the pair, thus affording a more robust protection and simpler layout. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 11 TPD4E110 SLVSC54B – JULY 2013 – REVISED APRIL 2014 www.ti.com 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPD4E110 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD4E110DPWR ACTIVE X2SON DPW 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 D2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of