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TPD4S1394
SLVSA55B – NOVEMBER 2009 – REVISED NOVEMBER 2016
TPD4S1394 Firewire ESD Clamp With Live-Insertion Detection Circuit
1 Features
•
•
1
•
•
•
IEEE 1394 Live Insertion Detection
ESD Protection Exceeds IEC61000-4-2 (Level 4)
– ±15-kV Human-Body Model (HBM)
– ±6-kV IEC 61000-4-2 Contact Discharge
4-Channel Matching ESD Clamps for High-Speed
Differential Lines
Flow-Through, Single-in-Line Pin Mapping
Simplifies Board Layout
Available in an 8-Pin X2SON (DQL) package
2 Applications
Firewire Interface
3 Description
The TPD4S1394 provides robust system level ESD
solution for the IEEE 1394 port, along with a live
insertion detection mechanism for high-speed lines
interfacing a low-voltage, ESD sensitive core chipset.
This device protects and monitors up to two
differential input pairs. The optimized line capacitance
protects the data lines with data rates in excess of
1.6 GHz without degrading signal integrity.
The TPD4S1394 incorporates a live insertion
detection circuit whose output state changes when
improper voltage levels are present on the input data
lines. The FWPWR_EN signal controls an external
FireWire port power switch. During the live insertion
event if there is a floating GND or a high level signal
at the D+ or D– pins, the internal comparator detects
the changes and pull the FWPWR_EN signal to a low
state. When FWPWR_EN is driven low, there is an
internal delay mechanism preventing it from being
driven to the high state regardless of the inputs to the
comparator.
Additionally, the TPD4S1394 performs ESD
protection on the four inputs pins: D1+, D1–, D2+,
and D2–. The TPD4S1394 conforms to the
IEC61000-4-2 (Level 4) ESD protection and ±15-kV
HBM ESD protection. The TPD4S1394 is
characterized for operation over ambient air
temperature of –40°C to 85°C.
A 0.1-µF decoupling capacitor is required at VCC.
Device Information(1)
PART NUMBER
TPD4S1394
PACKAGE
X2SON (8)
BODY SIZE (NOM)
2.00 mm × 1.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
D2+
D2 –
VCMLP
D1+
VCC
D1–
Reference
Generator
FWPWR_EN
VREF
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD4S1394
SLVSA55B – NOVEMBER 2009 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
3
4
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 6
7.1 Overview ................................................................... 6
7.2 Functional Block Diagram ......................................... 6
7.3 Feature Description................................................... 6
7.4 Device Functional Modes.......................................... 6
8
Application and Implementation .......................... 7
8.1 Application Information.............................................. 7
8.2 Typical Application .................................................... 7
9 Power Supply Recommendations........................ 8
10 Layout..................................................................... 8
10.1 Layout Guidelines ................................................... 8
10.2 Layout Example ...................................................... 9
11 Device and Documentation Support ................. 10
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
10
10
10
10
10
12 Mechanical, Packaging, and Orderable
Information ........................................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2013) to Revision B
Page
•
Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table,
Switching Characteristics table, Detailed Description section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
•
Added Thermal Information table ........................................................................................................................................... 4
Changes from Original (November 2009) to Revision A
•
2
Page
Removed hard coded ordering information table. Information contained in Package Orderable Addendum. ....................... 1
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SLVSA55B – NOVEMBER 2009 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
DQL Package
8-Pin X2SON
(Top View)
VCC
1
8
D1+
GND
2
7
D1–
3
6
D2+
4
5
D2–
VCMLP
FWPWR_EN
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
D1+
8
Input
High-speed ESD clamp input
D1–
7
Input
High-speed ESD clamp input
D2+
6
Input
High-speed ESD clamp input
D2–
5
Input
High-speed ESD clamp input
FWPWR_EN
4
Output
Control output
GND
2
Ground
Ground
VCC
1
Power
Power supply
VCLMP
3
Output
Comparator trip reference
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
4.6
V
0
4
V
Switch output
–0.5
4.6
V
TA
Operating free-air temperature
–40
85
°C
Tstg
Storage temperature
–65
150
°C
VCC
Supply voltage
VIO
IO voltage at D+, D–, VCLMP
FWPWR_EN
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
Electrostatic discharge
All pins except 5, 6, 7, and 8
±2500
Pins 5, 6, 7, and 8
±15000
Charged-device model (CDM), per JEDEC All pins except 5, 6, 7, and 8
specification JESD22-C101 (2)
Pins 5, 6, 7, and 8
±1000
IEC 61000-4-2 contact discharge
Pins 5, 6, 7, and 8 (interface side)
±6000
IEC 61000-4-2 air-gap discharge
Pins 5, 6, 7, and 8 (interface side)
±6000
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
MIN
MAX
3
3.6
Supply voltage
UNIT
V
6.4 Thermal Information
TPD4S1394
THERMAL METRIC (1)
DQL (X2SON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
167.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.8
°C/W
RθJB
Junction-to-board thermal resistance
82.3
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
82
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
High-to-low
2.9
3.4
4
Low-to-high
2.7
3.2
3.8
UNIT
VDX
FWPWR_EN trip voltage
(D+ and D– pins)
VCLMP
Value on pin
No connection
VBR
Breakdown voltage at VCLAMP
II = 1 mA
VD
Diode forward voltage for lower clamp
ID = 8 mA lower clamp diode
FWPWR_EN
Switch output
RDYN
Dynamic resistance (in and out clamp) of D+, D–
I=1A
CIO
I/O capacitance of D+, D–
VIO = 2.5 V
1.5
2
pF
ICC
Current consumption
VCC = 3.3 V, FWPWR_EN = high
130
200
µA
(1)
–0.6
V
2.45
V
4.2
V
–0.8
–0.95
V
VCC
V
1
Ω
A 0.1-µF decoupling capacitor is required at VCC.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tTRIP
Delay time for FWPWR_EN to go low
Loading on FWPWR_EN = 50 pF
0.5
2
5
µs
tRESET
Delay time for FWPWR_EN to go high after trip
FWPWR_EN = VCC
300
450
600
ms
4
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UNIT
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TPD4S1394
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SLVSA55B – NOVEMBER 2009 – REVISED NOVEMBER 2016
6.7 Typical Characteristics
2.5
0
-3
Insertion Loss (dB)
Capacitance (pF)
2.0
1.5
1.0
-6
-3.0 dB Frequency = 2.4 GHz
-9
-12
0.5
-15
0.0
0.0
0.5
1.0
1.5
2.0
Voltage Bias (V)
2.5
3.0
3.5
-18
1.0E+07
D+, D– Pins
Figure 1. I/O Capacitance vs I/O Voltage
1.0E+08
1.0E+09
Frequency (Hz)
D+, D– Pins
1.0E+10
Figure 2. Insertion Loss (S21)
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7 Detailed Description
7.1 Overview
TPD4S1394 is a FireWire interface part that complies to the IEEE 1394 standard. The device has ESD protection
for four high-speed data lines that pass 6-kV IEC61000-4-2 standard. Each dataline's I/O capacitance associated
with the ESD cell is minimal and supports high data rate. There is a live insertion detection circuit integrated in
TPD4S1394. During the live insertion event if there is a floating GND or a high-level signal at D+ or D–, the
FWPWR_EN is driven low, disabling the external FireWire power switch.
7.2 Functional Block Diagram
D2+
D2 –
VCMLP
D1+
VCC
D1–
Reference
Generator
FWPWR_EN
VREF
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
TPD4S1394's high-speed ESD cells on the data lines protect the pins from up to ±6-kV IEC 61000-4-2 contact
discharge. The live insertion protection circuit detects improper voltages on the data lines and turn off the
FireWire port power switch during an abnormal condition.
7.4 Device Functional Modes
The TPD4S1394's D1+, D1–, D2+, and D2– pins are a passive-integrated circuit that activates when voltages
exceed the forward voltage plus VCLMP or fall below the lower diodes forward voltage (–0.6 V). VCC must be
within recommended voltage range for live insertion detection circuit to work correctly.
6
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SLVSA55B – NOVEMBER 2009 – REVISED NOVEMBER 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
TPD4S1394 has both high-speed ESD cells to protect the D1+, D1–, D2+, and D2– lines and live insertion
detection circuit to identify improper status during insertion and to control the external power switch.
8.2 Typical Application
Firewire
Connector
Power
Power Switch
FWPWR_EN
TPB±
TPB+
TPB±_SYS
TPA±
TPB+_SYS
TPD1394
TPA+
TPA±_SYS
TPA+_SYS
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 3. Typical Application Schematic
8.2.1 Design Requirements
For this design example, a TPD4S1394 is used to protect the FireWire connector and detect live insertion.
Table 1 shows the design parameters:
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Power supply, VCC
3.3 V
Data line operating frequency
400 MHz (800 Mbps)
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8.2.2 Detailed Design Procedure
The data transfer rate of 800 Mbps is well below the bandwidth of the data pins of TPD4S1394. So the parasitics
associated with the ESD cells on these lines do not degrade the signal integrity. 3.3-V power supplies are
commonly available from the board and can be used to power the live insertion detection circuit.
8.2.3 Application Curves
2.5
0
-3
Insertion Loss (dB)
Capacitance (pF)
2.0
1.5
1.0
-6
-3.0 dB Frequency = 2.4 GHz
-9
-12
0.5
-15
0.0
0.0
0.5
1.0
1.5
2.0
Voltage Bias (V)
2.5
3.0
3.5
-18
1.0E+07
D+, D– Pins
1.0E+08
1.0E+09
Frequency (Hz)
1.0E+10
D+, D– Pins
Figure 4. I/O Capacitance vs I/O Voltage
Figure 5. Insertion Loss (S21)
9 Power Supply Recommendations
TI recommends a power supply for VCC is from 3 V to 3.6 V.
10 Layout
10.1 Layout Guidelines
•
•
•
8
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
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10.2 Layout Example
VCC
1
8
D1+
GND
2
7
D1–
VCLAMP
3
6
D2+
FWPWR_EN
4
5
D2–
Via to power ground plane
Via to power supply plane
Figure 6. TPD4S1394 Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD4S1394DQLR
ACTIVE
X2SON
DQL
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(5J7, 5JR)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
