TPD6F002QDSVRQ1

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPD6F002-Q1 SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 TPD6F002-Q1 Automotive ESD Protection and EMI Filter for LCD Displays and FPD-Link 1 Features 3 Description • • The TPD6F002-Q1 is a highly integrated device that provides a six channel Electromagnetic Interference (EMI) filter and a TVS based ESD protection diode array. The low-pass filter array suppresses EMI/RFI emissions for data ports subject to electromagnetic interference. The TVS diode array is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The high level of integration, combined with its small easy-to-route DSV package, allows this device to provide great circuit protection for LCD displays, memory interfaces, GPIO lines, and FPD-Link. 1 • • • • AEC-Q101 Qualified Six-Channel EMI Filtering for Data Ports – –47 dB Crosstalk Attenuation at 100 MHz – –30 dB Insertion Loss at 800 MHz – –3 dB Bandwidth 100 MHz Pi-Style (C-R-C) Filter Configuration (R = 100 Ω, CTOTAL = 34 pF) Robust ESD Protection Exceeds IEC 61000-4-2 (Level 4) – ±20-kV IEC 61000-4-2 Contact Discharge – ±30-kV IEC 61000-4-2 Air-Gap Discharge Low Leakage Current 20 nA (Max) Space-Saving SON Package (3 mm × 1.35 mm) PART NUMBER TPD6F002-Q1 PACKAGE SON (12) BODY SIZE (NOM) 3.00 mm × 1.35 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 2 Applications • • • • • Device Information(1) LCD Display Interface GPIO Memory Interface Data Lines at Flex Cable FPD-Link 4 Simplified Schematic 100 Ω Ch_In C1 = 17 pF Ch_Out C2 = 17 pF GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD6F002-Q1 SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 3 7.1 7.2 7.3 7.4 7.5 7.6 3 3 3 4 4 5 Absolute Maximum Ratings ..................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 6 8.1 Overview ................................................................... 6 8.2 Functional Block Diagram ......................................... 6 8.3 Feature Description................................................... 6 8.4 Device Functional Modes.......................................... 7 9 Application and Implementation .......................... 7 9.1 Application Information.............................................. 7 9.2 Typical Application ................................................... 8 10 Power Supply Recommendations ..................... 10 11 Layout................................................................... 10 11.1 Layout Guidelines ................................................. 10 11.2 Layout Example .................................................... 10 12 Device and Documentation Support ................. 11 12.1 Trademarks ........................................................... 11 12.2 Electrostatic Discharge Caution ............................ 11 12.3 Glossary ................................................................ 11 13 Mechanical, Packaging, and Orderable Information ........................................................... 11 5 Revision History Changes from Original (December 2014) to Revision A • 2 Page Initial release of full version datasheet. .................................................................................................................................. 1 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 TPD6F002-Q1 www.ti.com SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 6 Pin Configuration and Functions DSV PACKAGE (3.0 mm × 1.35 mm × 0.75 mm) Ch1_Out Ch2_In Ch2_Out Ch3_In Ch3_Out GND Ch1_In Ch4_In Ch4_Out Ch5_In Ch5_Out Ch6_In Ch6_Out Pin Functions PIN I/O DESCRIPTION 1, 2, 3, 4, 5, 6 IO ESD-protected channel, connected to corresponding ChX_Out 7, 8, 9, 10, 11, 12 IO ESD-protected channel, connected to corresponding ChX_In G G Ground NAME NO. ChX_In ChX_Out GND 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIO IO to GND 5.75 V TJ Junction temperature 125 °C Tstg Storage temperature range 150 °C (1) –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002, all pins (1) ±10 Charged device model (CDM), per AEC Q101-005, all pins ±1.5 IEC 61000-4-2 Contact Discharge ±20 IEC 61000-4-2 Air-Gap Discharge ±30 UNIT kV AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIO Input pin voltage TA Operating free-air temperature NOM MAX UNIT 0 5.5 V -40 125 °C Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 3 TPD6F002-Q1 SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 www.ti.com 7.4 Thermal Information TPD6F002-Q1 THERMAL METRIC (1) DSV UNIT 12 PINS RθJA Junction-to-ambient thermal resistance 120.7 RθJC(top) Junction-to-case (top) thermal resistance 104.4 RθJB Junction-to-board thermal resistance 78.5 ψJT Junction-to-top characterization parameter 13.0 ψJB Junction-to-board characterization parameter 77.7 RθJC(bot) Junction-to-case (bottom) thermal resistance 66.5 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics TA = –40°C to 125°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT 100 115 Ω 20 nA VBR DC breakdown voltage IIO = 10 μA R Resistance VIN = 3.3 V, IIn-to-out = 1mA C Capacitance (C1 or C2) VIO = 2.5 V 17 IIO Channel leakage current VIO = 3.3 V 1 fC Cut-off frequency ZSOURCE = 50 Ω, ZLOAD = 50 Ω (1) 4 6 85 V 100 pF MHz Typical values are at TA = 25°C. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 TPD6F002-Q1 www.ti.com SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 7.6 Typical Characteristics TA = 25°C unless otherwise noted 100 1E-5 8E-6 99 6E-6 Resistance (:) Current (A) 4E-6 2E-6 0 -2E-6 Temperature 25qC 85qC 125qC -40qC -4E-6 -6E-6 98 97 96 -8E-6 -1E-5 -1 0 1 2 3 4 Voltage (V) 5 6 95 -50 7 -25 0 25 50 Temperature (qC) D001 Figure 1. DC Voltage-Current Sweep across Input, Output Pins 75 100 125 D002 Figure 2. Series Resistance vs Temperature 0 28 -3 26 24 -9 Capacitance (pF) Insertion Loss (dB) -6 -12 -15 -18 -21 -24 22 20 18 16 -27 14 -30 -33 100000 12 1000000 1E+7 1E+8 Frequency (Hz) 1E+9 5E+9 0 Figure 3. Typical Insertion-loss Characteristics (DC Bias = 0 V, 50 Ω Environment) 2 3 4 Bias Voltage (V) 5 6 D004 Figure 4. Capacitance (C1 or C2) vs. Bias Voltage 5 60 Input Output 55 50 0 -5 45 -10 Voltage (V) 40 Voltage (V) 1 D003 35 30 25 20 -15 -20 -25 -30 15 -35 10 -40 5 -45 Input Output -50 0 0 50 100 Time (ns) 150 0 200 D006 Figure 5. +8-kV IEC Waveform 50 100 Time (ns) 150 200 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 D007 Figure 6. -8-kV IEC Waveform 5 TPD6F002-Q1 SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 www.ti.com 8 Detailed Description 8.1 Overview The TPD6F002-Q1 is a highly integrated device that provides a six channel EMI filter and a TVS based ESD protection diode array. The low-pass filter array suppresses EMI/RFI emissions for data ports subject to electromagnetic interference. The TPD6F002-Q1 is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The high level of integration, combined with its small easyto-route DSV package, makes this device ideal for protecting interfaces like LCD displays, memory interfaces, and FPD-Link. 8.2 Functional Block Diagram 100Ω Ch_In C1 =17pF Ch_Out C2=17pF GND 8.3 Feature Description The TPD6F002-Q1 is a highly integrated device that provides a six channel EMI filter and a TVS based ESD protection diode array. The low-pass filter array suppresses EMI/RFI emissions for data ports subject to electromagnetic interference. The TVS diode array is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The high level of integration, combined with its small easyto-route DSV package, allows this device to provide great circuit protection for LCD displays, memory interfaces, GPIO lines, and FPD-Link. 8.3.1 AEC-Q101 Qualified This device is qualified to AEC-Q101 standards. It passes HBM H3B (±8 kV) and CDM C5 (±1 kV) ESD ratings and is qualified to operate from –40°C to 125°C. 8.3.2 Six-Channel EMI Filtering This device provides six channels for EMI filtering of data lines with the following parameters: • • • –47 dB Crosstalk Attenuation at 100 MHz –30 dB Insertion Loss at 800 MHz –3 dB Bandwidth: 100 MHz 8.3.3 Pi-Style Filter Configuration This device has a pi-style filtering configuration composed of a series resistor and two capacitors in parallel with the I/O pins. The typical resistor value is 100 Ω and the typical capacitor values are 17 pF each. 8.3.4 Robust ESD Protection The ESD protection on all pins exceeds the IEC 61000-4-2 level 4 standard. Contact ESD is rated at ±20 kV and Air-gap ESD is rated at ±30 kV. 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 TPD6F002-Q1 www.ti.com SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 Feature Description (continued) 8.3.5 Low Leakage Current The I/O pins feature an ultra-low leakage current of 20-nA (max) with a bias of 3.3 V 8.3.6 Space-Saving SON Package The layout of this device makes it easy to add protection to existing layouts. The packages offer flow-through routing which requires minimal changes to existing layout for addition of these devices. Additionally, the device offers a small space-saving package that takes a minimal footprint on the board. 8.4 Device Functional Modes The TPD6F002-Q1 is a passive integrated circuit that passively filters EMI and triggers when voltages are above VBR or below the lower diode voltage (–0.6 V). During ESD events, voltages as high as ±30 kV (air) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels, the device reverts to passive. 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TPD6F002-Q1 is a highly integrated device that provides a six channel EMI filter and a TVS based ESD protection diode array. The low-pass filter array suppresses EMI/RFI emissions for data ports subject to electromagnetic interference. The TVS diode array is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The high level of integration, combined with its small easyto-route DSV package, allows this device to provide great circuit protection for LCD displays, memory interfaces, GPIO lines, and FPD-Link. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 7 TPD6F002-Q1 SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 www.ti.com 9.2 Typical Application TPD6F002-Q1 R0 1 12 R1 2 11 R2 3 10 R3 4 9 R4 5 8 R5 6 7 Display Panel Connector G0 1 12 G1 2 11 G2 3 10 G3 4 9 G4 5 8 G5 6 7 TPD6F002-Q1 Connector TPD6F002-Q1 GND GND B0 1 12 B1 2 11 B2 3 10 B3 4 9 B4 5 8 B5 6 7 GND Figure 7. Display Panel Schematic 8 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 TPD6F002-Q1 www.ti.com SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 Typical Application (continued) 9.2.1 Design Requirements For this design example, three TPD6F002-Q1 devices are being used in an 18-bit display panel application. This will provide a complete ESD and EMI protection solution for the display connector. Given the display panel application, the following parameters are known. DESIGN PARAMETER VALUE Signal range on all pins except GND 0 V to 5 V Operating Frequency 50 MHz 9.2.2 Detailed Design Procedure To begin the design process, some design parameters must be decided; the designer needs to know the following: • • • Signal range of all the protected lines Operating frequency Crosstalk response 9.2.2.1 Signal Range on All Protected Lines The TPD6F002-Q1 has 6 identical protection channels for signal lines. All I/O pins will support a signal range from 0 to 5.5 V. 9.2.2.2 Operating Frequency The TPD6F002-Q1 has a 100 MHz –3 dB bandwidth, which supports the operating frequency for this display. 9.2.2.3 Crosstalk Response The TPD6F002-Q1 has a –47 dB near-side crosstalk attenuation at 100 MHz, sufficient for this display. 9.2.3 Application Curves 0 -10 -20 Crosstalk (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 100000 1000000 1E+7 1E+8 Frequency (Hz) 1E+9 5E+9 D005 Figure 8. Near-Side Crosstalk Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 9 TPD6F002-Q1 SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 www.ti.com 10 Power Supply Recommendations This device is a passive EMI and ESD device so there is no need to power it. Care should be taken to not violate the recommended VIO specification (5.5 V) to ensure the device functions properly. 11 Layout 11.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 11.2 Layout Example This application is typical of an 18-bit RGB display panel layout. VIA to GND Plane B5 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R5 R4 R3 R2 R1 R0 6 5 4 3 2 1 6 5 4 3 2 1 6 5 4 3 2 1 11 12 GND GND GND 10 9 8 7 12 11 10 9 8 7 12 11 10 9 8 7 Figure 9. TPD6F002-Q1 Layout 10 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 TPD6F002-Q1 www.ti.com SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 12 Device and Documentation Support 12.1 Trademarks All trademarks are the property of their respective owners. 12.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPD6F002-Q1 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD6F002QDSVRQ1 ACTIVE SON DSV 12 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UNS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of