Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPD7S019
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
TPD7S019 7-Channel Integrated ESD Solution for VGA Port with Integrated Level-Shifter
and Matching Impedance
1 Features
3 Description
•
The TPD7S019 device is an integrated electrostatic
discharge (ESD) circuit protection solution for VGA
and DVI-I connectors. It integrates transient voltage
suppression (TVS) protection diodes for VIDEO, DDC
and SYNC signals and meets the IEC61000-4-2
standard for ±8-kV contact ESD protection. The TVS
diodes only add low capacitances to help signals run
at high-speed. It also provides level-shifting for the
DDC signals saving external level-shifters. Two
noninverting drivers on HSYNC and VSYNC convert
TTL input levels to CMOS output levels and each
buffer has a series termination resistor connected to
the SYNC_OUT pin, eliminating the external
termination resistors. Three supply lines control the
power rails of the VIDEO, DDC and SYNC channels
to facilitate interfacing with low voltage video
controller ICs in mixed supply-voltage environments.
The TPD7S019 comes with two package options. The
16-pin RSV is compact and space-saving. The 16-pin
DBQ package and pinout are optimized for easy
board layout.
1
•
•
•
•
•
•
7-Channel ESD Protection Includes ESD
Protection, Level-Shifting, Buffering and Sync
Impedance Matching
Exceeds IEC61000-4-2 (Level 4) ESD Protection
to Requirements on the External Pins
– ±8-kV IEC 61000-4-2 Contact Discharge
Very Low Loading Capacitance from ESD
Protection Diodes on VIDEO Lines (2.5 pF)
5-V Drivers for HSYNC and VSYNC Lines
Integrated Impedance Matching Resistors on
Sync Lines
Bidirectional Level-Shifting N-Channel FETs
Provided for DDC_CLK and DDC_DATA
Channels
Flow-Through Single-In-Line Pin Mapping Ensures
no Additional Board Layout Burden While Placing
the ESD Protection Chip Near the Connector
2 Applications
•
•
This ESD protection product is a good solution to
protect the VGA and DVI-I ports for desktop and
laptop PCs, set top boxes, TVs and monitors.
End Equipment:
– Desktop and Notebook PCs
– Set Top Boxes
– TVs
Interfaces:
– VGA
– DVI-I
Device Information(1)
PART NUMBER
PACKAGE
TPD7S019
BODY SIZE (NOM)
SSOP (16)
4.90 mm × 3.90 mm
UQFN (16)
2.60 mm × 1.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Schematic
3.3 V
5V
5V
5V
RP
0.1 µF
5V
RP
0.1 µF
VCC_DDC
BYP
VCC_VDEO
VCC_SYNC
0.1 µF
0.22 µF
VIDEO1
Red
VIDEO2
VIDEO3
Green
Blue
VGA Controller
RT
HSYNC
SYNC_IN2
SYNC_OUT2
SYNC_IN1
SYNC_OUT1
VSYNC
DDC_IN2
DDC_OUT2
DDC_CLK
DDC_OUT1
DDC_DAT
DDC_IN1
TPD7S019
VGA Connector
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD7S019
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 11
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support ................. 13
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2016) to Revision E
•
Updated Figure 6.................................................................................................................................................................. 10
Changes from Revision C (November 2015) to Revision D
•
2
Page
Removed PREVIEW status from the RSV package............................................................................................................... 3
Changes from Revision A (March 2012) to Revision B
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Original (August 2010) to Revision A
•
Page
Updated the Functional Block Diagram .................................................................................................................................. 8
Changes from Revision B (December 2012) to Revision C
•
Page
Page
Removed non released part descriptions from the datasheet................................................................................................ 1
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
TPD7S019
www.ti.com
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
5 Pin Configuration and Functions
VCC_VIDEO
VCC_SYNC
SYNC_OUT2
SYNC_IN2
RSV Package
16-Pin UQFN
Top View
16
15
14
13
DBQ Package
16-Pin SSOP
Top View
11
SYNC_IN1
VIDEO3
3
10
DDC_OUT2
GND
4
9
DDC_IN2
5
6
7
8
DDC_IN1
SYNC_OUT1
2
DDC_OUT1
12
VIDEO2
BYP
1
VCC_DDC
VIDEO1
Pin Functions
PIN
NAME
DBQ
RSV
BYP
8
6
DDC_IN1
10
8
DDC_IN2
11
9
DDC_OUT1
9
7
DDC_OUT2
12
10
TYPE
Power
DESCRIPTION
Bypass pin. Using a 0.2-µF bypass capacitor increases the ESD robustness of the
system
I
DDC signal input. Connects to the VGA controller side of one of the sync lines
O
DDC signal output. Connects to the video connector side of one of the sync lines
—
Ground
GND
6
4
SYNC_IN1
13
11
SYNC_IN2
15
13
SYNC_OUT1
14
12
SYNC_OUT2
16
14
VCC_DDC
7
5
Power
Isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates
VCC_SYNC
1
15
Power
Isolated supply input for the SYNC_1 and SYNC_2 level-shifters and their
associated ESD protection circuits
VCC_VIDEO
2
16
Power
Supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection
circuits
VIDEO1
3
1
VIDEO2
4
2
VIDEO3
5
3
I
Sync signal buffer input. Connects to the VGA controller side of one of the sync
lines
O
Sync signal buffer output. Connects to the video connector side of one of the sync
lines
ESD
High-speed ESD clamp input
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
3
TPD7S019
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
IO voltage
MIN
MAX
VCC_VIDEO
–0.5
6
VCC_DDC
–0.5
6
VCC_SYNC
–0.5
6
UNIT
V
VIO(VIDEO)
VIDEOx pins
–0.5
VCC_VIDEO
V
VI(SYNC)
SYNC pins
–0.5
VCC_SYNC
V
VI(DDC)
DDC_INx pins
–0.5
6
V
Output voltage
VO(DDC)
DDC_INx pins
–0.5
6
V
Input clamp current
IIK
SYNC_INx, DDC_INx,
VIDEOx
VI < 0
–50
Output clamp current
IOK
SYNC_OUTx, DDC_OUTx
VO < 0
–50
Input voltage
SYNC_OUTx
Continuous output current IO
Continuous current through supply pins
Storage temperature
(1)
mA
mA
–24
24
mA
DDC_INx to DDC_OUTx
–5
5
mA
VCC_VIDEO, VCC_SYNC, VCC_DDC
–50
50
mA
–55
125
°C
Tstg
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
TPD7S019 in RSV Package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Electrostatic discharge
All pins except 1, 2, 3, 4, 7, 10,
12, and 14
±2000
Pins 1, 2, 3, 7, 10, 12, and 14
±15000
Pin 4
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
IEC 61000-4-2 contact discharge
Pins 1, 2, 3, 7, 10, 12, and 14
±8000
All pins except 3, 4, 5, 6, 9, 12,
14, and 16
±2000
Pins 3, 4, 5, 9, 12, 14, and 16
±15000
Pin 6
±2000
V
TPD7S019 in DBQ Package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
4
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
IEC 61000-4-2 contact discharge
±8000
Pins 3, 4, 5, 9, 12, 14, and 16
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
TPD7S019
www.ti.com
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage
IO voltage
MIN
MAX
VCC_VIDEO
0
5.5
VCC_DDC
0
5.5
VCC_SYNC
0
5.5
UNIT
V
VIO(VIDEO)
VIDEOx pins
0
VCC_VIDEO
V
VI(SYNC)
SYNC pins
0
VCC_SYNC
V
VI(DDC)
DDC_INx pins
0
5.5
V
Output voltage
VO(DDC)
DDC_INx Pins
0
5.5
V
Operating temperature
TA
–40
85
°C
Input voltage
6.4 Thermal Information
TPD7S019
THERMAL METRIC (1)
DBQ (SSOP)
RSV (UQFN)
16 PINS
16 PINS
UNIT
115.8
124.5
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
67
52.7
°C/W
RθJB
Junction-to-board thermal resistance
58.3
53.8
°C/W
ψJT
Junction-to-top characterization parameter
19.9
1.4
°C/W
ψJB
Junction-to-board characterization parameter
57.9
53.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TYP
MAX
ICC_VIDEO
VCC_VIDEO supply current
PARAMETER
VCC_VIDEO = 5 V, VIDEO inputs at VCC_VIDEO or GND
1
10
µA
ICC_DDC
VCC_DDC supply current
VCC_DDC = 5 V
1
10
µA
1
50
ICC_SYNC
VCC_SYNC supply current
TEST CONDITIONS
VCC_SYNC = 5 V
MIN
SYNC inputs at GND or
VCC_SYNC,
SYNC outputs unloaded
UNIT
µA
SYNC inputs at 3 V;
SYNC outputs unloaded
2
mA
IIO_VIDEO
VIDEO input and output pins
VIO_VIDEO = 3 V
0.01
1
µA
IOFF
DDC pin power down leakage current
VCC_DDC ≤ 0.4 V, VDDC_OUT = 5 V
0.01
1
µA
VD
Diode forward voltage for lower clamp
of VIDEO, DDC, SYNC output pins
ID = 8 mA, lower clamp diode
–0.8
–0.95
V
RDYN_VIDEO
Dynamic resistance (VIDEO pins)
I=1A
VIH
High-level SYNC logic input voltage
VCC_SYNC = 5 V
VIL
Low-level SYNC logic input voltage
VCC_SYNC = 5 V
VOH
High-level SYNC logic output voltage
IOH = 0 mA, VCC_SYNC = 5 V
VOH
High-level SYNC logic output voltage
IOH = –24 mA, VCC_SYNC = 5 V
VOL
Low-level SYNC logic output voltage
IOL = 0 mA, VCC_SYNC = 5 V
0.15
V
VOL
Low-level SYNC logic output voltage
IOL = 24 mA, VCC_SYNC = 5 V
0.8
V
RT
SYNC driver output resistance
VCC_SYNC = 5 V, SYNC inputs at GND or 3 V
15
CIO_VIDEO
IO capacitance of VIDEO pins
VIO = 2.5 V, test frequency is 1 MHz
2.5
4
pF
tPLH
SYNC driver L => H propagation
delay
CL = 50 pF; VCC = 5 V, input tR and tF ≤ 5ns
12
tPHL
SYNC driver H => L propagation
delay
CL = 50 pF; VCC = 5 V, input tR and tF ≤ 5ns
12
tR, tF
SYNC driver output rise & fall times
CL = 50 pF; VCC = 5 V, input tR and tF ≤ 5ns
–0.6
1
Ω
2
V
0.6
4.85
V
2
V
Ω
4
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
V
ns
ns
ns
5
TPD7S019
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VBR
6
VIDEO ESD diode break-down
voltage
TEST CONDITIONS
IIO = 1 mA
Submit Documentation Feedback
MIN
9
TYP
MAX
UNIT
V
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
TPD7S019
www.ti.com
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
6.6 Typical Characteristics
Trf = 10 ns
Figure 2. TPD7S019-xx IEC Clamping Waveforms Positive
Contact
Figure 1. TPD7S019-xx TLP VID1 to GND, Barth
Figure 3. TPD7S019-xx IEC Clamping Waveforms Negative
Contact
VCC_VIDEO = 5 V
Figure 4. Leakage Current through VIDEO Pins
VCC_DDC = 0 V
Figure 5. IOFF (DDC_OUTx)
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
7
TPD7S019
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
7 Detailed Description
7.1 Overview
The TPD7S019 is an integrated protection solution for VGA or DVI-I ports by providing high-speed ESD
protection, level-shifting and signal buffering. The TVS protection diodes for VIDEO signals, DDC signals and
SYNC signals provide robust ESD clamping that meets the IEC61000-4-2 standard for ±8-kV contact stress. The
signals run at high speed is minimally affected by the low capacitance added to each signal line. The integrated
level-shifters for the DDC signals help save external ICs. Two buffers on the HSYNC and VSYNC signals convert
TTL input level to CMOS output level, and it saves external components by integrating series termination
resistors connected to the SYNC_OUT pin. The TPD7S019 takes in three signal rails to make the signals
compatible with different voltages on VIDEO, DDC and SYNC. The two package options provide the latitude to
choose between either small board area or easier layout and better signal integrity.
The end applications of this device include desktop and laptop PCs, set top boxes, TVs, and monitors.
7.2 Functional Block Diagram
VCC_VIDEO
VIDEO1
VIDEO2
VIDEO3
GND
VSYNC
BYP
VCC_DDC
DDC_IN1
DDC_IN2
DDC_OUT1
SYNC_IN1
RT
SYNC_OUT1
SYNC_IN2
RT
SYNC_OUT2
DDC_OUT2
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
The TPD7S019 is an integrated protection solution for VGA and DVI-I ports. It has the low capacitance ESD TVS
diodes for the VIDEO signals to ensure high speed data transmission. Level-shifting on the DDC lines translate
signals on the cable to the level can be processed by downstream ICs. Buffers on the SYNC lines condition the
signal levels and quality. The integrated termination resistors help reduce external devices. The TPD7S019
exceeds IEC61000-4-2 (Level 4) ESD standard of ±8-kV contact discharge, making the system robust against
system level ESD. The two package options provide the freedom to choose between a compact package or a
flow through package.
8
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
TPD7S019
www.ti.com
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
7.4 Device Functional Modes
DDC level translators and SYNC signal buffers are active and the ESD cells on all the lines are untriggered when
the recommended operating conditions are met. The bidirectional voltage-level translators provide noninverting
level-shifting from the system side to the connector side. Each connector side pin has an ESD clamp that triggers
when voltages are above VBR or below the lower diode's Vf. During ESD events, voltages as high as ±8-kV
(contact ESD) can be directed to ground through the internal diode network. Once the voltages on the protected
line fall below these trigger levels (usually within 10s of nano-seconds), these pins revert to a non-conductive
state.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
9
TPD7S019
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
When a system contains a human interface connector, it becomes vulnerable to large system-level ESD strikes
that standard ICs cannot survive. The TPD7S019 provides IEC61000-4-2 Level 4 Contact ESD rating to the VGA
or DVI-I port. The integrated voltage level-shifting, buffering and termination reduce the board space needed to
implement the control lines functions.
8.2 Typical Application
3.3 V
5V
5V
5V
RP
0.1 µF
5V
RP
0.1 µF
VCC_DDC
BYP
VCC_VDEO
VCC_SYNC
0.1 µF
0.22 µF
VIDEO1
Red
VIDEO2
Green
VIDEO3
Blue
VGA Controller
RT
SYNC_IN2
SYNC_OUT2
HSYNC
SYNC_IN1
SYNC_OUT1
VSYNC
DDC_IN2
DDC_OUT2
DDC_CLK
DDC_IN1
DDC_OUT1
DDC_DAT
TPD7S019
VGA Connector
Copyright © 2016, Texas Instruments Incorporated
Figure 6. Typical Application Schematic with TPD7S019
8.2.1 Design Requirements
In this application, the TPD7S019 is used to protect the VGA port. Table 1 lists the system parameters.
Table 1. Design Parameters
10
DESIGN PARAMETER
VALUE
Pull-up resistors on DDC lines
1.5 kΩ to 2 kΩ
Termination resistors on VIDEO lines
50 Ω to 75 Ω
VIDEO signals data rate
24 MHz to 388 MHz
Required IEC 61000-4-2 ESD Protection
±8-kV Contact
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
TPD7S019
www.ti.com
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
8.2.2 Detailed Design Procedure
To
•
•
•
begin the design process, some parameters must be decided upon; the designer must make sure:
Voltage range on the protected line must not exceed the reverse standoff voltage of the TVS diode(s) (VRWM)
Operating frequency is supported by the I/O capacitance CIO of the TVS diode
IEC 61000-4-2 protection requirement is covered by the IEC performance of the TVS diode
For this application, the DDC signals switch between 0 V and 5 V (with resistor pulling it up to 5-V power supply).
The VIDEO and SYNC signal levels are between 0 V and VCC_VIDEO / VCC_SYNC. All signals are not exceeding the
recommended values and the ESD cells on these pins stay untriggered.
Depending on the resolution and the refresh rate of the display, the VIDEO (RGB) signals' bandwidth can be
from 24 MHz to 388 MHz. The line capacitances from the ESD cells are 2.5 pF typical which is only takes up a
small portion of the total capacitance budget for the maximum frequency in this range.
±8-kV Contact ESD provided by the TPD7S019 meets the ESD design goal of ±8 kV contact.
Put 1.5-kΩ to 2-kΩ pullup resistor on the DDC lines to be compliant with the I2C standard. Termination resistors
on VIDEO lines are 50 Ω to 75 Ω to match the impedance on board trace.
8.2.3 Application Curves
Figure 7. IEC 61000-4-2 Clamping Voltage, Positive
Contact
Figure 8. IEC 61000-4-2 Clamping Voltage, Negative
Contact
9 Power Supply Recommendations
The TPD7S019 has three power supply pins: VCC_DDC, VCC_SYNC and VCC_VIDEO. Depending on the system, the
recommended voltage level of these three power supplies can be as high as 5.5 V.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
11
TPD7S019
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
10 Layout
10.1 Layout Guidelines
The optimum placement of this device is as close to the connector as possible. EMI during an ESD event can
couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.
Therefore, the PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected
traces away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Avoid using VIAs between the connecter and an I/O protection pin on the TPD7S019.
Avoid 90º turns in traces since electric fields tend to build up on corners, increasing EMI coupling.
Minimize impedance on the path to GND for maximum ESD dissipation.
The capacitors on VCC_VIDEO, VCC_DDC and VCC_SYNC must be placed close to their respective pins.
The VIDEO lines internal protection circuits are the same and thus these pins are interchangeable for routing.
10.2 Layout Example
Figure 9. Simplified Layout with TPD7S019 (Only IO Lines are Shown)
12
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
TPD7S019
www.ti.com
SLLSE33E – AUGUST 2010 – REVISED DECEMBER 2016
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Reading and Understanding an ESD Protection Datasheet
• ESD Layout Guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPD7S019
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD7S019-15DBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PQ19-15
TPD7S019-15RSVR
ACTIVE
UQFN
RSV
16
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
ZUS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
