TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
D
D
D
D
D
D
D
D
D
D
D
D
D
Precision Phase Lock Loop Motor – RPM
Control With Embedded DSP Filter
Algorithm for Loop Compensation
EEPROM Registers for User Adjustment of
PLL Loop Gain and DSP Filter Coefficients
(Pole/Zero)
Crystal Oscillator With EEPROM Adjustable
Divide-By for Versatile PLL Timebase
Standalone Operation With No Host
Processor Needed
RPM Lock Detection/Reporting
(±5% Window)
Synchronous Rectification,
Enabled (TPIC43T01)
Disabled (TPIC43T02)
Stalled Motor Timer/Shutdown
High-Side Current Limiting
High-Side Over-Current Shutdown
Differential Hall Effect Position Sensor
Inputs/Decode Provide Commutation
Control
Differential Variable Reluctance Speed
Sensor Inputs
Gate Drive for Six External N-Channel
Power FETs in Three Half-H Configuration
Charge Pump to Develop High-Side Gate
Drive Voltage
D
D
D
5 V Regulator – Designed for 10 mA
External Current
8 to 28 V Supply Voltage
Small Outline Surface-Mount Package
DA PACKAGE
(TOP VIEW)
IN2+
IN2–
IN3+
IN3–
FGOUT
FGIN–
FGIN+
CLT
CT
RT
OSC2
OSC1
VDD
FGSOUT
GND
LD
FSEL
S/S
F/R
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
IN1–
IN1+
TEST
VPP
PHA
UGA
LGA
UGB
PHB
LGB
LGC
UGC
PHC
SENSE
CP2
CP1
VCP
PGND
VCC
description
The TPIC43T01/02 is a monolithic motor control integrated circuit designed to provide RPM control to a 3-phase
brushless dc motor. The device provides two analog sensor input ports which include a speed sensor interface
and a Hall effect position interface. The speed feedback interface consists of an FG amplifier to receive an
external sinusoidal signal from a variable reluctance pickup and convert it to a digital speed signal for the control
circuit. When the motor speed is outside a ± 5% window of the reference signal, an out-of-lock condition is
declared. The Hall ffect sensor input section receives low-level differential voltages from external naked Hall
elements and converts them to digital position reference signals for the control circuit for commutation control.
The core of the control circuit implements a digital signal processing algorithm consisting of a digital integrator
and filter with user adjustable parameters to optimize the closed loop performance of the control system. The
device contains an internal EEPROM to set integrator gain and digital filter coefficients. In addition, Texas
Instruments provides a PC based Windows compatible software package to input the motor and system
characteristics and convert them to control parameters for the TPIC43T01/02. The software generates a JEDEC
compatible file to program the device through a third party device programmer.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Windows is a trademark of Microsoft Corporation.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
description (continued)
The TPIC43T01/02 provides pre-drive outputs to control six external N-channel FET switches connected in a
3-half H-bridge configuration to drive a 3-phase dc motor. A companion TI Power+ Arrays device is available,
the TPIC1310 3-half H-bridge power array, to provide up to 2.5 A motor drive capability. The TPIC1310 is a
monolithic gate protected DMOS power array available in the TI 15-pin PowerFLEX power package. The
TPIC43T01/02 gate drive outputs are designed to also drive discrete N-channel power FETs.
The TPIC43T01/02 provides onboard supervisory and shutdown logic to protect the device and motor from fault
conditions. Oscillators, charge pump, and voltage regulators have been integrated into the TPIC43T01/02 to
minimize the number of external discrete components required to support the motor system.
Power+ Arrays and PowerFLEX are trademarks of Texas Instruments Incorporated.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1k
CT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RT = 12.5 k
5.8 MHz
OSC
Freq Adj REG
FS
OSC
FG Ref
OSC
EEPROM
Program
and Test
Logic
FGS Bias
+
–
330 k
FGSOUT
GND
F1
F0
VDD
1 µF
5V
VReg
÷
Gain Select
Register
Watchdog
Timer
FS
FILTCLK
LD
Lock
Detect
FG Divide
Register 1
Speed
Discrimination
FGS
OUT
OSC_INT
FG
Frequency
Select
÷2
VIN
FGOUT
Digital
Integrator
8
10
VDD
UVLO
8–Bit PWM
Generator
k2:3–Bit REG
Digital
Filter
k1:6–Bit REG
A0
A1
A2
Lock
Counter
Lock
OSC
CLT
CLT = 0.1 µF
F/R
F/R
F/R
S/S
ILIM
Charge
Pump
CP2
PGND
Gate Drive
Control and
Commutation
Logic
Current
Limit
PWM
Sync
Rect
Coast
S/S
S/S
VDDUV S/S
CP1
181 kHz
OCSD
Shutdown
Logic
CPUV
CP
UVLO
÷ 32
OSC_INT
VCC
CP = 0.01 µF
–
+
–
+
–
+
Pre-FET
Drivers
VCP
Power
Array
IC
Analog Hall-Effect
Position Sensors
IN3–
IN2–
IN3+
IN1–
IN2+
IN1+
LGC
PHC
UGC
LGB
PHB
UGB
LGA
PHA
UGA
SENSE
Rsense
0.2
CS = 0.1–0.5 µF
Vm
Motor
3-Phase
0.1 µF
CM = 22 µF
1.5 k
typical application
CT = 0.02 µF
RT
Cosc = 30 pF
OSC2
Cosc = 30 pF
OSC1
TEST
VPP
FSEL
FGIN+
FGIN–
Speed
Pickup
0.01 µF
FG
1 µF
150 pF
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
3
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
Terminal Functions
TERMINAL
NAME
4
DESCRIPTION
NO.
I/O
CLT
8
I
Capacitor lock timer. CLT is a timing capacitor for the lock detect timer oscillator.
CP1
23
O
Charge pump. CP1 is the switched capacitor output number 1.
CP2
24
O
Charge pump. CP2 is the switched capacitor output number 2.
CT
9
I
Timing capacitor. CT is the timing capacitor for the filter oscillator.
F/R
19
I
Forward/Reverse. F/R is the forward/reverse direction data input.
FGIN –
6
I
FGIN – is a inverting amplifier input.
FGIN+
7
O
FGIN+ is a noninverting amplifier input.
FGOUT
5
O
FGOUT is a amplifier output.
FGSOUT
14
O
FGSOUT is a buffered FGS comparator output.
FSEL
17
I
Frequency select. FSEL is a frequency select input.
GND
15
IN1 –
38
I
Hall amplifier 1 inverting input
IN1+
37
I
Hall amplifier 1 noninverting input
IN2 –
2
I
Hall amplifier 2 inverting input
IN2+
1
I
Hall amplifier 2 noninverting input
IN3 –
4
I
Hall amplifier 3 inverting input
Ground
IN3+
3
I
Hall amplifier 3 non-inverting input
LD
16
O
Lock Detect. LD is an active low, open-drain output.
LGA
32
I
Lower gate drive A
LGB
29
I
Lower gate drive B
LGC
28
I
Lower gate drive C
OSC1
12
I
Crystal oscillator input 1. OSC1 is an external OSC input.
OSC2
11
I
Crystal oscillator input 2. OSC2 is an external OSC input.
PGND
21
PHA
34
I
Phase A return
PHB
30
I
Phase B return
PHC
26
I
Phase C return
RT
10
O
RT is the charge/discharge current setting resistor for filter and lock timer oscillators.
S/S
18
I
Stop/Start. S/S = low to start.
SENSE
25
I
Current limit sense. SENSE is the high-side current limit sense input.
TEST
36
I
Test enable
UGA
33
I
Upper gate drive A
UGB
31
I
Upper gate drive B
UGC
27
I
Upper gate drive C
VCC
VCP
20
I
Supply voltage
22
O
Charge-pump voltage source. VCP requires a storage capacitor.
VDD
VPP
13
O
5 V Supply output
35
I
EEPROM programming voltage input
PGND is the lower gate drive turnoff circuitry GND return.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
absolute maximum ratings over the recommended operating case temperature range (unless
otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V to 30 V
Motor drive voltage, V(motor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Charge pump output voltage, VCP(max), (VCP – VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 20 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C
Thermal resistance, junction to ambient, RθJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The device will function, but may not meet all electrical specifications over this voltage range.
recommended operating conditions
Supply voltage, VCC
MIN
TYP
MAX
18
24
28
UNIT
V
Extended supply voltage range, (see Note 1)
8
18
V
Operating case temperature, TC
0
70
°C
NOTE 1: The device will function, but may not meet all electrical specifications over this voltage range.
EEPROM programming
MIN
TYP
MAX
UNIT
VPP setup time, tsu(VPP)
VPP pulse width duration, tw(VPP)
See Figure 20
2
µs
See Figure 20
5
ms
VPP rise time, tr(VPP)
VPP fall time, tf(VPP)
See Figure 20
2
3
ms
See Figure 20
2
3
ms
electrical characteristics, TC = 25°C, VCC = 24V (unless otherwise noted)
PARAMETER
Iccq
TEST CONDITIONS
VDD quiescent current
TYP
MAX
S/S low, VCC = 28 V, I(VCP) = 2 mA
MIN
10
18
S/S high, VCC = 28 V, I(VCP) = 0 mA
5
10
MIN
TYP
MAX
2.5
3.1
4
UNIT
mA
VDD undervoltage lockout
PARAMETER
VDD(uvlo)
Vhys
TEST CONDITIONS
VDD under-voltage lockout threshold voltage
VDD under-voltage lockout threshold voltage
hysteresis
1.1
UNIT
V
V
5 V regulator
PARAMETER
TEST CONDITIONS
VDD
V(REGIN)
Output voltage
Line regulation
IO = –10 mA
VCC = 8 V to 28 V
V(REGOUT)
Load regulation
IO = 0 to –10 mA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
MAX
4.75
5
5.25
UNIT
0
50
mV
20
100
mV
V
5
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
electrical characteristics, TC = 25°C, VCC = 24V (unless otherwise noted) (continued)
charge pump
PARAMETER
VO(CP)
TEST CONDITIONS
IO = –1.5 mA, VCC = 18 V to 28 V,
CP = 0.01 µF, CS = 0.1 µF,
S/S = high
Output voltage
MIN
TYP
MAX
UNIT
VCC + 14
VCC + 15
VCC + 17
V
IO = –1.5 mA, VCC = 8 V,
CP = 0.01 µF, CS = 0.1 µF,
S/S = high
V(CP–uvlo)
Under voltage lockout
IO = –1.5 mA, VCC = 8 V to 28 V,
S/S = high (VCP forced externally)
Vhys(CP)
Under voltage lockout hysteresis
IO = –1.5 mA, VCC = 8 V to 28 V,
S/S = high (VCP forced externally)
VCC + 5.5
VCC + 5
VCC + 6
V
VCC + 7
0.6
V
V
FG signal conditioning
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIO(FG)
IIB(FG)
Amplifier input offset voltage
Measured at FGOUT
0.5
±7
mV
Amplifier input bias current
Measured at FGIN –
0.02
±1
µA
VOH(FG)
Amplifier high level output voltage
I(FG) = – 200 µA,
IDD = 0
VOL(FG)
AV
Amplifier low level output voltage
I(FG) = 200 µA, IDD = 0
V(FGsens)
V(FGbias)
FG input sensitivity (see Note 2)
100 x Gain, at 2 kHz,
FG bias voltage
VIT+(FGOUT)
FG comparator positive threshold
IFG = 0 µA, IDD = 0
FGOUT with respect to
V(FGIN+), See Figure 8
VIO(FGOUT)
FG comparator offset voltage
VOL(FGSOUT)
Ilkg(FGSOUT)
FGSOUT open drain saturation voltage
FGOUT with respect to
V(FGIN+), See Figure 8
IO = 2 mA
FGSOUT leakage current
VO = 5 V
VDD – 500 mV
VDD – 350 mV
100
Amplifier open-loop gain (see Note 2)
V
500
mV
45
dB
3
mV
2.375
2.5
2.625
V
215
250
285
mV
0.8
±7
mV
0.4
0.7
V
0.08
10
µA
NOTE 2: Design target only. Not tested in production.
Hall sensor signal conditioning
PARAMETER
IIB(HL)
VICR(HL)
TEST CONDITIONS
MIN
TYP
Input bias current (see Note 2)
Common-mode input voltage range (see Note 3)
1.5
VIT+(HL)
Input positive threshold voltage
With respect to V(CM), 1.5 kΩ in series
with both inputs, See Figure 9
VIT–(HL)
Input negative threshold voltage
MAX
UNIT
±4
µA
3.5
V
4
8
12
mV
With respect to VCM, 1.5 kΩ in series
with both inputs, See Figure 9
–4
–8
– 12
mV
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOTES: 2. Design target only. Not tested in production.
3. Not measured, forced during testing.
FG reference crystal oscillator
PARAMETER
VIT+(OSC1)
OSC1 input upper threshold (see Note 3)
VIT–(OSC1)
OSC1 input lower threshold (see Note 3)
2.7
1
NOTES: 3. Not measured, forced during testing.
6
POST OFFICE BOX 655303
V
• DALLAS, TEXAS 75265
V
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
electrical characteristics, TC = 25°C, VCC = 24V (unless otherwise noted) (continued)
digital filter f(s) RC oscillator
PARAMETER
TEST CONDITIONS
I(RT) = –160 µA
MIN
0.19 VDD
TYP
MAX
UNIT
V
RT reference voltage
VIT+(CT)
CT upper threshold voltage
0.7 VDD
V
VIT–(CT)
CT lower threshold voltage
0.3 VDD
V
V(CT)
CT amplitude
I(CT)
CT charge/discharge current
Measured at VIT+(CT) and VIT–(CT)
0.2 VDD
0.21 VDD
Vref(RT)
1.9
2
2.1
V
1.8 I(RT)
± 2 I(RT)
2.2 I(RT)
A
TYP
MAX
UNIT
lock detection timer
PARAMETER
VIT+(CLT)
CLT upper threshold voltage
VIT–(CLT)
CLT lower threshold voltage
V(CLT)
CLT amplitude
I(CLT)
CLT charge/discharge current
TEST CONDITIONS
MIN
0.7 VDD
V
0.3 VDD
Measured at VIT + (CLT) and VIT–(CLT)
V
1.9
2
2.1
V
1.9 I(RT)
± 2 I(RT)
2.3 I(RT)
A
high side gate drive
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
14
16
19
V
1
1.2
V
Clamp voltage
UGX to PHX, I(UGX) = –100 µA
VDS(UGX)
Source voltage drop
I(UGX) =–10 mA,
Measure VCP – V(UGX),
Vsink(UGX)
Sink voltage drop @10 mA
I(UGX)=10 mA,
V(PHx)= 0,
Measure V(UGX) – V(PHx) , VCC = 18 V
1.8
2
V
Vsink(UGX)
Sink voltage drop @100 uA
I(UGX)=10 mA,
V(PHx) = 0,
Measure V(UGX) – V(PHx) , VCC = 18 V
0.56
0.7
V
MIN
TYP
MAX
VC
VCP = VCC + 17 V,
VCC = 18 V
low side gate drive
PARAMETER
VO(REG15)
High level output voltage
Vsource(LGX)
Source voltage
VDS(LGX)
Sink voltage drop
TEST CONDITIONS
VCC = 18 to 28 V,
VCC = 8 to 18 V,
I(LGX) = 0
I(LGX) = 0
I(LGX) = –10 mA, with respect to PGND,
VCC = 18 V
UNIT
14
16
19
V
7.9
8
18
V
12
14.5
I(LGX) = 10 mA, with respect to PGND,
VCC = 18 V
V
0.6
1
V
MIN
TYP
MAX
UNIT
0.46
0.5
0.54
V
MIN
TYP
MAX
UNIT
0.9
1
1.1
MIN
TYP
MAX
12
13
15
V
15
23
35
kΩ
current limit control
PARAMETER
VIT(lim)
Limit threshold voltage
TEST CONDITIONS
VCC – V(SENSE)
over-current shutdown control
PARAMETER
VIT(ocsd)
Detection threshold voltage
TEST CONDITIONS
VCC – V(SENSE)
V
EEPROM programming
PARAMETER
VPP
R(VPP)
VPP programming voltage
VPP pulldown resistance
TEST CONDITIONS
VPP = 1 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
7
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
electrical characteristics, TC = 25°C, VCC = 24V (unless otherwise noted) (continued)
digital input pins
PARAMETER
TEST CONDITIONS
MIN
VIH
VIL
Digital input high level input voltage
Interface from 3.3 V controller
Digital input low level input voltage
Interface from 3.3 V controller
I(pullup)
Digital input pullup current, S/S, FSEL
VIN = 2.2 V
–9
I(F/R)
Digital input pulldown current, F/R
VIN = 1.1 V
17.5
I(TEST)
TEST input pulldown current
VIN = 1.1 V
TYP
MAX
2.2
UNIT
V
1.1
V
– 14
– 18
µA
27
35
µA
130
200
250
µA
MIN
TYP
MAX
UNIT
switching characteristics, TC = 25°C, VCC = 24 V
charge pump
PARAMETER
f(CP)
TEST CONDITIONS
180
Switching frequency
TC = 0 to 70°C
140
kHz
220
kHz
MAX
UNIT
FG signal conditioning
PARAMETER
BW
TEST CONDITIONS
MIN
Gain bandwidth (see Note 2)
TYP
200
kHz
NOTE 2. Design target only. Not tested in production.
FG reference crystal oscillator
PARAMETER
TEST CONDITIONS
f(OSC)
Crystal frequency range (see Note 2)
f(OSC1)
OSC1 frequency range
MIN
TYP
MAX
UNIT
5
6.87
10
MHz
10
MHz
MAX
UNIT
OSC1 driven externally, see FG Reference
Oscillator section
1
NOTE 2. Design target only. Not tested in production.
PWM control
PARAMETER
f(PWM)
PWM frequency
t(DT)
Gate drive dead time control
TEST CONDITIONS
MIN
TYP
22.7
TC = 0 to 70°C
See Figure 3
18
27
1
3.2
kHz
µs
digital filter f(s) RC oscillator
PARAMETER
f(CT)
TEST CONDITIONS
MIN
TYP
MAX
1/(2 × RT × CT) ±10%
Oscillator frequency (see Note 2)
UNIT
Hz
NOTE 2. Design target only. Not tested in production.
lock detection timer
PARAMETER
f(CLT)
TEST CONDITIONS
MIN
TYP
MAX
1/(2 × RT × CLT) ±10%
CLT oscillator frequency (see Note 2)
UNIT
Hz
NOTE 2. Design target only. Not tested in production.
lock detection
PARAMETER
TEST CONDITIONS
TYP
±5
LDERR†
Lock detect threshold
† Non JEDEC symbol.
8
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
%
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
switching characteristics, TC = 25°C, VCC = 24 V (continued)
current limit control
PARAMETER
t(DG)
Deglitch blanking time
TEST CONDITIONS
MIN
TYP
MAX
V(SENSE) – VL ≥ 100 mV, See Figure 1
0.5
3.7
6.5
TEST CONDITIONS
MIN
TYP
MAX
0.5
1.5
2.5
UNIT
µs
over-current shutdown control
PARAMETER
t(OCSD)
Response time
See Figure 2
UNIT
µs
Amplitude
VCC
V(SENSE)
VL
PWM
Cycle
High-Side Gate
Output
t(DG)
time
Figure 1. Current Limit Deglitch Blanking Time
Amplitude
V(SENSE)
VCC
VOCSD
High-Side Gate
Output
t(OCSD)
time
Figure 2. Over-Current Shutdown Response Time
Amplitude
UGx
t(DT)
t(DT)
LGx
time
Figure 3. Gate Drive Deadtime
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• DALLAS, TEXAS 75265
9
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
voltage regulator
The TPIC43T01/02 receives an 8 to 28 V supply voltage at the VCC pin and generates an internal 5 V, VDD,
supply for the internal analog and digital logic. An external terminal for VDD is provided for a required external
1 µF compensation capacitor. The regulator can also supply up to 10 mA current from the VDD pin to external
circuitry.
oscillators
internal oscillator
The device generates an internal 5.8 MHz clock to supply a frequency input to internal control blocks as
presented in Figure 4. No external components are required.
5.8 MHz
Oscillator
÷ 32
181 kHz
Charge
Pump
ILIM/OCSD
Deglitch
Timer
PWM, f∼23 kHz
8-Bit PWM
Generator
∼ 45 kHz
Watchdog
Gate Drive
Dead Time
Control
÷8
Integrator
Figure 4. 5.8 MHz Internal Oscillator Fanout
FG reference oscillator
The FG reference oscillator provides a clock to the FG frequency control section of the device. The oscillator
requires an external 5 to 10 MHz crystal to select the primary frequency. The user can alternatively input a 1
to 10 MHz signal from a signal generator to the OSC1 input to replace the external crystal. Two EEPROM bits
allow programming four different crystal oscillator divide-by values for controlling the FG reference frequency.
The FSEL pin provides an additional divide-by-2 for on-the-fly FG frequency (RPM) selection. Table 1 shows
the divide-by count and resulting FG reference frequency based on the two EEPROM bits (address 1, bits 0 –1)
and the FSEL pin input level.
10
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
Table 1. FG Reference Frequency
FG f(ref) @f(osc)
EEPROM
ADDR 1, BIT 1
EEPROM
ADDR 1, BIT 0
FSEL
INPUT
PRE-DIVIDER
DIVIDE BY
TOTAL f(osc)
DIVIDE-BY
1 MHZ
5 MHZ
10 MHZ
0
0
1
3
3072
326
1628
3256
0
0
0
6
6144
163
814
1628
0
1
1
4
4096
244
1221
2441
0
1
0
8
8192
122
610
1221
1
0
1
6
6144
163
814
1628
1
0
0
12
12,288
81
407
814
1
1
1
8
8192†
122
610
1221
16
16,384†
61
305
610
1
1
0
† Equals default value
sampling frequency for the digital filter, f(s), oscillator
An external resistor (RT) and capacitor (CT) must be connected from the respective RT and CT terminals to
GND to set the sampling frequency for the digital filter. Charge/discharge current at terminal CT will nominally
be ± 2 × (1V/RT). Nominal period is determined by the formula: T(CT) = 2 × RT × CT (see Figure 5).
VDD
1:1
1:2
I(RT)
2I(RT)
I(RT)
VDD
1 V Internal
Reference
1.5
+
_
+
_
R
Q
IRT
V(RT) = 1 V
RT
CT
4I(RT)
3.5
+
_
S
Clock To
Digital Filter
4:1
RT
CT
Figure 5. Digital Filter Sampling Clock Generation
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11
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
lock timer oscillator/counter
Overall lock timer functionality is implemented by the combination of the oscillator and counter. The lock timer
oscillator is identical to the sampling frequency oscillator. The external resistor (RT) is used as the current
setting reference for both blocks. An external capacitor must be connected from the CLT terminal to GND to
set the period, T(CLT), of the lock timer oscillator. The nominal period is determined by the formula:
TCLT = 2 × RT × CLT. When an out-of-lock signal is generated by the lock detect block (see lock detect section),
the lock timer counter will count at the frequency of the lock timer oscillator. Should the out-of-lock signal remain
for the duration of the counter completing 1023 counts, a lock timer time-out signal will then be generated which
the shutdown logic block will respond to (see shutdown section). The lock timer time-out is thus set by
TCLT × 1023.
power-up clear
An under-voltage lockout and power-up clear are provided to ensure FET drive outputs are set to a known state
during power-up. The device is held in a CLEAR state until the following three conditions are met:
1. VDD > VDD(uvlo), after which a power-up clear (PUC) time will begin.
2. The PUC timer counts 3 cycles of internal 20 kHz signal (internal 5.8 MHz ÷ 255), or ≅ 132 µs.
3. The charge pump voltage, V(CP), has charged to at least VCC + 5 V.
shutdown
The scheme for shutdown includes monitoring two conditions and latching the device in a CLEAR state should
an abnormal condition occur. Once shutdown is latched, the S/S input must be cycled high then low, or power
cycled OFF then ON to release shutdown and resume normal operation. If an abnormal condition still exists after
the S/S pin has been cycled, the device will relatch shutdown. A 1 on either S/S or VDD pins will clear the lock
timer. A VDD under-voltage-lockout detect will force a global clear. (see Table 2 and Figure 6).
Table 2. Shutdown Conditions
LATCHED SHUTDOWN
CONDITIONS
UNLATCHED SHUTDOWN CONDITIONS
S/S
INTERNAL
CLR
LT
LTCLR
GATE
OUTPUTS
OCSD
LT
CP UV
X
X
VDD UVLO
X
INPUT
X
H
0
0
0
X
X
X
VDD < VDD(uvlo)
X
0
0
0
V(SENSE) < V(OCSD)
Out of
Lock < t(LT)
VO(CP) > V(CPUV)
VDD > VDD(uvlo) + 3 counts
H↓L
1
1
1
X
X
VCP < V(CPUV)
for > t(DG)
X
X
X
X
0
V(SENSE) > V(OCSD)
for > t(DG)
X
X
X
X
X
X
0
X
Out of
Lock > t(LT)
X
X
L
X
1
0
12
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
S/S
ENA
CLR
PUC
VDD
UVLO
3 Counts
PWM
(22 KHz)
Internal
5.8 MHz
OSC
Charge Pump
UV
÷ 32
t(DG)
VDD
CPUV
D
Q
CLR
OSC
Lock
OSC
Lock
Counter
LTCLR
Lock
Detect
Q
ILIM
OCSD
t(DG)
OCSD
Shutdown
Latch
ENA
LT
ENA
Figure 6. Shutdown Logic Block Diagram
FG amplifier
The FG amplifier amplifies the ac signal from the FG variable-reluctance pickup and converts it to a digital signal
for internal use in the FG frequency control loop (see Figure 7). Figure 8 illustrates the generation of the
FGSOUT signal in the FG amplifier section. Two comparators driving an RS latch are used with the upper
comparator threshold (taken from the 5 V VDD band-gap buffer circuit feedback resistor string), while the lower
comparator threshold is connected to the FG bias voltage. This provides controlled hysteresis above the FGIN+
amplifier input reference voltage and zero-crossing detection at the input reference voltage.
FGSOUT
FG
Comparator
_
FGS Buffer
FGOUT
330 kΩ
150 pF
+
R
_
S
Q
+
FGIN–
+
1 kΩ
Band-Gap
Buffer
_
FG Amp
1 µF
1/2 VDD
+ 180 mV
FG
Winding
OP-Amp
FGIN+
+
_
1/2 VDD
Figure 7. FG Signal Conditioning Schematic
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
VIT+(FGOUT)
FGOUT
V(FGIN+)
VIO+(FGOUT)
FGSOUT
Figure 8. FG Signal Conditioning Block Waveforms
lock detect
The lock detect circuit monitors FGSOUT and flags when it is within ±5% of f(ref). The circuit counts the number
of FG reference clocks which occur between the rising edges of FGSOUT to determine whether motor speed
has reached the locking range. When a lock occurs, the LD terminal transitions low. When the FGSOUT
frequency is not within the ± 5% of f(ref) window, an internal out-of-lock signal is generated for the lock timer block
(see lock timer section).
Hall signal conditioning
The Hall signal conditioning block receives the low-level differential voltage from naked Hall elements and
implements symmetric threshold detection and hysteresis for noise rejection. The circuit has nominal input
voltage thresholds of ±7 mV at the INx+ pin with respect to the INx– pin. The common-mode input voltage range
is 1.5 V to 3.5 V (see Figure 9).
V(Hall)
(INx+)
VIT+(HL)
V(CM)
(INx–)
VIT–(HL)
Hall Amp
Output
(Internal)
Figure 9. Hall Signal Conditioning Waveforms
14
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
rotor position sensing/commutation control
To electronically commutate the three phases, the state of the three Hall-effect sensors is decoded to drive the
correct phases based on desired motor rotational direction and rotor position. This is accomplished by decoding
the Hall sensor gray-code with the F/R input condition as described in Table 3. If all three Hall inputs are detected
as identical states, this is an illegal condition and the device turns all outputs OFF.
Table 3. Hall Position Sensor Input Gray-Code Logic
COMMUTATION
F/R = LOW
F/R = HIGH
PHASE A
STEP
IN1
IN2
IN3
IN1
IN2
IN3
A
L
L
H
H
H
L
UPPER
LOWER
B
L
H
H
H
L
L
PWM
Note 4
C
L
H
L
H
L
H
PWM
Note 4
D
H
H
L
L
L
H
E
H
L
L
L
H
H
ON
F
H
L
H
L
H
L
ON
PHASE B
UPPER
LOWER
PWM
Note 4
PHASE C
UPPER
LOWER
ON
ON
ON
ON
PWM
PWM
Note 4
PWM
Note 4
Note 4
Illegal
L
L
L
L
L
L
all OFF
Illegal
H
H
H
H
H
H
all OFF
NOTE 4: For the Half-H in which GUx is being switched by PWM, the complimentary LGx can be EEPROM programmed by a single bit to enable
or disable synchronous rectification during t(OFF) of each PWM cycle. This allows configuration of the device for applications where
synchronous rectification can or cannot be used.
digital PWM operation
In Table 3, the term PWM represents the pulse-width-modulation duty-cycle. PWM switching is implemented
with the upper gate drive such that recirculation occurs in the lower external FET during the OFF portion of each
period. Coast mode is enabled or disabled using EEPROM address 0, bit 4. Synchronous rectification mode
is enabled or disabled using EEPROM address 0, bit 3.
An 8-bit digital PWM circuit uses an internal 5.8 Mhz oscillator as an input frequency. Each PWM period is
defined by 255 (28 –1) intervals where the number of ON intervals is controlled by the value of an 8-bit binary
input word from the digital filter output. The PWM generator is implemented such that duty cycle is:
Duty cycle
n
+ ǒ28 n– 1Ǔ + 255
Where:
n = decimal equivalent of the 8-bit binary input word
coast mode, (EEPROM address 0, bit 4, default = H)
When coast function is enabled (EEPROM address 0, bit 4 = H), the device uses a special mode to control speed
of the motor when it exceeds the selected reference speed. Referring to Figure 10, when FGSOUT frequency
exceeds f(ref) by 5%, resulting in a loss of lock detect, the high-side FET gate drives (UGx) are disabled and the
low-side FET drives (LGx) continue to sequence as per the commutation table. This will continue until FGSOUT
frequency drops below f(ref), which re-enables the high-side gate drives. The coast mode will override
synchronous rectification mode if both are enabled (see following) after the FSGOUT signal exceeds f(ref).
POST OFFICE BOX 655303
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
f(FGSOUT)
(Motor RPM)
Coast
+5%
f(ref)
–5%
Lock Detect
Range
Figure 10. Coast Mode Operation
synchronous rectification mode (EEPROM address 0, bit 3, default = H for TPIC43T01, default = L for
TPIC43T02)
The TPIC43T01 is set up with synchronous rectification enabled. With synchronous rectification enabled
(EEPROM address 0, bit 3 = H), the complimentary LGx of the phase being pulse-width-modulated will turn ON
inversely to UGx during each PWM cycle. This provides a low resistance path through the low-side FET,
operating in inverse, for recirculating inductive current of the motor winding. This technique improves drive
efficiency over allowing the inductive energy to recirculate through the FET’s drain-body diode. Dead-time will
be controlled in each half-H between upper to lower and lower to upper transitions to prevent high current
conduction directly through the power FETs. During this dead-time, recirculation current, due to load inductance,
will occur in the lower FET body diode. After dead-time, the complimentary LGx will be turned on, thus reducing
power dissipation by using the lower FET in inverse to produce a lower voltage drop across rDS(ON) than would
occur across VF of the FET drain-body diode (see Figure 11).
f(FG)
(Motor RPM)
Sync Blanking
+5%
fref
–5%
Synchronous
Rectification
Lock Detect
Range
Synchronous
Rectification
Figure 11. Synchronous Rectification/Coast Mode Operation
The TPIC43T02 is set up with synchronous rectification disabled. With synchronous rectification disabled
(EEPROM address 0, bit 3 = L), the complimentary LGx will stay low during the OFF time of UGx, and inductive
current will thus recirculate through the lower external FET drain-body diode for the duration of t(OFF).
16
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
digital integrator gain selections
In Table 4, EEPROM bits can be set for different clocking rates of the digital integrator. In effect, this allows for
different integrator gain, thereby allowing the user to optimize loop performance (see Figure 12). The integrator
circuit actually utilizes 14 bits with a 4-bit pre-integrator prior to the 10 bits which are output to the digital filter.
This design increases resolution in the error detected by the speed discriminator while reducing the bit-count
output to the digital filter.
Table 4. Digital Integrator Gain Selection Table
EEPROM
ADDR 0
BIT 2
EEPROM
ADDR 0
BIT 1
EEPROM
ADDR 0
BIT 0
0
0
0
INTEGRATOR INPUT
FREQUENCY DIVIDE
DOWN
÷ 1†
0 dB
5.8 MHz
0
1
0
÷2
– 6 dB
2.9 MHz
0
0
1
÷3
– 9.5 dB
1.93 MHz
1
0
0
÷4
– 12 dB
1.45 MHz
0
1
1
÷6
– 15.5 dB
967 kHz
1
1
0
÷8
– 18 dB
725 kHz
1
0
1
÷ 12
– 21.5 dB
483 kHz
÷ 16
– 24 dB
363 kHz
1
1
1
† Default setting for integrator clock.
Up
Down
PreIntegrator
(4 Bits)
INTEGRATOR
GAIN ADJUST
TYPICAL INTEGRATOR
INPUT FREQUENCY
Integrator
(10 Bits)
Input Frequency
B0
B1
B2
Divide-By
Gain
Adjust
Digital
Filter
8-Bit
PWM
Generator
5.8 MHz
OSC
Figure 12. Integrator Implementation
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
digital filter coefficients
The two digital filter coefficients can be set by programming the EEPROM to select the pole and zero for the
digital filter. The pole and zero values are directly proportional to the digital filter sample rate, T(s), and the filter
gain is independent of T(s). The adjustment range of T(s) is from 250 µs to 1 ms (see Figure 13). The K1 lead
coefficient value is stored in bits 2–7 of Address 1 as a BCD equivalent of the K1 coefficient. K1 has a range
from 0 to 63, with a default setting of 28. See Table 5 for a typical range of pole and zero frequencies at
T(s) = 500 µs. The K 2 coefficient value is stored in bits 5 –7 of Address 0 (see Table 6 and Figure 14).
The gain of the digital filter is given by the equation:
OUT
+ IN
[128 Z – K2]
Z–K1 128
ń
0.25
Where:
Z represents a delay of one period of the f(s) sampling clock.
The scaling factor of 0.25 in the above equation accounts for the difference in word lengths in the integrator
(10 bits), the filter (17 bits) and the PWM generator (8 bits).
+
Digital
Integrator
(10-Bit Data Word)
+
Σ
–
1/Z
K2
PWM
Generator
(8-Bit Data Word)
Σ
+
K1
Figure 13. Digital Filter System Diagram
Table 5. Filter Zero and Gain as a Function of K2, Ts = 500 µs
K1 = 14 (POLE = 704 Hz)
K1 = 28 (POLE = 483 Hz)
K1 = 56 (POLE = 263 Hz)
ZERO (Hz)
GAIN
ZERO (Hz)
GAIN
ZERO (Hz)
GAIN
127
6.2
0.28
4.8
0.32
3.7
0.45
126
12.4
0.28
9.7
0.32
7.3
0.45
125
18.4
0.42
14.5
0.48
11
0.68
124
24.7
0.28
19.3
0.32
14.6
0.45
123
30.9
0.35
24.2
0.4
18.3
0.56
122
37.1
0.42
29
0.48
21.9
0.68
121
43.3
0.25
33.9
0.28
25.6
0.39
120
49.4
0.28
38.7
0.32
29.2
0.45
K2
18
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
Table 6. Digital Coefficient Truth Table
EEPROM
ADDR 0
BIT 7
EEPROM
ADDR 0
BIT 6
EEPROM
ADDR 0
BIT 5
K2
COEFFICIENT
0
0
0
120
0
0
1
121
0
1
0
122
0
1
1
1
0
0
123
124†
1
0
1
125
1
1
0
126
1
1
1
† Default setting for the digital filter coefficient
127
DIGITAL FILTER ZERO
vs
K2 and K1 FILTER COEFFICIENT, (TS = 500 µs)
50
45
K1 = 14
Digital Filter Zero – Hz
40
K1 = 28
35
30
Default Zero Setting
25
K1 = 56
20
15
10
5
0
120
121
122
123
124
125
126
127
K2 and K1 Filter Coefficient
Figure 14. Digital Filter Coefficient
FG watchdog
The FG watchdog monitors FGOUT output, allowing an internal timer to count until a transition in FGOUT occurs
and clears the counter. Should timer time-out occur by reaching a count equivalent to 25 ms (512 counts of the
PWM clock), two actions are taken: 1) speed discriminator UP error output is set to 100%; 2) lock detect is set
and lock timer begins counting (see lock timer oscillator/counter section). These actions ensure the digital
integrator counts up (increasing motor drive PWM) at startup of the system, or, if the FG signal is lost during
operation and if no detection of an FG period of < 25 ms occurs for the duration of the lock timer, the IC will go
into shutdown mode, disabling the motor drive (see shutdown section).
POST OFFICE BOX 655303
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
current limit/over-current shutdown
Referring to Figure 15, two comparators monitor the voltage drop across an external current sensing resistor,
R(SENSE). The sensed voltage, V(SENSE), is then compared against two VCC referred voltages, VL and V(OCSD).
When V(SENSE) exceeds VL, the ILIM comparator outputs a high level. When V(SENSE) exceeds V(OCSD), the
OCSD comparator also outputs a high level. The combination of these two comparator outputs is then used in
conjunction with a deglitch or blanking timer to discriminate between a high di/dt, short-duration current spike.
This spike is commonly caused by reverse recover time (trr) current at the start of each PWM cycle and a portion
of the current waveform with lower di/dt. The lower di/dt is controlled by the L/R time constant of the motor
winding (see Figure 16). A comparator is also used to detect over current conditions caused by a shorted-load
or shorted phase-winding to GND (see Figure 17).
VCC
R
OCSD
Q
OCSD
COMP
D
+
V(sense)
R(sense)
IDET
S/S
PWM
Control
Digital
Deglitch
(0.5 – 2 µs)
PWM_START
OSC
ILIM
COMP
+
_
SENSE
3-Phase
Motor
VDD
Vref
A
+
Power
Drivers
_
ILIMIT
Block
V(thres)
Generation
Figure 15. ILIMIT/OCSD Diagram
20
2×R
+
_
Q CLK
CLR
PWM_OFF
V(LM)
VOCSD
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B
C
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
current limit/over-current shutdown (continued)
The deglitch timer prevents the ILIM COMP high from being recognized unless it occurs for the duration of the
timer, after which a high IDET level occurs. This IDET level is used to terminate, or latch off the upper gate drive
being driven by PWM for the remainder of the PWM interval. This ILIM latch and deglitch timer clears at the start
of each new PWM cycle; thus, a cycle-by-cycle PWM controlled current limit is implemented.
Amplitude
VOCSD
Current spike from trr
VL
VCC – VSENSE
t(DG) = 0.5 to 6.5 µs
ILIM
COMP
t(DE-GLITCH)
IDET
OCSD
COMP
OCSD
time
Figure 16. Normal Motor Current Waveform With trr Spike at Start of PWM Cycle
Amplitude
High Ipeak from shorted phase winding
or shorted-phase-to-GND(> 5 A depending on the value of R(SENSE))
VOCSD
VL
VCC – VSENSE
t(ocsd) = 0.5 to 2.5 µs
Combination of IDET high and OCSDCOMP high
sets OSCD latch
Latches high until S/S cycles
time
Figure 17. Motor Current Waveform With Shorted Phase Winding or Shorted Phase to GND
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
EEPROM registers
There are two user configurable EEPROM bit registers accessible through the serial test interface when the
device is configured in TEST mode. This mode is enabled when the TEST pin is held high at 5 V. Once the device
is placed in TEST mode, either register can be programmed by transmitting a 16-bit word. The first three bits
of this transmission are the address and R/W for the register the user wishes to modify. The next five bits must
be held low, and the remaining eight bits are configuration bits. Each register must be programmed
independently, i.e. once the register value is written, the VPP pin must immediately be taken to 13.5 V in the
manner described in the EEPROM Programming section. The two EEPROM registers are summarized in
Table 7. A detailed definition outlining the function of each bit in the EEPROM is presented in the respective
functional description sections of this specification (see Notes 5 and 6).
Table 7. EEPROM Register Definition
ADDR
EEPROM REGISTER CONFIGURATION BITS
BIT 7
0
BIT 6
BIT 5
K 2 Coefficient
BIT 4
BIT 3
Coast Enable
Synchronous
Rectification
BIT 2
BIT 1
BIT 0
Integrator Gain Select
TPIC43T01 default
1
0
0
1
1
0
0
0
TPIC43T02 default
1
0
0
1
0
0
0
0
TPIC43T01 default
0
1
1
1
0
0
1
1
TPIC43T02 default
0
1
1
1
0
0
1
1
1
K1 Coefficient
FG Frequency Select
NOTES: 5. Bit 0 in the EEPROM register definition table corresponds to D0 and E0 in the serial protocol sequence.
6. Data read out of the EEPROM corresponds to the contents of the register at the time it is read. (A register can
be read after programming it in order to verify that the EEPROM was programmed properly.)
serial test interface
User-programmable functions are controlled using two 16-bit EEPROM registers. These registers are
programmed by placing the device in program/test mode by pulling the TEST pin high and transferring data
using the serial interface. Pins 14 and 17–19 are multipurpose pins, which are configured for serial test mode
when the TEST pin is high (see Table 8).
Table 8. Serial Test Interface Pin Definition
PIN
NAME
NO.
PIN DESCRIPTION
SO
14
Serial data output. SO is an output terminal that reads data from the EEPROM.
SCLK
17
Serial clock. SCLK clocks the shift register. Serial data is clocked into the serial data input (SI) port on the rising edge of the
serial clock. Serial output data is clocked out of the serial data output (SO) port on the rising edge of the serial clock.
SIENB
18
SI
19
Serial transfer enable. A low to high transition on the SIENB pin enables the serial interface to send or receive data (see Figure
2). The SIENB signal must be taken low after 16 bits of data has been transferred to insure data has been loaded into the proper
bit locations. During program mode, the VPP input is strobed after SIENB is taken low to program the EEPROM.
Serial input. SI is an input terminal to load the EEPROM input register.
VPP
TEST
35
EEPROM program voltage. VPP transfers data from the EEPROM input register to the respective address location.
36
Serial interface/test mode enable. TEST is taken high to enable the serial interface.
22
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TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
EEPROM programming
Figure 18 presents the sequence of events required to program the onboard EEPROM. To begin the procedure,
the device must be placed into test mode by setting VPP to GND, TEST to VDD and VCC > 8 V. The SIENB input
must transition high to enable the serial input port (see Figure 19). Serial data is clocked into SI on the rising
edges of SCLK. Sixteen bits of data must be transferred during each serial transfer and SIENB must be set to
0 after the sixteenth clock. The first two bits transferred select the EEPROM address to be manipulated. Address
bit A0 is the least significant bit (LSB). The third bit sets the interface into read or write mode. A 1 selects a read
operation from the EEPROM and a 0 selects a write operation to the EEPROM. Set the next five unused bits
to 0. The next 8 bits of data are used for write operations, and are unused and should be set to zero for read
operations. The definition of the data word is presented in Table 7. SIENB must be set to 0 after the 16-bit transfer
has been completed. When new data is being programmed into the EEPROM, the VPP pin must transition to
13.5 V for at least 5 ms and then back to GND (see Figure 20). This completes the serial transfer and
programming sequence. Another transfer can begin using the same procedure. Only one register can be
programmed at a time. The TEST pin must be set to 0 after programming has been completed to disable the
serial test mode and reconfigure the multipurpose pins for normal operation.
Start
Set VPP = GND; Set TEST = VDD, VCC > 8 V
Set SIENB = H
Shift Address and Data into SI
Set SIENB = L
Ramp VPP to 13.5 V then back to GND
Figure 18. Recommended EEPROM Programming Sequence
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
VPP
SIENB
SCLK
SI
1
X
A0
2
A1
3
R/W
4
0
5
0
6
0
7
0
8
9
0
E0
10
11
E1
E2
12
13
E3
E4
14
E5
15
E6
16
E7
X
To Read EEPROM Registers:
SI
X
A0
A1
1
X
X
SO
D0
D1
D2
D3
D4
D5
D6
X
D7
To Write EEPROM Registers:
SI
X
A0
A1
0
X
E0
E1
E2
E3
E4
E5
Figure 19. Serial Protocol
tsu(VPP)
SIENB
tr(VPP)
tf(VPP)
90%
VPP
10%
VPP
10%
tw(VPP)
Figure 20. VPP Programming Waveforms
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
E6
E7
X
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
SLIS098 – APRIL 2000
PRINCIPLES OF OPERATION
charge pump
An external charge pump capacitor (CP) is connected across the CP1 and CP2 pins. An external storage
capacitor (CS) with a typical value of 0.01 µF is connected from VCP to VCC (see functional block diagram). The
charge pump output, VCP , powers the high-side gate drive circuitry for the pre-FET drivers. An internal CPUV
monitors the voltage between VCP and VCC and disables all outputs through a signal to the global shutdown
circuit until VCP – VCC ≥ 5 V. The VCP voltage level is internally regulated to VCC + 15 V (typical).
pre-FET drivers
The TPIC43T01/02 contains three pre-FET driver blocks, each with an upper and lower gate drive for driving
the gates of two external power NMOS FETs configured as a half H-power stage (see Figure 21). The
TPIC43T01/02 is designed to drive the TI TPIC1310 Power+ Array, but it is capable of driving discrete N-channel
FET devices as well. Each pre-FET gate output is capable of sourcing at least 60 mA peak current and sinking
at least 100 mA peak of current. The lower gate drive outputs provide VGS to the external FET from 14 to 20 V.
The upper gate drive outputs drive the external FET gate from VCP and provide VGS voltage protection (clamp
UGx pin with respect to Phx pin) to prevent the gate voltage from exceeding 19 V and damaging the external
FET in the event of a shorted-load or shorted-phase winding to ground.
Half-H
Pre-FET
Drive Stage
VCP
UGx
Upper Gate
Drive
3-Phase
Brushless Motor
PHx
Pre-Regulator
LGx
Lower Gate
Drive
PGND
Figure 21. Pre-FET Driver Output Stage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
TPIC43T01DAR
ACTIVE
TSSOP
DA
38
TPIC43T02DA
ACTIVE
TSSOP
DA
38
TPIC43T02DAR
ACTIVE
TSSOP
DA
38
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TBD
CU NIPDAU Level-3-220C-168 HR
40
TBD
CU NIPDAU Level-1-220C-UNLIM
2000
TBD
CU NIPDAU Level-1-220C-UNLIM
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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