TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
D
D
D
D
D
D
D
D
D
D
D
D
Serial or Parallel Control of Gate Outputs
Sleep State for Low Quiescent Current
Independent On-State Source
Short-to-Ground (Shorted-Load)
Detection/Protection
Independent On-State Over-Current
Detection/Protection With Dynamic Fault
Threshold
Independent Off-State Open-Load
Detection
Supply Over-Voltage Lockout Protection
Asynchronous Open-Drain Fault Interrupt
Terminal to Flag Fault Conditions. Output
Can be OR’ed With Multiple Devices
Encoded Fault Status Reporting Through
Serial Output Terminal (2-Bits Per Channel)
Programmable On-State Fault Deglitch
Timers
High Impedance CMOS Compatible Inputs
With Hysteresis
Fault Mode Selection: Outputs Latched Off
or Switched at Low Duty Cycle
Device Can be Cascaded With Serial
Interface
DA PACKAGE
(TOP VIEW)
CS
SD0
SDI
SCLK
AR_ENBL
GND
IN1
IN2
IN3
IN4
VCC
V(PK_A)
V(PK_B)
V(COMP1)
V(COMP2)
V(COMP3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PGND
V(PWR)
CP1
CP2
V(CP)
GATE1
SRC1
GATE2
SRC2
GATE3
SRC3
GATE4
SRC4
FLT
RESET
V(COMP4)
description
The TPIC44H01 is a four channel high-side pre-FET driver which provides serial or parallel input interface to
control four external NMOS power FETs. It is designed for use in low frequency switching applications for
resistive or inductive loads, including solenoids and incandescent bulbs.
Each channel has over-current, short-to-ground, and open-load detection that is flagged through the FLT pin
and distinguished through the serial interface. Over-current thresholds are set through the V(PK_x) and
V(COMP1-4) pins. Short-to-ground and open-load thresholds are set internally to approximately 2.5 V. The
AR_ENBL pin is used to define the operation of the device during a fault condition, allowing the outputs to either
latch off or to enter a low duty cycle, auto-retry mode. An over-voltage lockout circuit on V(PWR) protects the
device and the external FETs. A low current sleep state mode is provided to allow the TPIC44H01 to be used
in applications where V(PWR) is connected directly to the battery. An internal charge pump allows the use of
N-channel FETs for high-side drive applications, while current-limit gate drive provides slope control for reduced
RFI.
By having the unique ability to develop a dynamic over-current threshold, the TPIC44H01 can be used to drive
incandescent bulbs with long inrush currents without falsely flagging a fault. Likewise, the user can select an
internally set over-current threshold of ~1.25 V by pulling the respective V(COMP1-4) pin to VCC.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
description (continued)
The 8-bit serial peripheral interface (SPI) allows the user to command any of the four outputs on or off, to
program one of eight possible open-load, over-current, and short-load fault deglitch timer settings, and to
engage the sleep state. Data is clocked into the SDI pin on the rising edge of SCLK and clocked out of the SDO
pin on the SCLK falling edge. The serial input bits are logic OR’ed with the IN1-IN4 parallel inputs pins. The serial
interface is also used to read normal-load, open-load, over-current, and short-to-ground conditions for each
channel. Over-voltage lockout can be detected when the FLT pin is low and no bits are set in the SDO register.
Multiple TPIC44H01 devices may be cascaded together using the serial interface to further reduce I/O lines from
the host controller.
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TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
schematic/block diagram
0.01 µF
V(PK_B)
Vpeak
Buffer
V(PK_A)
Vpeak
Buffer
VpeakA
Vbg
0.1 µF
CP2 V(CP)
CS
OVLO
VpeakB
OSC
OVDS Vthres1
OVDS Vthres
Generation
V(COMP1)
AR_ENBL PGND CP1 CP
V(PWR)
OVLO
+
OVDS Vthres
Generation
Vbg
OVDS
Vthres
OVDS Vthres2
OVDS tDG
Vbg
OVDS Vthres
Generation
+
OVDS Vthres3
Gate
Control
OVDS Vthres4
FLT
PS
D
CLK
IN1
GATE1
HS Gate
Drive
7-V Int
+
Channel 1
Output
Gate Drive and
Fault Protection Logic
Q
Over-VDS
Detect
–
5-V Int
VpeakB
V(COMP4)
–
0.1 µF 1 µF
I
SRC1
100 Ω
–
On-State ShortLoad Detect
LOAD
Vbg
OVDS Vthres
Generation
+
V
Comp
VpeakB
V(COMP3)
5-V
Vreg
OVLO
Charge
Pump
VpeakA
V(COMP2)
5-V Int
Comp
+
–
Off-State OpenLoad Detect
2 Vbg
IN2
GATE2
Channel 2 Output
IN3
SRC2
IN4
GATE3
Channel 3 Output
SRC3
VCC
RESET
VCC
GATE4
tDG
Parallel Reg
Channel 4 Output
tAR
Sleep
SRC4
Ibias
Control Reg
Sleep
8
CS
2 Vbg
Fault Logic
Band Gap
Global
Ibias
OSC
UVLO/
POR
Vbg
SCLK
4
Charge Pump
Digital Deglitch
Serial Shift Register
SDI
VCC
8
4
Tri-State Buffer
SDO
GND
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3
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
Terminal Functions
PIN
NO.
I/O
DESCRIPTION
1
CS
I
Chip Select. CS is an active low, logic level input with internal pullup. A logic level low on CS enables the
serial interface and refreshes the fault interrupt (FLT). A high on CS enables the serial register to serve as
the fault data register.
2
SDO
O
Serial Data Output. SDO is a logic level, tri-state output that transfers fault data to the host controller. Serial
input data passes to the next stage for cascade operation. SDO is forced into a high impendance state when
CS terminal is in a high state. When CS is in a low state, data is clocked out on each falling edge of SCLK.
3
SDI
I
Serial Data Input. SDI is a logic level input with hysteresis and internal pulldown. Gate drive output control
data is clocked into the serial register using SDI. A high SDI bit programs a particular gate output on, and a
low turns it off, as long as the parallel input is off (OR function).
4
SCLK
I
Serial Clock. SCLK is a logic level input with hysteresis and internal pulldown. SCLK clocks data at the SDI
terminal into the input serial shift register on each rising edge, and shifts out fault data (and serial input data
for cascaded operation) to the SDO pin on each falling edge.
5
AR_ENBL
I
Auto-Retry Enable. AR_ENBL is a logic level input with hysteresis and internal pulldown. When
AR_ENBL=0, an over-current/short-to-ground fault latches the channel off. When AR_ENBL = 1, an
over-current/short-to-ground fault engages a low duty cycle operation.
6
GND
I
Analog ground and substrate connection
7–10
IN1-4
I
Parallel Inputs. IN1-4 are logic level inputs with hysteresis and internal pulldown. IN1–4 provide real-time
control of gate pre-drive circuitry. A high on IN1-4 will turn on corresponding gate drive outputs (GATE1-4).
Gate output status is a logic OR function of the parallel inputs and the serial input bits.
VCC
V(PK_A)
I
5-V logic supply voltage
I
Dynamic over-current fault threshold peak voltage that is shared by channels 1 and 2
V(PK_B)
V(COMP1-4)
I
Dynamic over-current fault threshold peak voltage that is shared by channels 3 and 4
I
Fault Reference Voltage. V(COMP1–4) are used to provide an external fault reference voltage for the
over-current fault detection circuitry. It is also used to generate a dynamic threshold when used in conjunction
with V(PK_x). To guarantee V(COMP) stability, a minimum of 100 pF capacitance should be placed from
V(COMP) to ground.
18
RESET
I
Reset. RESET is an active low, logic level input with hysteresis and internal pullup. A low on RESET clears
all registers and fault bits. All gate outputs are turned off and a latched FLT interrupt is cleared.
19
FLT
O
Fault Interrupt. FLT is an active low, logic level, open-drain output providing real-time latched fault interrupts
for fault detection. A latched FLT is cleared only by a low on CS. The FLT terminal can be OR’ed with other
devices for fault interrupt handling. An external pullup is required.
20, 22,
24, 26
SRC1-4
I
FET Source Inputs. These inputs are used for both open-load and over-current fault detection at the source
of the external FETs.
21, 23,
25, 27
GATE1-4
O
Gate Drive Outputs. Output voltage is derived from V(CP) supply voltage. Internal clamps prevent the voltage
on these nodes, with respect to SRC1-4, from exceeding the VGS rating of most FETs.
V(CP)
CP2
O
Charge pump voltage storage capacitor and supply pin to high-side gate drives
29
O
Charge pump capacitor terminal
30
CP1
O
Charge pump capacitor terminal
31
V(PWR)
PGND
I
Power supply voltage input
I
Power ground for charge pump
11
12
13
14–17
28
32
4
PIN
NAME
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TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Logic supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Power supply voltage range, V(PWR) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 40 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range, VO (SDO and FLT, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Source input voltage, VI(SRCx) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 3 V to 40 V
Output voltage, VO(GATEx) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 45 V
Logic input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 µA
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN
Logic supply voltage, VCC
4.5
Power supply voltage, V(PWR)
TYP
MAX
UNIT
5
5.5
V
24
V
8
High level logic input voltage, VIH (all logic inputs except RESET)
Low level logic input voltage, VIL (all logic inputs except RESET)
0.7×VCC
0
Setup time, SDI high before SCLK rising edge, tsu (see Figure 5)
10
Hold time, SDI high after SCLK rising edge, th (see Figure 5)
10
Operating case temperature, TC
VCC
0.3×VCC
V
V
ns
ns
– 40
125
°C
thermal resistance
PARAMETER
TEST CONDITIONS
RθJA
Junction-to-ambient thermal resistance
RθJC
Junction-to-case thermal resistance
Using JEDEC, low K, board configuration
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MIN
TYP
MAX
UNIT
86.04
°C/W
7.32
°C/W
5
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
electrical characteristics over recommended operating case temperature and supply voltage
range (unless otherwise noted)†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I(PWR)
ICCH
V(PWR)supplycurrent
5-V supply current
All outputs off, V(PWR)= 12 V
2
4
6
mA
All outputs off, VCC = 5.5 V
3
4
5
mA
I(PWR-slee
(PWR-sleep))
Sleep state current
Slee
(IPWR)
Sleep state (all outputs
Slee
out uts off)
off),
VCC = 5.5
V, V(PWR) = 12 V,
55V
V TC = 25°C
15
40
µA
ICCL(slee
CCL(sleep))
Sleep state current
Slee
(ICCL)
Sleep state (all outputs
Slee
out uts off)
off),
VCC = 5.5
V, V(PWR) = 12 V,
55V
V TC = 25°C
30
40
µA
VIT(POR)
Power-on reset
threshold, VCC
V(PWR) = 5.5 V, VCC increasing
3.4
3.9
4.4
V
Vhys(POR)
Power-on reset
threshold hysteresis,
VCC
V(PWR) = 5.5 V, VCC decreasing
100
300
500
mV
40
44
V
38
40
42
V
V(PWR) = 8 V,, CP = 0.01 µF,
µ , CS = 0.1 µF,
µ ,
I(CP) = – 2 mA, See Figure 8
11 5
11.5
13 5
13.5
V
V(PWR) = 5.5 V, CP = 0.01 µF,
CS = 0.1 µF, I(CP) = – 2 mA, See Figure 8
6.8
7.5
V
27.5
30
32.5
V
0.5
1
2
V
V(PWR) > 24 V,, CP = 0.01 µF,
µ , CS = 0.1 µF,
µ ,
I(CP) = – 2 mA, See Figure 8
V(CP)
Charge pump
um voltage
V(PWR) = 24 V,
V CP = 0.01
0 01 µF
µF, CS = 0.1
0 1 µF
µF,
I(CP) = – 2 mA
mA, See Figure 8
V(OVLO)
Over-supply voltage
lockout
Gate disabled, See Figure 10
Vhys(OV)
Over-supply voltage
reset hysteresis
See Figure 10
VG
Gate drive voltage
8 V < V(PWR) < 24 V,, IO = –100 µ
µA,,
All channels on, See Note 2
V(PWR)+4
5.5 V < V(PWR) < 8 V,, IO = –100 µA,
µ ,
All channels on, See Note 2
V(PWR)+1
5
+1.5
VG(sleep)
External gate sleep
state voltage
IO = 100 µA, RESET = CS = 0 V
VGS(clamp)
Gate-to-source clamp
voltage
VSG(clamp)
V(PWR)+18
V(PWR)+3
5
+3.5
V
V
0
100
300
mV
SRCx = 0 V, Output on
15
17
19.5
V
Source-to-gate clamp
voltage
Output off, II = 100 µA
6.5
8
9.5
V
IG(SRC
G(SRCx))
Gate drive source
current
– 2.3
–3
– 3.7
– 1.4
–2
– 2.6
IG(SNK
G(SNKx))
Gate drive sink
current
VG = 0 V, V(PWR) = 12 V
VG = 10 V, V(PWR) = 12 V
VG = 2 V, V(PWR) = 12 V
1
1.5
2
2
2.6
3.2
V(open)
SRCx pin off-state
open-load detection
threshold
All outputs off, See Figure 11
1.9
2.4
2.6
Vhys(open)
Off-state open-load
hysteresis
All outputs off
– 50
– 150
– 300
VG= V(PWR) = 12 V
† Device will function with degraded performance for a power supply voltage between 5.5 V and 8 V.
NOTE 2: For characterization purposes only, not implemented in production testing.
6
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mA
mA
V
mV
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
electrical characteristics over recommended operating case temperature and supply voltage
range (unless otherwise noted)† (continued)
PARAMETER
I(open)
Off-state open-load
detection current
V(OVDS)
(
)
Drain-to-source
Drain
to source
over-voltage
over voltage
V(STG)
On-state
short-to-ground
detection voltage
Vhys(STG)
On-state
short-to-ground
hysteresis
I(pullup)
Logic input pullup
current
(CS, RESET)
I(pulldown)
TEST CONDITIONS
MIN
All outputs off
TYP
UNIT
– 20
– 50
– 70
µA
1
1.25
1.5
V
V(COMPx) > VCC – 250 mV
0.95 × V(COMPx)– 15
mV
0.1 V < V(COMPx) < 2.5 V,,
See Figures 12 and 13
MAX
See Figure 17
1.05 × V(COMPx)+15
mV
V
1.9
2.35
2.6
–50
–150
–300
mV
VCC = 5 V, VIN = 0 V
–5
–20
–50
µA
Logic input pulldown
current (IN1 – 4, SCLK,
SDI, AR_ENBL)
VCC = 5 V, VIN = 5 V
5
20
50
µA
Vhys
Logic input voltage
hysteresis (IN1 – 4,
SCLK, SDI, AR_ENBL,
CS)
VCC = 5 V
0.5
0.8
1.2
V
VOH
High level serial output
voltage
IO = – 1 mA
VOL
Low level serial output
voltage
IO = 1 mA
IOZ
Serial data output
tri-state current
V(SDO) = 5.5 V to 0 V,
VCC = 5.5 V
VOL(FLT)
FLT low level output
voltage
Ilkg(FLT)
FLT leakage current
VIH(RESET)
RESET high level logic
input voltage
VIL(RESET)
RESET low level logic
input voltage
Vhys(RESET)
Logic input voltage
hysteresis (RESET)
0.8×VCC
4.96
V
V
0
100
400
mV
– 35
1
35
µA
IO = 220 µA
0
30
350
mV
R(pullup) = 25 K, VCC = 5.5 V
0
1
20
µA
1.9
2.2
VCC
V
0
1.2
1.4
V
0.6
1
1.4
V
VCC = 5 V
† Device will function with degraded performance for a power supply voltage between 5.5 V and 8 V.
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7
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
switching characteristics, VCC = 5 V, V(PWR) = 12 V, TC = 25°C
PARAMETER
t(STG)
t(OC)
Short-to-ground deglitch time
t(OL)
t(retry)
Open-load deglitch time
tPLH
TEST CONDITIONS
Over-current deglitch time
SDI bits DG1–3 = 0 ((default after POR),
),
See Figures 11, 12, and 17 and Table 4
Auto-retry time
Propagation turn-on delay, CS or IN1 – 4 to
GATE1 – 4
tPHL
Propagation turn-off delay, CS or IN1 – 4 to
GATE1 – 4
f(SCLK)
Serial clock frequency
tsu(lead)
Setup from the falling edge of CS to the
rising edge of SCLK
TYP
MAX
UNIT
16
µs
120
µs
120
µs
15
ms
5
µs
5
µs
pF See Figures 1 and 2
CG = 400 pF,
t(WH)= t(WL) = 0.5/f(SCLK), See Figure 5
1
5
MHz
100
ns
100
ns
50
ns
50
ns
150
ns
12
ns
512
µs
See Figure 5
tsu(lag)
Setup from the falling edge of SCLK to
rising edge of CS
tpd(SDOEN)
Propagation delay from falling edge of CS
to SDO valid
tpd(valid)
Propagation delay from falling edge of
SCLK to SDO valid
tpd(SDODIS)
Propagation delay from rising edge of CS
to SDO Hi-Z state
tf(FLT)
Fall time of FLT output
RL = 10 kΩ, CL = 200 pF, See Figure 3
t(active)
POR-to-active status delay, sleep-to-active
status delay
See Figure 4
8
MIN
RL = 10 kΩ, CL = 200 pF, See Figure 5
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TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC
50%
VCC
CS or IN1–4
0V
50%
CS or IN1–4
0V
VCC
tPLH
GATE1–4
50%
V(PWR)
90%
0V
V(CP)
tPHL
0V
V(CP)
GATE1–4
10%
0V
Figure 2. Gate Control Turn-Off
Figure 1. Gate Control Turn-On
VCC
POR Threshold
Input
90%
FLT
10%
tf (FLT)
VCC
Internal
Sleep Bit
0V
t(active)
t(active)
GATEx
Figure 3. Fault Interrupt Fall Time
Figure 4. Power-Up Waveforms
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9
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
FLT
tsu(lead)
tsu(lag)
CS
t(WH)
50%
SCLK
1
Hi-Z
t(SCLK)
2
7
tsu
tpd(valid)
tpd(SDOEN)
SDO
t(WL)
90%
90%
10%
10%
tpd(SDODIS)
Hi-Z
th
SDI
90%
10%
Fault Data
Register Latch
(Internal)
Fault Data
Register Refresh
(Internal)
SDO
RL
CL
SDO Output Test Schematic
Figure 5. Serial Interface Timing Diagram
10
8
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TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
serial data operation
The TPIC44H01 offers a serial interface to a host microcontroller to receive control data and to return fault data
to the host controller. For the serial interface operation, it is assumed that all parallel inputs, IN1 – 4, are low. The
serial interface consists of:
SCLK
CS
SDI
SDO
Serial clock
Chip select (active low)
Serial data input
Serial data output
After a CS transition from high to low, serial data at the SDI pin is shifted, MSB first, into the serial input shift
register on the low-to-high transition of SCLK. Eight SCLK cycles are required (see Table 1) to shift the first data
bit from LSB to MSB of the shift register. Eight SCLK cycles must occur before a transition from low to high on
CS to insure proper control of the outputs. Less than eight clock cycles will result in fault data being latched into
the output control buffer. Sixteen bits of data can be shifted into the device, but the first eight bits shifted out are
always the fault data and the last eight bits shifted in are always the output control data. A low-to-high transition
on CS will latch bits 1 – 4 of the serial shift register into the output control buffer, bits 5 – 7 into the deglitch timer
control register, and bit 8 into the sleep state latch. A logic 0 in SDI bit1 –4 will turn the corresponding gate drive
output off (providing the parallel input for that channel is at a logic low state); likewise, a logic 1 will turn the output
on. Functionality of bits 5 – 7 is detailed in Table 4. A logic 1 in SDI bit 8 will enable sleep state and a logic 0 will
maintain normal operation.
Table 1. Serial Data Input Shift Register Bit Assignment
SDI, Normal Protocol (8–SCLKs)
LSB
(Last In)
SDI
MSB
(First In)
Shift Direction
B1
B2
B3
B4
B5
B6
B7
B8
IN1
IN2
IN3
IN4
DG1
DG2
DG3
SLEEP
Table 2. Serial Data Output Shift Register Bit Assignment
SDO, Fault Bit Protocol (8–SCLKs)
MSB
(First Out)
SDO
LSB
(Last Out)
Shift Direction
B8
B7
B6
B5
B4
B3
B2
B1
F4B
F4A
F3B
F3A
F2B
F2A
F1B
F1A
Table 3. Fault Bit Encoding
FAULT CONDITION
FxB
FxA
FLT
Normal – no faults
X
X
1
Over-voltage
0
0
0
Open-load
0
1
0
Over-current
1
0
0
Short-to-ground
1
1
0
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11
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
Table 4. Deglitch Time Encoding
0
SHORT-TO-GND
DEGLITCH TIME,
t(STG)
(µs)
16†
SHORT-TO-GND
DUTY CYCLE
WITH:
AR_ENBL=1
0.1%†
OVER-CURRENT
DEGLITCH TIME,
t(OC)
(µs)
120†
OVER-CURRENT
DUTY CYCLE
WITH:
AR_ENBL=1
0.75%†
AUTO-RETRY
TIME,
t(retry)
(ms)
16†
OPEN-LOAD
DEGLITCH
TIME, t(OL)
(µs)
120†
0
1
4
0.1%
30
0.75%
4
30
1
0
8
0.1%
60
0.75%
8
60
0
1
1
32
0.1%
240
0.75%
32
240
1
0
0
120
0.1%
120
0.75%
16
120
1
0
1
30
0.1%
30
0.75%
4
30
1
1
0
60
0.1%
60
0.75%
8
60
1
1
1
240
0.1%
240
0.75%
32
240
DG1
SDI
BIT5
DG2
SDI
BIT6
DG3
SDI
BIT7
0
0
0
0
† Indicated default conditions after power up.
SDO MSB fault data is setup on the SDO pin by the high-to-low transition of CS prior to the first low-to-high
transition of SCLK. Thus, there must be a lead time, tsu(lead) (see Figure 5), in the host controller from CS
high-to-low transition to the first rising edge of SCLK to allow the SDO tri-state output to enable and to setup
the fault data MSB on the SDO pin. The remaining 7 bits of fault data are shifted out by the falling edge of the
next 7 SCLK cycles. To prevent data from prematurely shifting out of SDO on a low transition of CS while SCLK
is high, the device requires a low-to-high transition on SCLK after a low transition on CS before the second fault
bit is shifted out. One SCLK cycle is required to clear the serial data register and latch in fault data. If a low
transition on CS occurs without a low-to-high transition on SCLK, then fault data remains in the SDO register
and the device will not latch data into the control register.
The serial register serves as the fault register while CS is high. Thus, a fault occurring any time after the end
of the previous serial interface protocol (low-to-high transition of CS) will be latched as a fault in the serial register
and will be reported via SDO during the next serial protocol. The FLT interrupt will refresh on the high-to-low
transition of CS. The CS input must be driven to a high state after the last bit of serial data has been clocked
into the device. The rising edge of CS will inhibit the SDI input port, put the SDO output port into a high
impedance state, latch the 4 bits of SDI data into the output buffer, and clear/re-enable the serial fault registers
(see Figure 6).
1
2
3
4
5
6
7
8
SCLK
CS
SDO
Hi-Z
FLT4B
FLT4A
FLT3B
FLT3A
FLT2B
FLT2A
FLT1B
FLT1A
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Hi-Z
Figure 6. SDO Timing Diagram
The TPIC44H01 serial data interface allows multiple devices to be cascaded together to reduce I/O from the
host controller by using a single CS line. In this configuration, 8 bits of data for every cascaded TPIC44H01 must
be sent during the time that CS is low for proper operation (see Figure 7 for an example of two cascaded
TPIC44H01s). If less than 8 bits of data per cascaded device is sent during the time CS is low, the wrong output
may be enabled or disabled, and some fault data will be latched to the output(s) once CS returns high.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
CS
SCLK
SDI
1st
TPIC44H01
SDO
CS
µC
SCLK
MOSI
MISO
MISO = Master In Slave Out
MOSI = Master Out Slave In
CS
SCLK
SDI
2nd
TPIC44H01
SDO
LAST IN
FIRST IN
SDI Shift Direction
LSB
B1
1st
IN1
MSB
B2
1st
IN2
B3
1st
IN3
B4
1st
IN4
B5
1st
DG1
B6
B7
1st
1st
DG2 DG3
B8
1st
SLEEP
B1
2nd
IN1
B2
2nd
IN2
B3
2nd
IN3
B4
2nd
IN4
B5
2nd
DG1
B6
2nd
DG2
FIRST OUT
SDO Shift Direction
B7
2nd
F4A
B8
2nd
SLEEP
LAST OUT
MSB
B8
2nd
F4B
B7
2nd
DG3
B6
2nd
F3B
B5
2nd
F3A
B4
2nd
F2B
B3
2nd
F2A
B2
2nd
F1B
LSB
B1
2nd
F1A
B8
1st
F4B
B7
1st
F4A
B6
1st
F3B
B5
1st
F3A
B4
1st
F2B
B3
1st
F2A
B2
1st
F1B
B1
1st
F1A
Figure 7. Cascading Multiple TIPC44H01s
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
parallel input data operation
In addition to the serial interface, the TPIC44H01 also provides a parallel interface to control gate drive outputs.
Parallel input is OR’ed with the serial interface control bit. Thus, the parallel inputs provide direct, real-time
control of the output drivers. SCLK and CS are not required to transfer parallel input data to the output buffer.
Fault detection/protection is provided during parallel operation (see performance under fault conditions
section).
With AR_ENBL pin low, detection of an over-current or short-to-ground fault condition will disabled the gate drive
until the auto-retry timer clears and re-enables the output.
CAUTION:
If a parallel input is cycled low then high during auto-retry time, the timer is reset and the gate drive
re-enable. The device will not prevent the user from switching at a higher duty cycle than the
auto-retry function provides.
Serial fault data can be read over the serial data bus as described in the serial data operation section. If the FLT
pin is latched low due to a fault detection, it cannot be cleared by cycling the parallel input. It can only be cleared
by a low level on CS.
In applications where the serial interface and FLT interrupt are unused, CS should be tied high to disable the
serial interface.
In applications where the serial interface or FLT interrupt are used only to retrieve fault data, care should be
taken to program the SDI input low to prevent accidental activation of a gate drive output using a serial input
control bit.
charge pump operation
The TPIC44H01 provides a charge pump circuit to generate the high-side gate drive voltage. It is a doubler using
external pump and storage capacitors, CP and CS respectively (refer to the schematic/block diagram). For
V(PWR) voltage levels above 16 V, the charge pump voltage, V(CP), is internally regulated to approximately
V(PWR) + 15 V. However, when V(PWR) voltage rises to higher than 27 V, V(CP) is limited to approximately 42 V
from ground (see Figure 8).
Voltage
42 V
30 V
V(CP)
15 V
14 V
42 V
V(PWR)
Time
Figure 8. Charge Pump Voltage With Respect to V(PWR)
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
gate drive operation
The TPIC44H01 uses a 2-mA source/sink method for external FET gate drive. This gate drive method limits the
current drain from the charge pump so that when one channel is shorted to ground, the device will maintain
sufficient gate drive for the remaining three channels. This benefit allows the user to add an external Miller
capacitor between the FET’s drain and gate pins to reduce the slew rate minimizing radiated emissions (see
Figure 9).
In order to prevent the external FETs from turning on when VCC is not applied to the TPIC44H01, an internal
regulator powered from V(PWR) supplies voltage to the gate drive input control circuitry. This allows the device
to be used in switched VCC applications without the concern of one of the outputs turning on when VCC is low.
An internal zener clamp (15 V – 17 V) from SRCx to GATEx protects the external FET from excessive VGS
voltages. During the flyback event when turning off an inductive load, the diode from GATEx to ground protects
the TPIC44H01 and external FETs from overstress. The voltage at SRCx during flyback will be V(GND) – V(F)
– VGS, where V(GND) is ground potential, V(F) is the forward voltage drop of the internal diode from GATEx to
ground, and VGS is the voltage drop from gate to source of the external FET.
CS
CP
0.01 µF
PGND
CP1
0.1 µF
CP2
V(CP)
Vreg
Charge
Pump
V(PWR)
C(Miller)
HS Gate
2 mA
Drive
HV
Level-Shift
+
GATEx
5-V Int
LS
Logic
100 Ω
2 mA
SRCx
Channel x
Output
LOAD
Gate
Control
Figure 9. Gate Drive Block Diagram
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
performance under fault conditions
The TPIC44H01 is designed for normal operation over a supply voltage range of 8 V to 24 V with over-voltage
fault detection typically at 30 V. The device offers on board fault detection to handle a variety of faults which may
occur within a system. The primary function of the circuitry is to prevent damage to the load and the external
power FETs in the event that a fault occurs, but off-state, open-load detection and reporting is also provided for
diagnostics. Note that unused SRC1 – 4 inputs must be connected to their respective GATE1– 4 pins to prevent
false reporting of open-load fault conditions. Unused outputs with a SRC-to-GATE short should not be
commanded on. For on-state faults, the circuitry detects the fault, shuts off the output to the FET, and reports
the fault to the microcontroller. The primary faults monitored are:
1.
2.
3.
4.
V(PWR) over-voltage lockout (OVLO)
Open-load
Over-current
Short-to-ground
FLT, fault interrupt operation
The FLT pin provides a real-time fault interrupt to signal a host controller that a fault has been detected. Any
of the four fault conditions listed above causes the FLT pin to be latched low immediately upon fault detection.
NOTE:
Once FLT is latched low from a fault occurrence, it can only be cleared by a high-to-low transition
on CS.
V(PWR) over-voltage lockout
The TPIC44H01 monitors V(PWR) supply voltage and responds in the event of supply voltage exceeding OVLO.
This condition may occur due to voltage transients resulting from a loose battery connection. If V(PWR) supply
voltage is detected above 30 V, the device will turn off all gate drive outputs to prevent possible damage to the
internal charge pump, the external FET, and the load. An OVLO fault will be flagged to the controller by FLT being
latched low. The FLT interrupt will be reset by a high-to-low transition of CS, provided that the OVLO condition
is corrected, and no other faults have been detected with internal fault bits set. Thus, the user will detect an
OVLO fault by a low transition on FLT with no fault bit read from SDO (see Table 3). The gate outputs will return
to normal operation immediately after the OVLO condition is removed (the outputs are not latched off). Figure
10 illustrates the operation of the over-supply voltage detection circuit.
V(PWR)
30 V
V(PWR)
+
_
OVLO Output Disable
30 V
29 V
12 V
GATE (1–4)
Figure 10. Over-Voltage Lockout Waveform
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
open load
An off-state, open-load condition is implemented in the TPIC44H01 by monitoring the SRCx terminal voltage
when the FET is turned off by both the parallel input and the SDI bit being a logic 0. Figure 11 illustrates the
operation of the open-load detection circuit. When the GATEx output is low, thus turning off the FET (see
Figure 11), a 50-µA current is internally sourced from VCC to pull up the SRCx pin for open-load fault detection.
If the load is open, or if the impedance is substantially high, the 50-µA current source will cause the SRCx pin
to rise above the ~2.4 V reference threshold of the open-load comparator. Unused SRC1 – 4 inputs must be
connected to their respective GATE1– 4 pins to prevent false reporting of open-load fault conditions. An on
board deglitch timer starts when the open-load comparator detects a SRCx voltage greater than ~2.4 V,
providing time for the SRCx voltage to stabilize after the power FET has been turned off. The SRCx voltage must
remain above the open-load detection threshold for the entire deglitch time, t(OL), (programmable, see Table 4)
for the fault to be recognized as valid. If a valid fault is recognized, a real-time fault is flagged to the host controller
by latching the FLT pin low, and the appropriate fault bit is set. The host controller can read the serial SDO bits
to determine which channel reported the fault. Fault bits (1:8) distinguish faults for each of the output channels
(see Table 2 and Table 3). This feature provides useful diagnostic information to the host controller to
troubleshoot system failures and warn the operator that a problem exists.
If an open-load fault is detected by the TPIC44H01 while an output is off, the gate drive will be disabled the next
time the output is commanded on either through the serial interface or the parallel inputs. In order to re-enable
the gate drive, the load must return to a normal condition and the user must toggle the input to the previously
faulted channel on then off then back on again.
NOTE:
If an open-load fault is detected by the TPIC44H01 while an output is off and AR_ENBL = 0, the
gate drive will be disabled the next time the output is commanded on either through the serial
interface or the parallel inputs. In order to re-enable the gate drive, the load must return to a normal
condition and the user must toggle the input to the previously faulted channel on then off then back
on again.
NOTE:
If an open-load fault is detected by the TPIC44H01 while an output is off and AR_ENBL = 1, the
auto-retry timer will be initiated. This will cause the gate drive output to be delayed by t(retry) from
the input signal. If more than one channel has detected an open-load fault, the delay from the input
signal to the gate drive output signal will depend on which output detected the fault first. This
happens because there is a single auto-retry timer used for all four channels. Normal operation will
return once the fault condition is removed.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
V(PWR)
+
V(CP)
GATEx
HS Gate
Drive
VCC
50 µA
I
100 Ω
Comp
SRCx
LOAD
Deglitch
Timer
2 Vbg
OSC
Normal Load
Open Load
Input
Input
GATEx
GATEx
SRCx
V(open)
SRCx
t(deglitch)
V(OVDS), and resets when VDS < V(OVDS). If the V(OVDS)
threshold is exceeded for the entire deglitch time, a valid over-current shutdown fault (OCSD) is recognized.
If an over-current fault is detected with AR_ENBL = 0, a real-time fault condition is flagged to the host controller
by latching FLT low, the appropriate internal fault bit is set, and the GATEx output is latched off. GATEx will
remain off until the error condition has been corrected and the input bit or parallel input is cycled off then on.
An over-heating condition of the FET can occur if the host controller continually re-enables the output under
short-to-ground conditions.
If an over-current fault is detected with AR_ENBL = 1, FLT is latched low, the appropriate internal fault bit is set,
and the gate output is disabled until an auto-retry timer re-enables it. If the over-current remains, auto-retry
provides a low duty cycle PWM (≈ 0.75%) function to protect the FET from over heating. The PWM period is
defined as t(OC) + t(retry), while the duty cycle is defined as t(OC) / (t(OC) + t(retry)). The auto-retry cycle is
maintained until the fault has been eliminated and/or until the channel is turned off by both the INx parallel input
and the serial control bit. The host controller can read the serial port of the device to determine which channel
reported the fault condition. Fault bits (1:8) distinguish faults for each of the output channels (see Table 3).
V(PWR)
+
V(OVDS)
V
VDS
–
+
Comp
100 Ω
–
SRCx
OSC
LOAD
Deglitch
Timer
Over-Current
AR_ENBL = 0
Normal Load
Over-Current
AR_ENBL = 1
Input
Input
Input
GATEx
GATEx
GATEx
V(OVDS)
V(OVDS)
VDS
VDS