Product
Folder
Sample &
Buy
Technical
Documents
Support &
Community
Tools &
Software
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
TPIC6C596 Power Logic 8-Bit Shift Register
1 Features
•
•
•
1
•
•
•
•
•
•
3 Description
Low RDS(on), 7 Ω (Typical)
Avalanche Energy, 30 mJ
Eight Power DMOS Transistor Outputs of 100-mA
Continuous Current
250-mA Current Limit Capability
ESD Protection, 2500 V
Output Clamp Voltage, 33 V
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
2 Applications
•
•
•
•
Instrumentation Clusters
Tell-Tale Lamps
LED Illumination and Controls
Automotive Relay or Solenoids Drivers
Logic Symbol
G
RCK
CLR
SRCK
SER IN
8
EN3
10
C2
7
R
SRG8
15
C1
2
3
1D
2
4
5
DRAIN0
DRAIN1
DRAIN2
6
DRAIN3
11
DRAIN4
12
DRAIN5
13
DRAIN6
14
DRAIN7
2
9
SER OUT
This symbol is in accordance with
ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
The TPIC6C596 device is a monolithic, mediumvoltage, low-current, 8-bit shift register designed for
use in systems that require relatively moderate load
power such as LEDs. The device contains a built-in
voltage clamp on the outputs for inductive transient
protection. Power driver applications include relays,
solenoids, and other low-current or medium-voltage
loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift
register clock (SRCK) and the register clock (RCK),
respectively. The storage register transfers data to
the output buffer when shift register clear (CLR) is
high. When CLR is low, all registers in the device are
cleared. When output enable (G) is held high, all data
in the output buffers is held low and all drain outputs
are off. When G is held low, data from the storage
register is transparent to the output buffers. When
data in the output buffers is low, the DMOS transistor
outputs are off. When data is high, the DMOS
transistor outputs have sink-current capability.
The serial output (SER OUT) is clocked out of the
device on the falling edge of SRCK to provide
additional hold time for cascaded applications. This
will provide improved performance for applications
where clock signals may be skewed, devices are not
located near one another, or the system must tolerate
electromagnetic interference.
Outputs are low-side, open-drain DMOS transistors
with output ratings of 33 V and 100 mA continuous
sink-current capability. Each output provides a 250mA maximum current limit at TC = 25°C. The current
limit decreases as the junction temperature increases
for additional device protection. The device also
provides up to 2500 V of ESD protection when tested
using the human body model and the 200-V machine
model.
The TPIC6C596 device is characterized for operation
over the operating case temperature range of −40°C
to 125°C.
Device Information(1)
PART NUMBER
TPIC6C596
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm × 3.91 mm
PDIP (16)
19.30 mm × 6.35 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 18
11.3 Thermal Considerations ........................................ 19
12 Device and Documentation Support ................. 20
12.1 Trademarks ........................................................... 20
12.2 Electrostatic Discharge Caution ............................ 20
12.3 Glossary ................................................................ 20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision C (April 2005) to Revision D
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
TPIC6C596
www.ti.com
SLIS093D – MARCH 2000 – REVISED MARCH 2015
5 Pin Configuration and Functions
D, N, or PW Packages
16-Pin SOIC, PDIP, and TSSOP
Top View
VCC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
CLR
G
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
GND
SRCK
DRAIN7
DRAIN6
DRAIN5
DRAIN4
RCK
SER OUT
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CLR
7
I
Shift register clear, active-low
DRAIN0
3
O
Open-drain output
DRAIN1
4
O
Open-drain output
DRAIN2
5
O
Open-drain output
DRAIN3
6
O
Open-drain output
DRAIN4
11
O
Open-drain output
DRAIN5
12
O
Open-drain output
DRAIN6
13
O
Open-drain output
DRAIN7
14
O
Open-drain output
G
8
I
Output enable, active-low
GND
16
—
Power ground
RCK
10
I
Register clock
SER IN
2
I
Serial data input
SER OUT
9
O
Serial data output
SRCK
15
I
Shift register clock
VCC
1
I
Power supply
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
3
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VCC
Logic supply voltage (2)
–0.3
7
V
VI
Logic input voltage
–0.3
7
V
VDS
Power DMOS drain-to-source voltage (3)
–0.3
33
V
Continuous source-to-drain diode anode current
250
mA
Pulsed source-to-drain diode anode current (4)
500
mA
ID
Pulsed drain current, each output, all outputs on, TC = 25°C (4)
250
mA
ID
Continuous drain current, each output, all outputs on, TC = 25°C (4)
100
mA
250
mA
(4)
IDM
Peak drain current single output, TC = 25°C
EAS
Single-pulse avalanche energy (see Figure 11)
30
mJ
IAS
Avalanche current (5)
200
mA
Continuous total dissipation
See Thermal Information
TC
Operating case temperature
–40
125
°C
TJ
Operating virtual junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Each power DMOS source is internally connected to GND.
Pulse duration ≤ 100 μs and duty cycle ≤ 2%.
DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 11).
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
VALUE
UNIT
±2500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Logic supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
4.5
NOM
MAX
5.5
0.85 VCC
(2)
(see Figure 7)
V
V
0.15 VCC
Pulsed drain output current, TC = 25°C, VCC = 5 V, all outputs on (1)
UNIT
250
V
mA
tsu
Setup time, SER IN high before SRCKM ↑ (see Figure 9)
15
ns
th
Hold time, SER IN high after SRCKM ↑, (see Figure 9)
15
ns
tw
Pulse duration (see Figure 9)
40
ns
TC
Operating case temperature
–40
(1)
(2)
4
125
°C
Pulse duration ≤ 100 μs and duty cycle ≤ 2%.
Technique should limit TJ − TC to 10°C maximum.
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
TPIC6C596
www.ti.com
SLIS093D – MARCH 2000 – REVISED MARCH 2015
6.4 Thermal Information
TPIC6C596
THERMAL METRIC (1)
PW (TSSOP)
D (SOIC)
N (PDIP)
16 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
109.7
83.7
51.5
RθJC(
Junction-to-case (top) thermal resistance
44.6
45.1
38.3
RθJB
Junction-to-board thermal resistance
54.8
41.2
31.4
ψJT
Junction-to-top characterization parameter
5
12.1
23.6
ψJB
Junction-to-board characterization parameter
54.2
40.9
31.3
UNIT
top)
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
33
37
MAX
V(BR)DSX
Drain-to-source breakdown
voltage
ID = 1 mA
VSD
Source-to-drain diode forward
voltage
IF = 100 mA
VOH
High-level output voltage, SER
OUT
IOH = − 20 µA,
VCC = 4.5 V
4.4
4.49
IOH = − 4 mA,
VCC = 4.5 V
4
4.2
VOL
Low-level output voltage, SER
OUT
IOL = 20 µA,
VCC = 4.5 V
0.005
0.1
IOL = 4 mA,
VCC = 4.5 V
0.3
0.5
IIH
High-level input current
VCC = 5.5 V,
VI = VCC
IIL
Low-level input current
VCC = 5.5 V,
VI = 0
0.85
V
1.2
µA
–1
µA
20
200
All outputs on
150
500
5
Logic supply current
VCC = 5.5 V
ICC(FRQ)
Logic supply current at
frequency
fSRCK = 5 MHz,
All outputs off,
CL = 30 pF,
See Figure 9 and Figure 2
1.2
IN
Nominal current
VDS(on) = 0.5 V,
TC = 85°C
IN = ID,
See (1) (2) (3)
90
VDS = 30 V,
VCC = 5.5 V
0.1
0.2
IDSX
OFF-state drain current
VDS = 30 V
TC = 125°C
VCC = 5.5 V
0.15
0.3
6.5
9
9.9
12
9.9
10
Static drain-source ON-state
resistance
ID = 50 mA,
TC = 125°C,
VCC = 4.5 V
See (1) and (2) and Figure 3
and Figure 4
ID = 100 mA,
VCC = 4.5 V
(1)
(2)
(3)
V
1
ICC
rDS(on)
V
V
All outputs off
ID = 50 mA,
VCC = 4.5 V
UNIT
µA
mA
mA
µA
Ω
Technique should limit TJ − TC to 10°C maximum.
These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage
drop of 0.5 V at TC = 85°C.
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
5
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
6.6 Switching Characteristics
VCC = 5 V, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
Propagation delay time, low-to-high-level output
from G
tPLH
tr
Propagation delay time, high-to-low-level output CL = 30 pF, ID = 75 mA, See Figure 5,
from G
Figure 8 and Figure 9
Rise time, drain output
tf
Fall time, drain output
tpd
Propagation delay time, SRCK↓ to SEROUT
tPHL
CL = 30 pF, ID = 75 mA, See Figure 9
Serial clock frequency
CL = 30 pF, ID = 75 mA
ta
Reverse-recovery-current rise time
trr
Reverse-recovery time
IF = 100 mA, di/dt = 10 A/µs (2)
See Figure 10
(2)
(3)
6
MAX
ns
50
ns
100
ns
80
ns
15
ns
10
(3)
,
UNIT
80
(1)
f(SRCK)
(1)
TYP
MHz
100
120
ns
This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin.
Technique should limit TJ − TC to 10°C maximum.
These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
TPIC6C596
www.ti.com
SLIS093D – MARCH 2000 – REVISED MARCH 2015
6.7 Typical Characteristics
1
6
VCC = 5 V
TC = −40C° to 125°C
ICC − Supply Current − mA
5
0.1
3
2
1
0.01
0.1
rDS(on) − Drain-to-Source On-State Resistance − Ω
4
0
1
10
0.1
1
10
100
tav − Time Duration of Avalanche − ms
f − Frequency − MHz
Figure 1. Peak Avalanche Current
vs Time Duration of Avalanche
Figure 2. Supply Current vs Frequency
30
VCC = 5 V
See Note A
25
TC = 125°C
20
15
10
TC = 25°C
5
TC = − 40°C
0
50
70
90
110
130
150
170
190
210
250
rDS(on) − Static Drain-to-Source On-State Resistance − Ω
IAS − Peak Avalanche Current − A
TC = 25°C
12
ID = 50 mA
See Note A
TC = 125°C
10
8
TC = 25°C
6
4
TC = − 40°C
2
0
4.0
4.5
ID − Drain Current − mA
5.0
5.5
6.0
6.5
7.0
VCC − Logic Supply Voltage − V
Technique should limit TJ − TC to 10°C maximum.
140
ID = 75 mA
See Note A
tr
Switching Time − ns
120
100
tf
80
tPLH
60
tPHL
40
20
0
−50
−25
0
25
50
75
100
125
TC − Case Temperature − °C
Figure 4. Static Drain-to-Source ON-State Resistance
vs Logic Supply Voltage
ID − Maximum Continuous Drain Current of Each Output − A
Figure 3. Drain-to-Source ON-State Resistance
vs Drain Current
0.25
VCC = 5 V
0.20
0.15
TC = 25°C
0.10
TC = 100°C
TC = 125°C
0.05
0.00
1
2
3
4
5
6
7
8
N − Number of Outputs Conducting Simultaneously
Technique should limit TJ − TC to 10°C maximum
Figure 5. Switching Time vs Case Temperature
Figure 6. Maximum Continuous Drain Current of
Each Output vs Number of Outputs Conducting
Simultaneously
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
7
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
ID − Maximum Peak Drain Current of Each Output − A
Typical Characteristics (continued)
0.30
d = 10%
0.25
d = 20%
0.20
d = 50%
0.15
d = 80%
0.10
VCC = 5 V
TC = 25°C
d = tw/tperiod
= 1 ms/tperiod
0.05
0.00
1
2
3
4
5
6
7
8
N − Number of Outputs Conducting Simultaneously
Figure 7. Maximum Peak Drain Current of
Each Output vs Number of Outputs Conducting Simultaneously
8
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
TPIC6C596
www.ti.com
SLIS093D – MARCH 2000 – REVISED MARCH 2015
7 Parameter Measurement Information
5V
15 V
7
1
7
15
Word
Generator
(see Note A)
2
10
8
CLR
DUT
DRAIN
SER IN
5
4
3
2
1
0
3 −6,
11 −14
Output
CL = 30 pF
(see Note B)
RCK
G
5V
G
0V
5V
SER IN
0V
5V
RCK
0V
5V
CLR
0V
GND
16
5V
0V
ID
VCC
RL = 200 Ω
SRCK
6
SRCK
15 V
DRAIN1
0.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 8. Resistive-Load Test Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
9
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
Parameter Measurement Information (continued)
5V
G
50%
50%
0V
5V
15 V
tPLH
1
7
15
Word
Generator
(see Note A)
2
10
8
CLR
SRCK
Output
VCC
ID
3 −6,
11 −14
DUT
24 V
90%
10%
10%
RL = 200 Ω
tr
Output
0.5 V
tf
SWITCHING TIMES
5V
CL = 30 pF
(see Note B)
RCK
G
90%
DRAIN
SER IN
tPHL
50%
SRCK
0V
GND
tsu
th
16
5V
SER IN
50%
50%
TEST CIRCUIT
0V
tw
INPUT SETUP AND HOLD WAVEFORMS
SRCK
50%
50%
tpd
SER OUT
50%
tpd
50%
SER OUT PROPAGATION DELAY WAVEFORM
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 9. Test Circuit, Switching Times, and Voltage Waveforms
10
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
TPIC6C596
www.ti.com
SLIS093D – MARCH 2000 – REVISED MARCH 2015
Parameter Measurement Information (continued)
TP K
DRAIN
Circuit
Under
Test
0.1 A
2500 µF
250 V
di/dt = 10 A/µs
+
L = 0.85 mH
IF
(see Note A)
IF
15 V
−
0
TP A
25% of IRM
t2
t1
t3
Driver
IRM
RG
VGG
(see Note B)
ta
50 Ω
trr
TEST CIRCUIT
CURRENT WAVEFORM
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The VGG amplitude and RG are adjusted for di/dt = 10 A/µs. A V GG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.
Figure 10. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
5V
15 V
tw
1
7
CLR
VCC
30 Ω
Word
Generator
(see Note A)
2
10
8
DUT
G
See Note B
1.5 H
SER IN
3 −6,
11 −14
DRAIN
RCK
5V
Input
ID
15 SRCK
GND
0V
IAS = 200 mA
ID
VDS
V(BR)DSX = 33 V
MIN
VDS
16
tav
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
VOLTAGE AND CURRENT WAVEFORMS
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 200 mA.
Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ.
Figure 11. Single-Pulse Avalanche Energy Test Circuit and Waveforms
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
11
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
8 Detailed Description
8.1 Overview
The TPIC6C596 device is a monolithic, medium-voltage, low-current 8-bit shift register designed to drive
relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for
inductive transient protection, so it can also drive relays, solenoids, and other low-current or medium-voltage
loads.
8.2 Functional Block Diagram
G 8
10
RCK
7
CLR
3
D
SRCK
SER IN
15
C1
D
C2
CLR
CLR
4
2
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
D
C2
CLR
C1
CLR
5
6
11
12
13
14
16
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
GND
D
C1
9
CLR
SER OUT
Figure 12. Logic Diagram (Positive Logic)
12
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
TPIC6C596
www.ti.com
SLIS093D – MARCH 2000 – REVISED MARCH 2015
8.3 Feature Description
8.3.1 Serial-In Interface
The TPIC6C596 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock
(SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when
shift register clear (CLR) is high.
8.3.2 Clear Register
A logical low on CLR clears all registers in the device. TI suggests clearing the device during power up or
initialization.
8.3.3 Output Control
Holding the output enable (G) high holds all data in the output buffers low, and all drain outputs are off. Holding
G low makes data from the storage register transparent to the output buffers. When data in the output buffers is
low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable of sinkcurrent. This pin can also be used for global PWM dimming.
8.4 Device Functional Modes
8.4.1 Operation With V(VIN) < 4.5 V (Minimum V(VIN))
This device works normally during 4.5 V ≤ V(VIN) ≤ 5.5 V, when operation voltage is lower than 4.5 V. The
behavior of device can't be ensured, including communication interface and current capability.
8.4.2 Operating With 5.5 V < V(VIN) < 6 V
This device works normally during this voltage range, but reliability issues may occurs while the device works for
a long time in this voltage range.
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
13
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPIC6C596 device is a serial-in parallel-out, Power+LogicE 8-bit shift register with low-side switch DMOS
outputs rating of a 100 mA per channel. The device is designed to drive resistive and inductive loads and is
particularly well-suited as an interface between a microcontroller and LEDs or lamps. The TPIC6C596 device is
an enhancement of the TPIC6C595 device, where the shift register serial output (SER OUT) is clocked on the
falling edge of the serial clock to provide additional hold-time in applications where several devices are
cascaded.
9.1.1 Cascaded Application
The serial output (SEROUT) clocks out of the device on the falling edge of SRCK to provide additional hold time
for cascaded applications. Connect the device (SEROUT) pin to the next device (SERIN) for daisy Chain. This
provides improved performance for applications where clock signals may be skewed, devices are not located
near one another, or the system must tolerate electromagnetic interference.
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
VCC
DRAIN
33 V
Input
25 V
20 V
12 V
GND
GND
Figure 13. Schematic of Inputs and Outputs
9.2 Typical Application
The typical application of TPIC6C596 device is an automotive cluster driver. In this example, two TPIC6C596
power shift registers are cascaded and used to turn on LEDs in the cluster panel. In this case, the LED must be
updated after all 16 bits of data have been loaded into the serial shift registers. The MCU outputs the data to the
serial input (SER IN) while clocking the shift register clock (SRCK). After the 16th clock, a pulse to the register
clock (RCK) transfers the data to the storage registers. If output enable (G) is low, then the LEDs are turned on
corresponding to the status word with ones being on and zeros off. With this simple scheme, MCU can use the
SPI interface to turn on 16 LEDs using only two ICs as illustrated in Figure 14.
14
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
TPIC6C596
www.ti.com
SLIS093D – MARCH 2000 – REVISED MARCH 2015
Typical Application (continued)
Vbattery
Vbattery
5V
5V
R1
R2
R3
R4
R5
R6
R7
R8
0.1uF
10k
R9
R9
R9
R9
R9
R9
R9
D9
D10
D11
D12
D13
D14
D15
D16
10k
VCC
VCC
TPIC6C596
TPIC6C596
DRAIN0
SRCK
D1
D2
D3
D4
D5
D6
D7
DRAIN0
D8
DRAIN1
RCK
MCU
R9
0.1uF
DRQIN2
SRCK
DRAIN1
RCK
DRQIN2
SER IN
DRAIN3
SER IN
DRAIN3
CLR
DRAIN4
CLR
DRAIN4
G
DRAIN5
G
DRAIN5
DRAIN6
DRAIN6
DRAIN7
DRAIN7
SER OUT
SER OUT
GND
TO SERIAL INPUT OF THE NEXT
STAGE
GND
Figure 14. Typical Application Schematic
9.2.1 Design Requirements
Table 1 lists the design parameters for Figure 14.
Table 1. Design Parameters
DESIGN PARAMTER
EXAMPLE VALUE
Vsupply
9 to16 V
V (D1), V (D2), V (D3), V (D4), V (D5), V (D6),V (D7), V (D8)
2V
V (D9), V (D10),V (D11), V (D12), V (D13), V (D14),V (D15), V
(D16)
3.3 V
I (D1), I (D2), I (D3), I (D4), I (D5), I (D6),I (D7), I (D8)
20 mA when Vbattery is 12 V
I (D9), I (D10), I (D11), I (D12), I (D13), I (D14),I (D15), I (D16)
30 mA when Vbattery is 12 V
9.2.2 Detailed Design Procedure
To begin the design process, the designer must decide on a few parameters. The designer must know the
following:
• Vsupply: LED supply is connected directly to the car battery, which has a voltage range from 9 V to 16 V, or
fixed voltage. This application connects to the battery directly.
• V(Dx): LED forward voltage
• I(Dx): LED setting current when battery is 12 V.
9.2.2.1 R1, R2, R3, R4, R5, R6, R7, R8 R1 = R2 = R3 = R4 = R5 = R6 = R7 = R8 =
(Vsupply – V (Dx)) / I (Dx) = (12 V – 2 V) / 0.02 A = 500 Ω
When Vsupply is 9 V, I (D1) = I (D2 ) = I (D3) = I (D4) = I (D5) = I (D6) = I (D7) = I (D8) = (Vsupply – V(Dx) ) / Rx
= 14 mA.
When Vsupply is 16 V, I (D9) = I (D10) = I (D11) = I (D12) = I (D13) = I (D14) = I (D15) = I (D16) =(Vsupply –
V(Dx)) / Rx= 43.8 mA.
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
15
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
NOTE
If designers can accept the current variation when battery voltage is changing, they can
connect the device directly to the battery. If a designer need the less variation of current,
they need to use the voltage regulator as supply voltage of LED, or change to constant
current LED driver directly
9.2.3 Application Curve
Figure 15. CH1 is SRCK, CH2 is RCK, CH3 is SER IN and
CH4 is D1 Current
16
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
TPIC6C596
www.ti.com
SLIS093D – MARCH 2000 – REVISED MARCH 2015
10 Power Supply Recommendations
The TPIC6C596 device is designed to operate from an input voltage supply range from 4.5 V and 5.5 V. This
input supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin.
11 Layout
11.1 Layout Guidelines
There is no special layout requirement for the digital signal pin; the only requirement is placing the ceramic
bypass capacitors near the corresponding pin. Because the TPIC6C596 device does not have a thermal
shutdown protection function, to prevent thermal damage, TJ must be less than 150°C. If the total sink current is
high, the power dissipation might be large. The devices are currently not available in the thermal pad package,
so good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability of the
device.
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board, because the major
heat-flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when the design does not include heat sinks attached to the PCB on the other side of the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
17
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
11.2 Layout Example
Power Ground
both in TOP and
Bottom
Vcc
GND
TPIC6C596
VIA to Ground
SRCK
SER IN
DRAIN0
DRAIN7
DRAIN1
DRAIN6
DRAIN2
DRAIN5
DRAIN3
DRAIN4
CLR
RCK
SER OUT
G
Figure 16. Recommended Layout Example
18
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
TPIC6C596
www.ti.com
SLIS093D – MARCH 2000 – REVISED MARCH 2015
11.3 Thermal Considerations
RθJA − Normalized Junction-to-Ambient Thermal Resistance − °C/W
10
DC Conditions
1
d = 0.5
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
Single Pulse
0.001
tc
tw
ID
0
0.0001
0.0001
0.001
0.01
0.1
tw − Pulse Duration − s
1
10
† Device mounted on FR4 printed-circuit board with no heat sink
NOTES: ZθA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 17. D Package†, Normalized Junction-to-Ambient Thermal Resistance vs Pulse Duration
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
19
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015
www.ti.com
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6C596
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPIC6C596D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TPIC6C596
TPIC6C596DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6C596
TPIC6C596DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TPIC6C596
TPIC6C596DRG4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6C596
TPIC6C596DRQ1
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6C596Q
TPIC6C596N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TPIC6C596
TPIC6C596PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6C596PW
TPIC6C596PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6C596PW
TPIC6C596PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
6C596PW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
