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TPIC7218-Q1
SLDS182A – AUGUST 2010 – REVISED JULY 2015
TPIC7218-Q1 Power Controller and Sensor ASIC For Braking Applications
1 Device Overview
1.1
Features
1
• Qualified for Automotive Applications
• AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4
• PWM Low-Side Drivers
– 4 PWM Low-Side Driver Outputs
– Current Limitation
– Thermal Protection: TJ = 185°C (Minimum)
– Open-Load Detection
– Energy Capability: 30 mJ at TJ = 150°C
– Clamp Voltage: 40 V
– Low RDSon: 0.3 Ω (Maximum) at TJ = 150°C
• Digital Low-Side Drivers
– 4 Digital Low-Side Driver Outputs
– Current Limitation
– Thermal Protection: TJ = 185°C (Minimum)
– Open-Load Detection
– Energy Capability: 50 mJ at TJ = 150°C
– Clamp Voltage: 40 V
– Low RDSon: 0.2 Ω (Maximum) at TJ = 150°C
• Dual High-Side Power Drivers
– Direct Input Control
– PWM Capability
– Load Dump (overvoltage) Detection
– Programmable overcurrent detection
– Load Leakage Detection
– Programmable short-circuit Protection
– Fault detection over SPI
1.2
•
Applications
Anti-lock Braking Systems (ABS)
1.3
• Wheel-Speed Sensor Interface
– Compatible with Intelligent and Active WheelSpeed Sensors
– 4 High-Side Switches With Short-Circuit
Protection
– 4 Low-Side Switches With Short-Circuit
Protection
– 2 High Voltage Low-Side Output Drivers
– 4 Digital Outputs to Indicate the Speed
– Integrated Data Decoder for Intelligent WheelSpeed Sensors
• Open-Drain Warning Lamp Drivers
– 2 High Voltage Drivers
– Thermal Protection With Hysteresis
– Current Limitation
– TJ = 185°C (Minimum)
– RDSon: 4 Ω at TJ = 150°C
– Clamp Voltage: 40 V
• Other Features
– K-LINE Transceiver
– 3.3-V or 5-V Compatible Digital IO
– Internal 3.3-V Regulator
– Internal Charge Pump
– 1 Low-Voltage Open-Drain Warning Lamp
Driver
– Full Duplex SPI Interface
– Watchdog Input With Open-Drain Fault
Reporting for Safety
– Pb-Free ASIC
– Compliant With CISPR 25 NB Class 5 for
Conducted and Radiated Emissions
•
Electronic Stability Control Systems (ESC)
Description
The TPIC7218-Q1 device integrates in single package several functions needed in ABS and ESC
electronic control units (ECU). This integration coupled with the minimization of the external components
saves valuable ECU board space.
1
The TPIC7218-Q1 device is an antilock braking controller capable of directly driving eight solenoid valves
with internal high-current low-side drivers. Low-side drivers configured for digital control do not require
external voltage clamps. The TPIC7218-Q1 device has gate drive capability for two high-side N-Channel
MOSFETs that can be used to drive a pump motor and power to all solenoids. The TPIC7218-Q1 device
provides a fault-tolerant interface for both Intelligent and Active wheel-speed sensors to an external
microprocessor. The TPIC7218-Q1 device can be used with either 3.3- or 5-V microprocessors and uses
a standard SPI (Serial-Peripheral Interface).
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC7218-Q1
SLDS182A – AUGUST 2010 – REVISED JULY 2015
www.ti.com
The TPIC7218-Q1 device has two internal open-drain warning lamp drivers that can be pulled up to
battery voltage, as well as one low-voltage driver. An internal state machine monitors a watchdog input
and reports faults on a warning-lamp pin and SPI register. A K-Line transceiver is also included. A
multitude of safety and fault monitoring functionality supervise both system and TPIC7218-Q1 circuits.
Faults must be polled and reset over SPI. The TPIC7218-Q1 device is designed for use in harsh
automotive environments, capable of withstanding high operating temperatures and electrically noisy
signals and power. Short-to-ground, short-to-battery, and open-load conditions are tolerated and
monitored. The TPIC7218-Q1 device also exhibits outstanding Electro-Magnetic Compatibility (EMC)
performance.
Device Information (1)
PART NUMBER
TPIC7218-Q1
(1)
2
PACKAGE
HTQFP (80)
BODY SIZE (NOM)
12.00 mm × 12.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.
Device Overview
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1.4
SLDS182A – AUGUST 2010 – REVISED JULY 2015
Functional Block Diagram
Figure 1-1. Functional Block Diagram
Device Overview
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TPIC7218-Q1
SLDS182A – AUGUST 2010 – REVISED JULY 2015
www.ti.com
Table of Contents
1
Device Overview ......................................... 1
4.23
PWM Low-Side Driver Switching Characteristics ... 15
Features .............................................. 1
4.24
K-Line Switching Characteristics .................... 15
.......................................... 1
1.3
Description ............................................ 1
1.4
Functional Block Diagram ............................ 3
Revision History ......................................... 4
Pin Configuration and Functions ..................... 5
Specifications ............................................ 8
4.1
Absolute Maximum Ratings .......................... 8
4.2
ESD Ratings .......................................... 9
4.3
Recommended Operating Conditions ................ 9
4.4
Thermal Information .................................. 9
4.5
Input Port Electrical Characteristics ................. 10
4.6
PWM Low-Side Driver Electrical Characteristics ... 10
4.7
Digital Low-Side Driver Electrical Characteristics ... 10
4.8
High-Side Driver Electrical Characteristics.......... 11
4.9
K-Line Electrical Characteristics .................... 11
4.10 Warning Lamp Electrical Characteristics............ 11
4.11 Power Supply Electrical Characteristics ............ 12
4.12 SPI Electrical Characteristics ....................... 12
4.13 WL_LS Low-Side Switch Output Characteristics ... 12
4.14 Wheel-Speed High-Side Driver Characteristics ..... 12
4.15 Wheel-Speed Low-Side Driver Characteristics ..... 13
4.16 Wheel-Speed Output Characteristics ............... 13
4.17 RST Output Characteristics ......................... 13
4.18 SPI Timing Electrical Characteristics ............... 13
4.19 Power Supply Switching Characteristics ............ 14
4.20 Wheel-Speed Counter Switching Characteristics ... 14
4.21 HS Driver Switching Characteristics ................ 14
4.22 Digital Low-Side Driver Switching Characteristics .. 15
4.25
Warning Lamp Switching Characteristics ........... 15
4.26
Watchdog Switching Characteristics ................ 16
4.27
4.28
Wheel Speed Interface Switching Characteristics .. 16
Wheel-Speed High-Side Driver Switching
Characteristics....................................... 16
4.29
Wheel-Speed Output Switching Characteristics .... 16
4.30
Typical Characteristics .............................. 18
1.1
1.2
2
3
4
Applications
5
6
7
8
9
Detailed Description ................................... 19
...........................................
5.1
Overview
5.2
Functional Block Diagram ........................... 20
.................................
...........................
5.5
Programming ........................................
5.6
Register Maps .......................................
Application and Implementation ....................
6.1
Application Information ..............................
6.2
Typical Application ..................................
Power Supply Recommendations ..................
Layout ....................................................
8.1
Layout Guidelines ..................................
8.2
Layout Example .....................................
Device and Documentation Support ...............
9.1
Documentation Support .............................
9.2
Community Resources ..............................
9.3
Trademarks..........................................
9.4
Electrostatic Discharge Caution .....................
9.5
Glossary .............................................
19
5.3
Feature Description
20
5.4
Device Functional Modes
39
39
41
47
47
47
50
50
50
52
56
56
56
56
57
57
10 Mechanical, Packaging, and Orderable
Information .............................................. 57
2 Revision History
Changes from Original (August 2010) to Revision A
•
4
Released full version of the data sheet
Page
...........................................................................................
Revision History
1
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SLDS182A – AUGUST 2010 – REVISED JULY 2015
3 Pin Configuration and Functions
PGND5
PGND5
DPR
SPR
64
63
62
61
Q5
Q5
66
67
65
Q6
Q6
68
PGND6
PGND6
69
71
70
Q7
PGND7
PGND7
74
73
72
Q8
Q8
76
Q7
PGND8
77
75
WSSOUT2
WSSOUT1
78
WSP1
80
79
PFP Package
80-Pin HTQFP With PowerPAD™
Top View
WSP2
1
60
CHP
WSP3
2
59
VBAT
WSP4
3
58
GPR
WSSOUT3
4
57
GMR
WSSOUT4
5
56
SMR
GND
6
55
DMR
VCC3
7
54
ISOK
REF
VDD
WDIN
8
53
9
52
10
51
WLQ2
WLQ1
WLG2
11
50
WLG1
12
49
KRX
VREF
13
48
KTX
WSS4
14
47
HSPC
WSS3
15
46
TEST
WSS2
16
45
HSMC
WSS1
17
44
CSN
nRST
WL_LS
36
40
35
Q1
Q1
39
34
Q2
WSSQ1
33
Q2
WSSQ2
32
PGND2
37
31
PGND2
38
30
Q3
PGND3
PGND3
VIO
27
28
Q3
PGND1
26
Q4
29
24
25
Q4
SO
PGND4
41
23
20
CNT_CLR
SI
WSLS2
21
SCLK
42
22
43
WSLS1
18
19
CNT_EN
WSLS4
WSLS3
Pin Functions
PIN
NAME
NO.
I/O
FUNCTION DESCRIPTION
INPUT PIN
PULLUP OR
PULLDOWN
PIN DURING
RESET
CONDITION
VCHP = VBAT +
12 V (typical)
CHP
60
O
External 100-nF capacitor to VBAT for an internal charge
pump
Pullup
CNT_CLR
23
I
Clear bit for the 8-bit digital counter that counts the wheelspeed sensor pulse edges seen in WSSOUTx
Pulldown
CNT_EN
22
I
Enable bit for the 8-bit digital counter that counts the wheelspeed sensor pulse edges seen in WSSOUTx
Pulldown
CSN
44
I
SPI chip select active low pin
Pullup
Pin Configuration and Functions
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Pin Functions (continued)
PIN
NAME
NO.
I/O
FUNCTION DESCRIPTION
INPUT PIN
PULLUP OR
PULLDOWN
PIN DURING
RESET
CONDITION
DMR
55
I
Drain pin for master relay (MR) FET
Pulldown
Externally supplied
voltage (VBAT)
DPR
62
I
Drain pin for PR (pump motor relay) FET
Pulldown
Externally supplied
voltage (VBAT)
GMR
57
O
Gate pin for master relay (MR) FET
GND
6
Ground
GPR
58
O
Gate pin for PR (pump motor relay) FET
HSMC
45
I
Logic input for MR (master relay) FET
Pulldown
HSPC
47
In
Logic input for PR (pump motor relay) FET
Pulldown
ISOK
54
I/O
K-line serial data transmit output to diagnosis tester and Kline serial data receive input from diagnosis tester
KRx
49
O
K-line serial data input to the microcontroller
KTx
48
I
K-line serial data output from the microcontroller
nRST
11
I/O
PGND1
37
Ground
Power ground pin for low-side valve driver 1
Ground
Power ground pin for low-side valve driver 2
Ground
Power ground pin for low-side valve driver 3
Ground
Power ground pin for low-side valve driver 4
Ground
Power ground pin for low-side valve driver 5
Ground
Power ground pin for low-side valve driver 6
Ground
Power ground pin for low-side valve driver 7
Ground
Power ground pin for low-side valve driver 8
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
31
32
29
30
24
63
64
69
70
71
72
77
35
36
33
34
27
28
25
26
65
66
67
68
73
74
75
76
Low
Ground
Low
High-Z
High
Pullup
Reset signal that is used to either indicate an internal reset
event or to induce an external reset
Pulldown
See Table 5-1
O
Drain pin of the low-side valve driver 1
High-Z
O
Drain pin of the low-side valve driver 2
High-Z
O
Drain pin of the low-side valve driver 3
High-Z
O
Drain pin of the low-side valve driver 4
High-Z
O
Drain pin of the low-side valve driver 5
High-Z
O
Drain pin of the low-side valve driver 6
High-Z
O
Drain pin of the low-side valve driver 7
High-Z
O
Drain pin of the low-side valve driver 8
High-Z
REF
8
I
Reference pin used to generate the internal bias currents.
An external load of 10 kΩ is needed.
Pulldown
SCLK
43
I
SPI clock pin
Pulldown
6
High-Z
Pin Configuration and Functions
REF = 1.25 V
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SLDS182A – AUGUST 2010 – REVISED JULY 2015
Pin Functions (continued)
PIN
NAME
NO.
I/O
FUNCTION DESCRIPTION
SI
42
I
SPI input pin
SMR
56
O
Source pin for master relay (MR) FET
SO
41
O
SPI output pin
SPR
61
I/O
Source pin for PR (pump motor relay) FET
INPUT PIN
PULLUP OR
PULLDOWN
PIN DURING
RESET
CONDITION
Pulldown
Low
High-Z
Internal test pin. For any application, this is externally pulled
to ground with a 1-kΩ resistor.
Low
TEST
46
I
Pulldown
VBAT
59
Power
Battery power supply (after reverse battery)
VCC3
7
Power
Internal regulator for digital logic. Connect this pin only to a
capacitor for regulator stability.
VDD
9
Power
5-V external power supply
VIO
38
Power
3.3-V or 5-V external supply for the I/O buffers
VREF
13
I
Externally supplied voltage reference used to set the current
detection thresholds for the wheel-speed sensor interface
Pulldown
WDIN
10
I
Watchdog timer signal
Pulldown
WLG1
50
I
Logic input for warning lamp driver 1
Pulldown
WLG2
51
I
Logic input for warning lamp driver 2
Pulldown
WLQ1
52
O
Drain pin of low-side warning lamp driver 1
See Table 5-1
WLQ2
53
O
Drain pin of low-side warning lamp driver 2
See Table 5-1
High-Z
VCC3 = 3.3 V
WL_LS
12
O
Low side switch for warning-lamp driver control that
indicates the watchdog status
WSLS1
21
I
Wheel-speed sensor channel 1 low-side switch
High-Z
WSLS2
20
I
Wheel-speed sensor channel 2 low-side switch
High-Z
WSLS3
19
I
Wheel-speed sensor channel 3 low-side switch
High-Z
WSLS4
18
I
Wheel-speed sensor channel 4 low-side switch
High-Z
WSP1
80
O
Supplies VBAT power to wheel-speed sensor channel 2
Low
WSP2
1
O
Supplies VBAT power to wheel-speed sensor channel 2
Low
WSP3
2
O
Supplies VBAT power to wheel-speed sensor channel 3
Low
WSP4
3
O
Supplies VBAT power to wheel-speed sensorchannel 4
WSS1
17
I
Wheel-speed sensor channel 1 signal pin
Pulldown
WSS2
16
I
Wheel-speed sensor channel 2 signal pin
Pulldown
WSS3
15
I
Wheel-speed sensor channel 3 signal pin
Pulldown
WSS4
14
I
Wheel-speed sensor channel 4 signal pin
Pulldown
Low
See Table 5-1
Low
WSSOUT1
78
O
Supplies processed wheel-speed pulse signal output to the
microcontroller of channel 1 in a digital voltage form
WSSOUT2
79
O
Supplies to the microcontroller the processed wheel-speed
pulse signal of channel 2 in a digital voltage form
Low
WSSOUT3
4
O
Supplies to the microcontroller the processed wheel-speed
pulse signal of channel 3 in a digital voltage form
Low
WSSOUT4
5
O
Supplies to the microcontroller the processed wheel-speed
pulse signal of channel 4 in a digital voltage form
Low
WSSQ1
40
O
Drain pin for wheel-speed channel 1 output driver. Used to
pass WSSOUT1 information to a high-voltage capable node
High-Z
WSSQ2
39
O
Drain pin for wheel-speed channel 2 output driver. Used to
pass WSSOUT2 information to a high-voltage capable node
High-Z
PAD
Ground
Thermal power ground pin for low-side drivers. Connect to
PGNDx plane.
Pin Configuration and Functions
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4 Specifications
4.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC
Input voltage, VIN
MIN
MAX
UNIT
VDD, VIO
–0.3
6.5
V
WDin, CNT_EN, CNT_CLR, SI, SCLK, CSN, KRX, KTX,
WL_LS, WLGx, VIO, HSMC, HSPC
–0.3
6.5
V
WSSQx, WSSx, WSLSx
–0.3
40
V
CHP
–0.3
55
V
DMR,DPR
–1
40
V
–0.3
40
V
–1
40
V
–1
40
V
ISOK
–0.3
40
V
Qx, WLQx, WSSQx
–0.3
40
V
SO
–0.3
(VCC + 0.3 )
V
nRST , WL_LS
–0.3
6.5
V
GMR, GPR
–1
55
V
REF voltage, VREF
REF, VREF
–0.3
6.5
V
Ground voltage, VGND
PGNDx, GND
–0.3
0.3
V
Q1, 2, 3, 4
0
5
A
Q5, 6, 7, 8,
0
3.5
A
WLQx
0
100
mA
SMR,SPR, TEST
Load dump
Supply voltage
Transient (2
range, VBAT
ms)
Load dump voltage, VISOK
(2)
Output voltage, VOUT
Continuous
Drain current,
IIN
VBAT
nRST
Negative
Transients
Input current, IIN
±20
mA
Q1, 2, 3, 4 (10 ms)
–5
0
A
Q5, 6, 7, 8, (10 ms)
–5
0
A
WLQx (2 ms)
–5
0
A
WDIN, WLGx, CNT_EN, CNT_CLR, SI, SCLK, CSN, KRX,
KTX, HSMC, HSPC
SPR, SMR
Output current, IOUT
SO
REF current, IREF
Short-circuit current limit, ISC
±20
–10
mA
10
±20
mA
REF
±20
mA
ISOK
1000
mA
Current with 510-Ω sense, IISOK ISOK
–100
113.5
mA
VDD
–20
50
mA
VBAT (including WSSPx current limit thresholds)
–20
620
mA
Supply current, ICC
Repetitive avalanche energy,
EAR_DQ150
(TJ = 150°C)
Q1, 2, 3, 4
50
mJ
Repetitive avalanche energy,
EAR_PQ150
(TJ = 150°C)
Q5, 6, 7, 8
30
mJ
ISOK clamp energy, EClamp
ISOK
20
mJ
Operating virtual-junction temperature, TJ
–40
175
°C
Tstg
–65
150
°C
(1)
(2)
8
Storage temperature range
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This module survives double-battery jump-start conditions in typical application for 10 minutes duration.
Specifications
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4.2
SLDS182A – AUGUST 2010 – REVISED JULY 2015
ESD Ratings
VALUES
Human body model (HBM), per
AEC Q100-002 (1)
Electrostatic
discharge
V(ESD)
Charged device model (CDM),
per AEC Q100-011
(1)
WLQx, Qx, VBAT, ISOK, DMR, SMR,
WSSx, WSLSx, WSPx, WSSQx, DPR,
SPR (to GND)
±4000
Other pins
±2000
Corner pins (WSP2, WSP1, SPR, CHP
SO, WSSQ1, WSLS1, and WSLS2)
±750
Other pins
±500
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
4.3
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VBAT
Supply voltage, battery
VBAT
6
20
V
VDD
Supply voltage
VDD
4.5
5.5
V
VIO_3.3V
Supply voltage I/O 3.3V
VIO is a 3.3-V externally supplied power
2.8
3.6
V
VIO_5V
Supply voltage I/O 5V
VIO is a 5-V externally supplied power
4.5
5.5
V
VIN
Input voltage
WDIN, CNT_EN, CNT_CLR, SI, SCLK, CSN, nRST, HSMC,
HSPC, KTX, WLGx
0
VIO + 0.5
V
VOUT
Output voltage
Qx, WLQx
0
VBAT
V
TA
Operating ambient temperature
–40
125
°C
4.4
Thermal Information
TPIC7218-Q1
THERMAL METRIC
(1)
PFP (HTQFP)
UNIT
80 PINS
RθJA
Junction-to-ambient thermal resistance
27.2
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
8.9
°C/W
Junction-to-board thermal resistance
11.1
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
11
°C/W
Junction-to-case (bottom) thermal resistance
0.3
°C/W
RθJC(bot)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Specifications
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4.5
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Input Port Electrical Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
VIH_3.3V
Input high voltage (3.3-V
compatible)
WDIN, CNT_CLR, CNT_EN, HSMC, HSPC, WLGx, CSN,
SI, SCLK, nRST
VIL_3.3V
Input low voltage (3.3-V
compatible)
WDIN, CNT_CLR, CNT_EN, HSMC, HSPC, WLGx, CSN,
SI, SCLK, nRST
0.8
V
Vhys_3.3V
Input voltage threshold
hysteresis (5-V compatible)
WDIN, CNT_CLR, CNT_EN, HSMC, HSPC, WLGx, CSN,
SI, SCLK, nRST
300
mV
VIH_5V
Input high voltage (5-V
compatible)
WDIN, CNT_CLR, CNT_EN, HSMC, HSPC, WLGx, CSN,
SI, SCLK, nRST
VIL_5V
Input low voltage (5-V
compatible)
WDIN, CNT_CLR, CNT_EN, HSMC, HSPC, WLGx, CSN,
SI, SCLK, nRST
1
Vhys_5V
Input voltage threshold
hysteresis (5-V compatible)
WDIN, CNT_CLR, CNT_EN, HSMC, HSPC, WLGx, CSN,
SI, SCLK, nRST
300
IPD
Pin pulldown current,
with VIN = VDD (max)(5.5 V) to
VIL (min)
WDIN, CNT_CLR, CNT_EN, HSMC, HSPC, WLGx, SI,
SCLK, nRST
Ipu_csn
CSN pullup current
IPD_SMR
SMR pin input current
4.6
2.2
3.5
V
V
V
mV
5
20
μA
–5
μA
0
1
mA
TYP
MAX
–20
–1
PWM Low-Side Driver Electrical Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
Ron_PWMx
Ilim_PWMx
TEST CONDITIONS
On resistance
MIN
150°C junction temperature,
6 V ≤ VBAT ≤ 20 V
0.3
Current limit
5
UNIT
Ω
A
TA = –40°C
5.5
Isink_PWMx
Sink current
Qx between 1 V and 20 V
10
Ileak_PWMx
Drain leakage current
VBAT = 0, VDD = 0
Tsd_PWMx
Thermal shutdown junction temperature
VolvtDIPWMx
Open load comparator threshold voltage
Vcl_PWMx
Active clamp voltage
40
Vbvdss_PWMx
Max BVDSS voltage without active clamp
50
V
Ineg_PWMx
Maximum negative current for 10 ms
–5
A
4.7
A
60
μA
1
μA
185
215
°C
1.84
2.16
V
50
V
Digital Low-Side Driver Electrical Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
Ron_DLSx
TEST CONDITIONS
On resistance
150°C junction temperature,
6 V ≤ VBAT ≤ 20 V
Ilim_DLSx
Current limit
Isink_DLSx
Sink current
Qx output between 1 V and 20 V
Ileak_DLSx
Drain leakage current
VBAT = 0, VDD = 0
Tsd_DLSx
Thermal shutdown junction temperature
Volvt_DLSx
Open load comparator threshold
Vcl_DLSx
Vbvdss_DLSx
Ineg_DLSx
10
MIN
TYP
MAX
0.2
6
UNIT
Ω
A
60
μA
1
μA
185
215
°C
1.84
2.16
V
Active clamp voltage
40
50
V
Max BVDSS voltage without active clamp
50
V
Maximum negative current for 10 ms
–5
A
Specifications
10
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4.8
SLDS182A – AUGUST 2010 – REVISED JULY 2015
High-Side Driver Electrical Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IDMR/IDPR Overcurrent threshold current
MIN
TYP
MAX
UNIT
60
75
90
μA
1.6
2
2.4
V
3
5
7
mA
VSTG
On-state short-to-ground detection
voltage
ILCdet
Leakage current in SMR pin
Ileak_SMR
Leakage current on SMR
0 ≤ SMR ≤ 20 V,
6 V ≤ VBAT ≤ 20 V
135
μA
IDark_DMR
Dark current
0 ≤ DMR ≤ 20 V,
VBAT = 0, VDD ≤ 0
2.5
μA
VFGMR/
VFGPR
Voltage threshold FGMR in GMR pin
and FGPR in GPR pin
1.6
2.4
V
Vgs_clamp
Voltage clamp between GMR-SMR
and GPR-SPR pins
16
20
V
6 V < VBAT < 7 V
VBAT + 5
VBAT + 15
7 V ≤ VBAT < 10 V
VBAT + 7
VBAT + 15
10 V ≤ VBAT < 20 V
VBAT + 10
VBAT + 15
7 V ≤ VBAT < 10 V
VBAT + 7
VBAT + 15
10 V ≤ VBAT < 20 V
VBAT + 10
VBAT + 15
Output on voltage for GMR and GMR
(each are turned on individually)
VON
4.9
2
V
K-Line Electrical Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIL_tx
VIH_tx
Ipu_tx
VOL_rx
VOH_rx
KTX pullup current
Thermal shutdown hysteresis
ISC_iso
VOL_iso
VOH_iso
Ileak_isok
–2
μA
0.2* ×
VDD
V
V
185
215
C
20
30
C
V
ISOK input high voltage threshold
Short-circuit current limit
0.05 ×
VBAT
50
Output low voltage
Output high voltage
Drain leakage current
V
0.4 ×
VBAT
Vhys_iso = VIH_iso – VIL_iso
UNIT
0.7 ×
VDD
0.8 ×
VDD
ISOK input low voltage threshold
Input hysteresis
MAX
V
–40
KRX output high voltage threshold
Vhys_kln
Vhys_iso
TYP
KRX output low voltage threshold
Thermal shutdown temperature
VIH_iso
MIN
0.3 ×
VDD
KTX input high voltage threshold
Tlim
VIL_iso
TEST CONDITIONS
KTX input low voltage threshold
0.7 ×
VBAT
V
0.1 ×
VBAT
V
1000
mA
0.1 ×
VBAT
V
0.95 ×
VBAT
V
VBAT = 0, VDD = 0, ISOK = 12 V
6
μA
4.10 Warning Lamp Electrical Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Ron_WLQx
On resistance
150°C junction temperature
Ilim_WLQx
Current limitation
250
Tsd_WLQx
Thermal shutdown temperature
185
TYP
MAX
4
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Ω
mA
215
Specifications
Copyright © 2010–2015, Texas Instruments Incorporated
UNIT
C
11
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Warning Lamp Electrical Characteristics (continued)
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Thys_WLQx
Thermal shutdown hysteresis
Isink_WLQx
Sink current
WLQx output between 1 V and 20 V
Ileak_WLQx
Drain leakage current
VBAT = 0, VDD = 0
Volvt_WLQx
TYP
MAX
UNIT
20
30
C
10
60
μA
1
μA
Open load comparator threshold voltage
2.3
2.7
V
Vcl_WLQx
Active clamp voltage
40
50
V
Vbvdss_WLQx
Max BVDSS voltage without active clamp
50
V
Ineg_WLQx
Maximum negative current for 2 ms
5
A
4.11 Power Supply Electrical Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVDD
Current consumption on VDD
20
mA
IVBAT
Current consumption on VBAT
10
mA
VurvlVDD
Undervoltage shutdown voltage
4.5
4.625
4.75
VuvrhVDD
Undervoltage reset threshold for microcontroller
4.6
4.725
4.85
VVDD_uvr_hys
Undervoltage recovery hysteresis
50
VrstVDD
Undervoltage reset voltage
VuvVBAT
Undervoltage shutdown
5.2
VovVBAT
Overvoltage shutdown
27
VREF
Band-gap reference voltage
V
V
mV
3
V
5.6
6
V
29
31
V
1.25
V
External reference resistor accuracy (chip
resistor)
RREF = 10 kΩ
1%
External predriver capacitor tolerance
CCHP = 100 nF
20%
External load capacitor for internally used VCC3
regulator
100 pF < CVCC3 < 10 nF
20%
4.12 SPI Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
SO output threshold high voltage
VOL
SO output threshold low voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD –1
V
0.4
V
4.13 WL_LS Low-Side Switch Output Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOL
WL_LS output low voltage
TEST CONDITIONS
MIN
TYP
IOL = 20 mA , WDSTAT = ‘0’
MAX
0.4
UNIT
V
4.14 Wheel-Speed High-Side Driver Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Ron_WSPx
On resistance
150°C junction temperature
Ileak_WSPx
Leakage current
Switch disabled, VBAT = 18 V,
Reverse polarity leakage current
Switch disabled, VBAT open,
VWSPx=18 V
Irvleak_WSPx
Ioc_WSPx
Short to ground current limitation
Vclamp_WSPx
Maximum output voltage
CLOAD_WSPx
Maximum capacitive load
12
MIN
TYP
10
8
Ω
10
μA
μA
150
12
UNIT
30
100
50
Specifications
MAX
mA
15
V
10
nF
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4.15 Wheel-Speed Low-Side Driver Characteristics
VBAT = 6 V to 20 V, VDD = 4.85 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
Ron_WSLSx
Ileak_WSLSx
Ileak_WSSx
TEST CONDITIONS
10
Ω
Switch disabled,
VBAT = 18 V,VWSLSx = 18V
200
μA
Leakage current
Switch disabled,
VBAT = 18 V,VWSLSx = 18V
200
μA
3.3
V
V
100% threshold detection VREF / RLOAD (Intelligent
Sensor)
2
1
50% threshold detection VREF / RLOAD (Intelligent
Sensor)
100% threshold detection VREF / RLOAD (Active
Sensor)
25% threshold detection VREF / RLOAD (Intelligent
Sensor)VWSSX – VWSLSX
VWSSX – VWSLSX
11.25% threshold detection VREF / RLOAD (Intelligent
Sensor)
VWSSX – VWSLSX
VWSSX – VWSLSX
22.5% threshold detection VREF / RLOAD (Active
Sensor)
VTHRESH2 = VTHRESH3 = VTHRESH4 = 5 kHz,
VTHRESH1= Measured
–10%
1 × VREF
10%
–10%
1 × VREF
10%
–10%
0.5 × VREF
10%
–10%
0.25 × VREF
10%
–10%
0.5 × VREF
10%
–20%
0.1125 ×
VREF
20%
–20%
0.225 × VREF
20%
VWSSX – VWSLSX
50% threshold detection VREF / RLOAD(Active Sensor)
VWSSthresh
UNIT
150°C junction temperature
VTHRESH4
VTHRESH1
MAX
Leakage current
Reference voltage used to set WSS threshold
detection
VTHRESH2
TYP
On resistance
VREF
VTHRESH3
MIN
V
3 WSS channels switching at
5 kHz
V
V
40
dB
4.16 Wheel-Speed Output Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Ron_WSSQx
On resistance
Ilim_WSSQx
Current limitation
Ileak_WSSQx
Drain leakage current
Volvt_WSSQx
Open load/Short to ground comparator threshold
voltage
Cload_WSSQx
Capacitive Load (Inductive load is not supported)
MIN
150°C junction temperature
TYP
5
MAX
15
50
UNIT
Ω
mA
VWSSQx = 13.5 V
1.84
2
20
μA
2.16
V
22
nF
4.17 RST Output Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOL
RST output low voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOL = 1.6 mA
0.4
V
1 V < VDD < VurvlVDD, IOL = VDD/10 kΩ
0.4
V
4.18 SPI Timing Electrical Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted) (see Figure 4-1)
MIN
4
NOM
MAX
UNIT
8
MHz
fSPI
SPI operation frequency
tSCLK
SCLK clock period
125
ns
T(WH)
SCLK clock high time
62.5
ns
T(WL)
SCLK clock low time
62.5
ns
tSU(lead)
Setup time from falling edge of CSN to rising edge of SCLK
62.5
ns
tSU(lag)
Setup time from falling edge of SCLK to rising edge of CSN
62.5
ns
tpd(SDOEN)
Propagation delay from falling edge of CSN to SO valid
50
Specifications
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SPI Timing Electrical Characteristics (continued)
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted) (see Figure 4-1)
MIN
NOM
MAX
UNIT
tpd(SDODIS)
Propagation delay from rising edge of CSN to SO Hi-Z state
50
ns
tpd(valid)
Propagation delay from rising edge SCLK to 0.2 V1 < SO < 0.8 V1,
SO
CL = 200 pF
50
ns
4.19 Power Supply Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5
µs
53
76.5
100
ms
tRST
Reset response time
trst_delay
Delay time for reset from low to high
(minimum reset hight)
tVovVBAT
Overvoltage blanking time
280
400
520
µs
tVuvVBAT
Undervoltage blanking time
280
400
520
µs
4.20 Wheel-Speed Counter Switching Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tcnt_clr
CNT_CLR deglitcher duration
4.2
7.8
μs
tcnt_en
CNT_EN deglitcher duration
4.2
7.8
μs
4.21
HS Driver Switching Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tFovdet
Overvoltage detection time
280
400
520
µs
tGPRact
Overvoltage activation time
320
460
600
ms
tOCdet
Overcurrent detection time
560
800 1040
µs
tSTG
Short to ground detection
time
70
100
130
µs
tHSDUVBAT
HSD deglitcher time for
VBAT undervoltage
1.3
2.5
µs
Comparator deglitcher time
4.2
7.8
µs
tLCdet
Leakage current detection
time in SMR pin
140
260
µs
tDark_DMR
Time to reach dark current
300
µs
tSTGMR/
tSTGPR
Turnon masking time (1)
8
ms
tON1
Turnon time
tC1deg
tC2deg
tON2_P
tON2_S
(1)
14
Turnon time
Turnon time
After VBAT = 0 V and VDD = 0
5
GMR = 8 nF
GPR = 16 nF,
GMR,
GPR turn ON
together
GPR = 16 nF,
GPR turnon only
200
–6 V < VBAT < 7 V, GPR > VBAT + 4
0.8
–7 V ≤ VBAT < 10 V, GPR > VBAT + 6
1.3
–10 V ≤ VBAT < 20 V, GPR > VBAT + 9
1.5
–6 V < VBAT < 7 V, GPR > VBAT + 4
ms
2
–7 V ≤ VBAT < 10 V, GPR > VBAT + 6
2.8
–10 V ≤ VBAT < 20 V, GPR > VBAT + 9
3.3
–6 V < VBAT < 7 V, GPR > VBAT + 4
1.1
–7 V ≤ VBAT < 10 V, GPR > VBAT + 6
1.5
–10 V ≤ VBAT < 20 V, GPR > VBAT + 9
1.8
ms
ms
This deglitcher applies only during the turnon time of GMR/GPR pins. During this masking time, no overcurrent conditions are reported.
Specifications
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4.22
SLDS182A – AUGUST 2010 – REVISED JULY 2015
Digital Low-Side Driver Switching Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tosoff_DLSx
Open load comparator deglitcher
tr/tf_DLSx
Rise time/fall time
From 10% to 90%
Turnon/turnoff delay time
From CSN going high to digital LSD
turning off or turning on
td_on_DLSx
td_off_DLSx
MIN
TYP
MAX
UNIT
140
200
260
μs
50
μs
70
μs
10
toff_blank_DLSx
Blank time before output shutdown in
current limitation
140
200
260
μs
toff_tmp_DLSx
Blank time before output shutdown in
overtemperature
140
200
260
μs
4.23 PWM Low-Side Driver Switching Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tosoff_PWMx
Open load comparator deglitcher time
tr/tf_PWMx
Rise time/fall time
From 10% to 90%
Turnon delay time
From CSN going high to PWM LSD
turning off
Turnoff delay time
From CSN going high to PWM LSD
turning off
td_on_PWMx
td_off_PWMx
toff_blank_PWMx
Blank time before output shutdown in
case of current limitation
toff_tmp_PWMx
Blank time before output shutdown
during overtemperature
4.24
MIN
TYP
MAX
UNIT
140
200
260
μs
500
ns
10
μs
2.25
μs
30
5
6
7
μs
140
200
260
μs
MAX
UNIT
100
kHz
K-Line Switching Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
ft_rx ft_tx ft_iso
tfall_tx_iso
trise_tx_iso
tpd_tx_iso
TEST CONDITIONS
TYP
KRX, KTX, ISOK,
RISO = 510 Ω, CISO = 1.3 nF
Fall time (20% to 80% of ISOK )
RISO = 510 Ω to VBAT,
CISO = 10 nF to GND
2
μs
Rise time (80% to 20% of ISOK)
RISO = 510 Ω to VBAT,
CISO = 10 nF to GND
15
μs
ISOK propagation delay
toff_iso_rx
MIN
Transmission frequency
50
High to low,
RISO = 510 Ω, CISO = 10 nF
6
Low to high,
RISO = 510 Ω, CISO = 10 nF
6
Turnoff propagation delay time
RISO = 510 Ω, CISO = 10 nF
Turnon propagation delay time
RISO = 510 Ω, CISO = 10 nF
μs
toff_tx_iso
ton_iso_rx
ton_tx_iso
Blank time for overtemperature (1)
toff_kln
ton_kln
(1)
μs
4
μs
140
200
260
μs
15
20
25
μs
Cumulative blank time before
shutdown for overcurrent
toff_isok
17
toff_kln is the deglitcher time for K-Line to turnoff, and ton_kln is the deglitcher time for K-Line to turn on from shutdown.
4.25
Warning Lamp Switching Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
tosoff_WLQx
TEST CONDITIONS
Open-load comparator deglitcher time
MIN
TYP
MAX
UNIT
140
200
260
μs
Specifications
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Warning Lamp Switching Characteristics (continued)
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
tr_WLQx
TEST CONDITIONS
Rise time/fall time
tf_WLQx
td_on_WLQx
MIN
TYP
MAX
From 10% to 90%
Turnon/turnoff delay time
td_off_WLQx
toff_blank_WLQx
toff_tmp_WLQx
ton_tmp_WLQx
4.26
Blank time for overcurrent /short battery
sensing
Blank time in case of overtemperature
UNIT
60
μs
25
μs
8
10
12
μs
140
200
260
μs
UNIT
Watchdog Switching Characteristics
VBAT = 6 V to 20 V, VDD = 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TWD
Watchdog window
TWD_PULSE
Watchdog induced reset
pulse
TEST CONDITIONS
MIN
TYP
MAX
Upper window (WDH)
–10%
programmable
10%
Lower window (WDL)
10%
programmable
10%
Out-of-range window (2 × WDH)
10%
programmable
10%
1
1.5
2
Watchdog out-of-range (counter stays at
000)
ms
ms
4.27 Wheel Speed Interface Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
trise_WSPx
tfall_WSP
trise_WSLSx
tfall_WSLSx
trise_WSSQx
tfall_WSSQx
TEST CONDITIONS
MAX
UNIT
100
μs
50-mA load
50
μs
50 mA load, C = 200 pF
50
μs
Propagation delay from rising edge
of CSN to the rising and falling edge
of WSPx.
20 mA load, Cload = 10 nF
Propagation delay from rising edge
of CSN to rising and falling edge of
WSLSx
Propagation delay from rising edge
of CSN to rising and falling edge of
WSSQx
MIN
TYP
4.28 Wheel-Speed High-Side Driver Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tdelay_WSPx
TEST CONDITIONS
Delay time for fault reporting
MIN
TYP
MAX
UNIT
80
100
120
μs
MIN
TYP
MAX
UNIT
4.29 Wheel-Speed Output Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Tdelay_WSS
Delay time for overcurrent fault reporting
Qx
Delay time for open load fault
reporting
16
Specifications
15
20
25
µs
140
200
260
µs
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Figure 4-1. SPI Interface Input Timing
Specifications
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4.30 Typical Characteristics
14.5
Current Consumption IVDD (mA)
Current Consumption I VBAT (mA)
3.5
3
2.5
2
1.5
-70
-20
30
80
Temperature (Cq)
130
14
13.5
-70
180
-20
30
80
Temperature (Cq)
D002
Figure 4-2. Current Consumption from VBAT vs Temperature
130
180
D002
Figure 4-3. Current Consumption from VDD vs Temperature
VCC3 Regulator Output Voltage (V)
3.315
40qC
25qC
125qC
3.31
3.305
3.3
3.295
3.29
3.285
3.28
3.275
0
2
4
6
8
Load Current (mA)
10
12
D004
Figure 4-4. VCC3 Regulator Load Regulation Across Temperature (VDD = 4.5 V)
18
Specifications
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5 Detailed Description
5.1
Overview
The TPIC7218-Q1 device is an anti-lock braking controller capable of directly driving eight solenoid valves
with internal high-current low-side drivers. Low-side drivers configured for digital control do not require
external voltage clamps. The TPIC7218-Q1 device has gate drive capability for two high-side N-Channel
MOSFETs that can be used to drive a pump motor and power to all solenoids. The TPIC7218-Q1 device
provides a fault-tolerant interface for both Intelligent and Active wheel-speed sensors to an external
microprocessor.
The TPIC7218-Q1 device can be used with either 3.3- or 5-V microprocessors and uses a standard SPI
(Serial-Peripheral Interface). The TPIC7218-Q1 device has two internal open-drain warning lamp drivers
that can be pulled up to battery voltage, as well as one low-voltage driver. An internal state machine
monitors a watchdog input and reports faults on a warning-lamp pin and SPI register. A K-Line transceiver
is also included. A multitude of safety and fault monitoring functionality supervise both system and
TPIC7218-Q1 circuits. Faults must be polled and reset over SPI.
The TPIC7218-Q1 device is designed for use in harsh automotive environments, capable of withstanding
high operating temperatures and electrically noisy signals and power. Short-to-ground, short-to-battery,
and open-load conditions are tolerated and monitored. The TPIC7218-Q1 device also exhibits outstanding
electromagnetic compatibility (EMC) performance.
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5.2
Functional Block Diagram
5.3
Feature Description
5.3.1
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Ground Connections
The TPIC7218-Q1 device has two types of grounds: Power-grounds (PGND), which are used to provide a
path for internal high-current open-drain FETs, and ground (GND), which are used to provide ground to all
analog and digital circuitry. All the PGND pins and the thermal pad are internally shorted together. A verylow impedance connection exists internal to the TPIC7218-Q1 device between all power grounds and the
ground pin (pin 6). TI recommends that all PGND, GND, and PowerPad pins be connected together at the
pins of the TPIC7218-Q1 device to a solid ground plane. Failure to implement the grounding in this way is
likely to result in poor EMC performance.
20
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Charge Pump
An internal charge pump generates the charge necessary for proper operation of all drivers. A capacitor
with a value of 100 nF connected between the CHP pin and VBAT pin is required for proper operation.
The voltage on the CHP pin is typically 12 V greater than the voltage on the VBAT pin. When selecting a
charge pump capacitor, care must be taken to ensure that the capacitors specifications are not violated.
5.3.3
Reference Current Generator
The TPIC7218-Q1 device generates an internal reference current that is output on the REF pin. This pin
requires a 10-kΩ, ±1% resistor connected to GND.
5.3.4
Wheel-Speed Reference, VREF
The voltage set on the VREF pin must be stable at all times. If this voltage deviates from the desired
setting, then all the wheel-speed thresholds will change. TI recommends externally monitoring the VREF
voltage to ensure proper operation of the wheel-speed functional block.
5.3.5
Faults Common To Most Functional Blocks
Table 5-1. Summary Fault State Table
GMR
GPR
WLQ1
WLQ2
WL_LS
nRST
Q1-Q4
Q5-Q8
WSPx
WSLSx
SPI
VDD undervoltage
shutdown
EVENT
OFF
OFF
High Z
High Z
Low
Low
High Z
High Z
OFF
High Z
YES (1)
VDD undervoltage
reset
OFF
OFF
High Z
High Z
High Z
High Z
High Z
High Z
OFF
High Z
NO
Recovery after VDD
undervoltage reset
(VDD>4.85V)
OFF
OFF
High Z
High Z
Low
High Z
High Z
High Z
OFF
High Z
YES
Recovery after VDD
undervoltage reset
(VDD
*100%
1024
(1)
For example, a setting of 0x3FF causes a 100% duty cycle and a setting of 0x000 causes a 0% duty
cycle.
All 10 bits must be written for the new duty cycle code to be latched into the state machine. Changes in
the 10-bit result in a duty-cycle change in the following complete period to prevent glitches. PWM drivers
can be used as digital drivers by fully turning them on (100% duty cycle) and off (0% duty cycle).
However, care must be taken not to violate electrical specifications when using PWM drivers in this way
(such as energy handling capability).
22
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The frequency is also configurable (see Table 5-3), but is not independent for each enabled driver; all
PWM drivers are set by selecting a 2-bit value in register 0x12. Frequency selection changes take place
only when the PWM drivers are disabled and then re-enabled.
Table 5-3. PWM Frequency Selection
PWMFreq
PWMFreq
SELECTED FREQUENCY
0
0
2 kHz
1
0
4 kHz
0
1
8 kHz
1
1
16 kHz
For example, if Q5 is enabled while the frequency setting is but Q6 is enabled after the frequency
setting was changed to , then Q5 is switching at 2 kHz and Q6 is switching at 16 kHz.
Each PWM driver monitors, reports, and has integrated protection for many electrical fault conditions.
Overcurrent faults are reported as a 1 in register 0x02, (bits 0, 2, 4, and 6 are referenced by bits F5, F6,
F7, and F8) and cause the affected driver to disable after a deglitch time of toff_blank_PWMx. Overtemperature (junction) faults are reported in register 0x03, (bit-6 OTSD) and cause not only the affected
driver, but also the adjacent driver to disable after a deglitch time of toff_tmp_PWMx. The PWM drivers
also check for an open-load or short to ground condition whenever they are not disabled. This type of fault
is reported as 1 in register 0x02, (bits 1, 3, 5, 7 are referenced by bits S5, S6, S7, and S8). A master lowside fault bit in register 0x00, (bit-0) becomes high whenever any of the previously mentioned overcurrent
or open-load faults occur. Fault flags can be cleared after the removal of the fault condition by reading the
appropriate fault reporting register. When the fault flags are cleared, the low-side master fault bit (FAIL)
can be cleared by reading it.
The PWM drivers also respond to fault conditions within other functional blocks. The drivers are disabled
whenever VBAT undervoltage, VBAT overvoltage, or VDD undervoltage fault bits in register 0x00 are set.
Also watchdog fault can cause PWM drivers to disable, if register 0x11, bit-4 (WD_EN) is set. This bit
defaults to 0 upon power up. Any of these faults do not cause the FAIL bit to be set.
Faults can be cleared by reading the appropriate fault reporting register. When the faults are cleared, the
drivers can be re-enabled. To enable or re-enable a driver, simply toggle the driver bits (GE5, GE6, GE7,
GE8) by writing a 0, then 1. Fault reporting bits do not have any affect on PWM drivers; only the actual
fault condition causes a driver to disable. Nevertheless, TI recommends clearing the fault bits by reading
these bits before enabling the drivers.
Besides monitoring and reporting faults, PWM drivers have overvoltage-protection circuitry built in. An
active-clamp monitors the voltage on PWM driver pins and limits it to Vcl_PWMx. At the system level, PWM
drivers use an external recirculation diode in parallel with the inductive load.
5.3.7
Digital Low-Side Drivers
The TPIC7218-Q1 device features eight low-side drivers, four of which can be used digital control of
solenoids. The low-side driver pins: Q1, Q2, Q3, and Q4 are open-drain MOSFETs that are capable of
sinking large amounts of current. Each driver is monitored for three fault conditions: overcurrent, openload, and over-temperature. However, driver operation also is dependant on other fault conditions: VBAT
undervoltage, VBAT overvoltage, VDD undervoltage, watchdog fault. See the application circuit and
register diagram in Figure 5-2.
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V_RELAY
Q1,2,3,4
µP
SPI
4
DIGITAL CORE
GATE DRIVE
AND
FAULT DETECT
PGND
PGND
Figure 5-2. Digital Driver Register and Application Circuit Diagram
Each digital driver monitors, reports, and has integrated protection for many electrical fault conditions.
Overcurrent faults are reported as a 1 in register 0x01, (bits 0, 2, 4, and 6 are referenced by bits F1, F2,
F3, and F4) and cause the affected driver to disable after a deglitch time of toff_blank_DLSx. Overtemperature (junction) faults are reported in register 0x03, (bit-6 OTSD) and cause not only the affected
driver, but also the adjacent driver to disable after a deglitch time of toff_tmp_DLSLx. Digital drivers also
check for an open-load or short to ground condition whenever they are not enabled. This type of fault is
reported as a 1 in register 0x01, (bits 1, 3, 5, 7 are referenced by S1, S2, S3, and S4). The master lowside fault bit in register 0x00, (bit-0) becomes high whenever an overcurrent or open-load fault occurs.
Fault flags can be cleared after the removal of the fault condition by reading the appropriate fault reporting
register. When this occurs the low-side master fault bit (FAIL) can be cleared by reading it.
The digital drivers also respond to fault conditions within other functional blocks. These drvers are
disabled whenever the VBAT undervoltage, VBAT overvoltage, or VDD undervoltage fault bits in register
0x00 are set. Also, a watchdog fault can cause the digital drivers to disable if register 0x11, bit-4 (WD_EN)
is set. This bit defaults to 0 upon power up. Any of these faults do not cause the FAIL bit to be set.
Faults can be cleared by reading the appropriate fault reporting register. When this is complete the digital
drivers can be re-enabled. To enable or re-enable a driver, simply toggle the driver bits (GE1, GE2, GE3,
GE4) by writing a 0, then 1. Fault reporting bits do not have any affect on the digital drivers; only the
actual fault condition will cause a driver to disable. Nevertheless, TI recommends clearing the fault bits by
reading them before enabling the drivers.
Besides monitoring and reporting faults, digital drivers have overvoltage protection circuitry built in. An
active-clamp monitors voltage on the pins of these drivers and limits the voltage to Vcl_DLSx.
24
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5.3.8
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High-Side Drivers
The TPIC7218-Q1 device features two independent high-side gate drivers to control and monitor external
N-Channel FETs. The pins, GPR, SPR, and DPR, are typically used to control an external N-MOSFET for
the purpose of providing power to a motor pump. The pins, GMR, SMR, and DMR are typically used to
control an external N-MOSFET for the purpose of providing power to the solenoid coils. When activated,
the gate voltage drive on the GPR and GMR pins is sufficient to provide a strong VGS because of a built-in
charge pump. High-side drivers are electrically protected and monitored for fault conditions.
5.3.8.1
High-Side Terminals: GPR, SPR, DPR, and HSPC
The GPR, SPR, and DPR (gate, source, and drain-pump relay) pins connect to an external N-MOSFET as
shown in Figure 5-3. The purpose of this MOSFET is to relay the VBAT power to a pump motor. The NMOSFET is turned on when the GPR pin is enabled. The GPR pin is controlled by either the HSPC pin or
the GE_PR bit, bit-3 of address 0x11 as listed in Table 5-4.
C CHP
CPC
CHARGE PUMP
V_BAT
0 .1µF
I DPR
DPR
V_BAT
R DPR
COMP #1
µP
SPI
4
GPR
DIGITAL CORE
HSPC
COMP #2
BG (2V)
SPR
GPR
GATE DRIVE
MOTOR GND
Figure 5-3. GPR, SPR, DPR, and HSPC Register and Application Circuit Diagram
Table 5-4. High-Side Operation Logic
HSPC PIN
GE_PR BIT
GPR GATE PIN
LOW
0
OFF
LOW
1
ON
HIGH
0
ON
HIGH
1
ON
OPEN
1
ON
OPEN
0
OFF
The overcurrent detection of the external N-MOSFET is triggered by a voltage difference between the
DPR and SPR pins in comparator COMP #1. To set the overcurrent threshold the external series resistor,
RDPR, must be sized to generate a particular input voltage (in conjunction with IDPR) on one input of the
comparator. The other input voltage of the comparator changes as a function of the RDSON(MAX) and IDS
values of the N-MOSFET. By comparing these voltages, the N-MOSFET overcurrent condition is reported.
Given the RDSON(MAX) value of the N-MOSFET and the desired overcurrent threshold, RDPR can be
calculated using Equation 2.
VBAT - ( I DS * RDSON ( MAX ) ) > VBAT - ( I DPR * RDPR )
(2)
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If the VDS value of the N-MOSFET exceeds the threshold set by the comparator for more than the
deglitcher time, tOCdet, the GPR pin switches off and the appropriate fault flag (OCPR) is set high. When
the overcurrent condition ends, the GPR pin can be switched on again with the SPI enable bit or the
external enable pin.
Faults detected on VDD, VBAT, Watchdog (if WD_EN bit is high) prevent the high-side driver from
enabling; GPR remains low or turns off. At the time the high-side driver is enabled, voltage on GPR pin is
tested for a short-to-ground condition only after a certain delay time defined as tSTGPR. If a short is
detected the GPR pin remains low. Any time the high-side driver is enabled overcurrent in the external
MOSFET, short-to-ground on GPR, and short-to-ground on SMR can cause a fault condition and disable
the high-side driver.
An overvoltage condition (such as load-dump) on VBAT turns the GPR pin on (clamping any energy from
the alternator). If VBAT returns to normal operating voltage from an overvoltage fault condition, the GPR
pin remains on for a minimum time, tGPRact.
If an overvoltage condition occurs on VBAT, the fault flag, FOV, is set after a deglitch time, tFovdet. With the
overvoltage removed, the FOV flag can be cleared by reading address 0x00. After the fault bit is cleared,
the GPR pin can be re-enabled. The GPR pin does not respond to successive overvoltage conditions until
after a blanking time. See Table 5-5 and Figure 5-4 for more details.
Table 5-5. Pump Relay Fault and Operation
TPIC7218-Q1 STATE
SYSTEM EVENT
FAULT BITS AFFECTED
BEFORE
EVENT
AFTER EVENT
GPR ON
GPR OFF
NOTES
VDD Undervoltage
PORn = 1
nRST is internally driven
low
VBAT Overvoltage (>VovVBAT)
FOV = 1
GPR OFF
GPR ON
VBAT Undervoltage ( tSTGPR)
GPR OFF
GPR OFF
FGPRDIS = 0 (disabled),
turn ON GPR
Short to GND on GPR, while GPR is ON
WD_EN = 1 (enabled)
FGPR = 1,FHSD = 1
GPR ON
GPR OFF
FGPRDIS = 0 (enabled)
Short to GND on GPR, while GPR is OFF FGPR = 1,FHSD = 1
(time > tSTGPR)
GPR OFF
GPR ON
FGPRDIS = 1 (enabled),
turn ON GPR
Short to GND on GPR, while GPR is ON
FGPR = 1,FHSD = 1
GPR ON
GPR ON
FGPRDIS = 1 (enabled)
Short to GND on SPR
STGPR = 1,FHSD = 1
GPR ON
GPR ON
STGPRDIS = 1 (enabled)
Short to GND on SPR
STGPR = 1,FHSD = 1
GPR ON
GPR OFF
STGPRDIS = 0 (disabled)
Overvoltage
VBAT
GPR
tGPRact
tGPRact
TFovdet
Start
tGPRact
Start
tGPRact
Figure 5-4. Pump Relay High-Side Driver Overvoltage Behavior
The pump relay external MOSFET is electrically protected from voltage spikes by an active voltage clamp
that limits any voltage levels between the GPR and SPR pins that are larger than Vgs_clamp.
26
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The GPR function supports PWM output. The charge on the charge-pump capacitor, CCHP, which is lost
when GPR is switched on, is refreshed before the start of the next PWM cycle to a value that sufficiently
ensures proper turnon behavior. The PWM capability consists of a period of T = 5 ms with a duty cycle
10% to 90%. When selecting a duty cycle the rise and fall times of GPR must be taken into account.
5.3.8.2
High-Side Terminals: GMR, SMR, DMR, and HSMC
The GMR, SMR, and DMR (gate, source, and drain master relay) pins connect to an external N-MOSFET
as shown in Figure 5-5. The purpose of this MOSFET is to relay VBAT power to a master power supply
for solenoid coils. The N-MOSFET turns on when the GMR pin is enabled. The GMR pin function is
controlled by either the HSMC pin or the GE_MR bit, bit-2 of address 0x11 as shown in Table 5-6.
C CHP
CHARGE PUMP
CPC
V_BAT
0 .1µF
I DMR
V_BAT
R DMR
5V
DMR
COMP #1
µP
SPI
4
HSMC
COMP #2
BG (2V)
GATE DRIVE
R SOL
GMR
DIGITAL CORE
SMR
GMR
V_RELAY
Low Side Drivers V_RELAY
Q1,2,3,4,5,6,7,8
Figure 5-5. GMR, SMR, DMR, and HSMC Register and Application Circuit Diagram
Table 5-6. High-Side Operation Logic
HSMC PIN
GE_MR BIT
GMR GATE PIN
LOW
0
OFF
LOW
1
ON
HIGH
0
ON
HIGH
1
ON
OPEN
1
ON
OPEN
0
OFF
The overcurrent detection of the external N-MOSFET is triggered by a voltage difference between the
DMR and SMR pins in comparator COMP #1. To set the overcurrent threshold, the external series
resistor, RDMR, must be sized to generate a particular input voltage (in conjunction with IDMR) on one input
of the comparator. The other input voltage of the comparator changes as a function of the RDSON(MAX) and
IDS values of the N-MOSFET. By comparing these voltages, the N-MOSFET overcurrent condition is
reported. Given the RDSON(MAX) value of the N-MOSFET and the desired overcurrent threshold, RDMR can
be calculated using Equation 3.
VBAT - ( I DS * RDSON ( MAX ) ) > VBAT - ( I DMR * RDMR )
(3)
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If the VDS of the N-MOSFET exceeds the threshold set by the comparator for more than the deglitcher
time, tOCdet, the GMR pin switches off and the appropriate fault flag (OCMR) is set high. When the
overcurrent condition ends, the GMR pin can be switched on again with the SPI enable bit or the external
enable pin.
Faults detected on VDD, VBAT, Watchdog (if WD_EN bit is high) prevent the high-side driver from
enabling; the GMR pin remains low or turns off. At the time the high-side driver is enabled, the voltage on
the GMR pin is tested for a short-to-ground condition only after a certain delay time defined as tSTGPR. If a
short is detected the GMR pin remains low. Any time the high-side driver is enabled overcurrent in
MOSFET, short-to-ground on the GMR pin, and short-to-ground on the SMR pin can cause a fault
condition and disable the high-side driver.
An overvoltage condition (such as a load-dump) on VBAT either turns the GMR pin off or allows it to
remain in the previous state depending on the setting of bit 5 (OV_GMR) in register 0x11. With the
overvoltage removed, the fault flag FOV can be cleared by reading address 0x00.
The main relay external MOSFET is electrically protected from voltage spikes by an active voltage clamp
that limits any voltage levels between GMR and SMR larger than Vgs_clamp.
Load-leakage faults are tested by sourcing a current, ILCdet, out of the SMR pin into the source of the
external N-MOSFET. After a time, tLCdet, the SMR voltage is checked to see if it is above VDD. If no
leakage is present, the source is above VDD and the GMR pin is turned on. If leakage is present, the
source is below VDD and the GMR pin does not turn on. A high on the LMR bit indicates a load-leakage
fault. During a load-leakage fault, the SMR pin is biased to the voltage set by the external resistor (RSOL)
and a series diode to VDD. Without this path, the SMR pin is floating and may not display faults properly.
Table 5-7 lists a summary of the faults that affect the GMR pin behavior.
Table 5-7. Master Relay Fault and Operation
TPIC7218-Q1 STATE
SYSTEM EVENT
FAULT BITS AFFECTED
BEFORE
EVENT
AFTER
EVENT
NOTES
VDD Undervoltage
PORn = 1
GMR ON
GMR OFF
nRST pin is internally driven
low
VBAT Overvoltage (>VovVBAT)
FOV = 1
GMR ON
GMR OFF
OV_GMR = 1
VBAT Overvoltage (>VovVBAT)
FOV = 1
GMR ON
GMR ON
OV_GMR = 0
VBAT Undervoltage ( tSTGMR)
GMR OFF
GMR OFF
FGMRDIS = 0 (disabled),
turn ON GMR
Short to GND on GMR, while GMR is ON
FGMR = 1,FHSD = 1
GMR ON
GMR OFF
FGMRDIS = 0 (disabled)
Short to GND on GMR, while GMR is OFF
FGMR = 1,FHSD = 1
(time > tSTGMR)
GMR OFF
GMR ON
FGMRDIS = 1 (enabled),
turn ON GMR
Short to GND on GMR, while GMR is ON
FGMR = 1,FHSD = 1
GMR ON
GMR ON
FGMRDIS = 1 (enabled)
Short to GND on SMR
STGMR = 1,FHSD = 1
GMR ON
GMR OFF
STGMRDIS = 0 (disabled)
Short to GND on SMR
STGMR = 1,FHSD = 1
GMR ON
GMR ON
STGMRDIS = 1 (enabled)
GMR is turned on while Q1-Q8 on
LGMR = 1,FHSD = 1
GMR OFF
GMR OFF
LGMRDIS = 0 (disabled),
turn ON GMR
GMR is turned on while Q1-Q8 on
LGMR = 1,FHSD = 1
GMR OFF
GMR ON
LGMRDIS = 1 (enabled),
turn ON GMR
28
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WD_EN = 1 (enabled)
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The high-side GMR, SMR, and DMR functionality also includes logic that facilitates system diagnostic
testing. The operational status, as well as some fault conditions can be determined for both high-side
drivers (HSD) and low-side drivers (LSD). Table 5-8 lists the details.
Table 5-8. High-Side Driver Logic (GMR Only)
5.3.9
HSD
FET
LSD FETx
COMP #1
(HSDC1)
COMP #2
(HSDC2)
ON
ON
OFF
L
L
Normal operating condition for HSD FET
OFF
H
L
HSD FET open
ON
ON
ON
L
L
Normal operating condition for HSD and LSD FETs
ON
H
L
HSD (GMR) FET in overcurrent condition
ON
ON
H
H
HSD (GMR) FET in short to ground condition
OFF
ON
H
H
Normal operating condition for LSD
OFF
ON
H
L
Open load or open LSD FETx
OFF
OFF
H
L
Normal operating condition for HSD FET
OFF
OFF
H
H
Load short to ground/LSD FETx short to ground
RESULT
Wheel-Speed Sensing
The TPIC7218-Q1 device is capable of interfacing with industry standard Active and Intelligent wheelspeed sensors. The TPIC7218-Q1 device features an analog front end that provides power, ground, and
interprets current-encoded speed and diagnostic information (Intelligent VDA sensors only) for sensors.
Current thresholds can be adjusted to easily interface with most sensors. By setting a voltage on the VREF
pin in conjunction with an appropriate current sense resistor, RLOAD, current levels through the wheelspeed sensors are evaluated according to the threshold states. Active wheel-speed sensor current pulse
levels can be: undercurrent, overcurrent, wheel-speed-pulse-low (for example 7 mA), and wheel-speedpulse-high (for example 14 mA). Intelligent wheel-speed sensor current pulse levels can be: undercurrent,
overcurrent, wheel-speed-pulse-low (for example 7 mA), wheel-speed-pulse-high (for example 28 mA),
and diagnostic-data-bit (for example 14 mA). Wheel-speed-pulse-low and wheel-speed-pulse-high logic
state is directly interpreted to a digital voltage output for each sensor (rotational speed). Diagnostic
information, diagnostic-data-bit, is directly decoded and placed in four 9-bit registers. Rotational speed
information (for two sensors) is also available on high-voltage open-drain outputs. Rotational wheel-speed
pulse information for any of the sensors can be MUX-ed into a digital pulse counter. This counter
increments on both rising and falling edges. The 8-bit counter, along with other wheel-speed bits are
available over SPI. Wheel-speed pins are also electrically protected from typical fault conditions. See
Figure 5-6 for register and applications information.
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C CHP
CHARGE PUMP
CPC
V_BAT
DIGITAL CORE
0 .1µF
SPI
4
WSP1/2/3/4
4
CNT_EN
CNT_CLR
µP
C LOAD_WSPx
WHEEL SPEED
DIGITAL
PULSE
COUNTER
Wheel
Speed
Sensor
WHEEL SPEED
SENSOR
INTERFACE
WSSOUT1/2/3/4
GND
WSLS1/2/3/4
4
4
C LOAD
GND
OPTIONAL
SYSTEM ESD
FILTER
V_BAT
WSS1/2/3/4
R LOAD
GND
4
R WSSQ 1
WSSOUT1
VDD
WSSQ1
R WSSQ 2
WSSQ2
WSSOUT2
THRESHOLD
DETECTION
REFERENCE
CIRCUIT
VREF
GND
Figure 5-6. Wheel-Speed Register and Application Circuit Diagram
The TPIC7218-Q1 device has three pins for each of the four wheel-speed sensors. The WSPx pins
provide a path for current from VBAT to the wheel-speed sensor. The WSLSx pins provide a path for
current from the wheel-speed sensor to GND. The WSSx pins monitor current through the sensor by
measuring a voltage across the RLOAD resistance, shown in Figure 5-6.
Current is provided to the sensor from the WSP1, WSP2, WSP3, and WSP4 pins. When enabled (by
setting the WSPx bits in register 0x1B), the WSPx pins output current and are voltage clamped to
Vclamp_WSPx. WSPx pins are electrically protected from short-to-battery, short-to-ground, and overcurrent.
Short-to-battery fault bits, WSPx_STB, are located in registers 0x08, 0x0A, 0x0C, 0x0E and overcurrent
fault bits, WSPxILIMIT, are located in register 0x1D. If a fault is detected, then the WSPx pins disable.
Reading these registers clears the fault bits after the fault condition has been removed.
Current from the sensors is returned to the WSP1, WSP2, WSP3, and WSP4 pins of the TPIC7218-Q1
device, thus providing a path to ground. Current out of the sensor passes through a series resistor, RLOAD,
into internal open-drain MOSFETs. These open-drain MOSFETs are controlled by setting the WSLSx bits
in register 0x1C. The WSLSx pins are electrically protected from overcurrent by detecting an excessive
voltage between WSLSx and WSSx pins. Overcurrent fault bits, WSSxOC, are located in register 0x0F. If a
fault is detected then the WSLSx pins stop sinking current. Reading these registers clears the fault bits
after the fault is removed.
The sensed voltage difference between the WSSx and WSLSx pins provides the current encoded sensor
information to the wheel-speed logic. The WSSx pins are electrically protected from short-to-battery and
short-to-ground. These conditions are reported by reading the WSSxOC and WSSxFAULT bits in register
0x0F.
If a fault occurs on WSLSx, the path of the sensor to ground is removed. This type of fault must be
cleared by following a specific procedure to prevent an overcurrent fault from being erroneously reported.
To clear this fault, first disable the WSPx pins, re-enable the WSLSx pins, and finally re-enable the WSPx
pins. The main purpose for this procedure is to first provide a ground path for the sensor before providing
power. Other types of faults can be cleared in the normal way, as long as the WSLSx pins are enabled.
Table 5-9 lists more information about wheel-speed faults.
30
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Table 5-9. Wheel-Speed Sense Fault and Operation
TPIC7218-Q1
SYSTEM EVENT
FAULT BITS AFFECTED
VDD Undervoltage
NOTES
PRIOR TO
EVENT
POST EVENT
PORn = 1
WSPx ON
WSLSx ON
WSSQx ON
WSPx OFF
WSLSx OFF
WSSQx OFF
All of the enable bits for these
functions are cleared. nRST is driven
low.
VBAT Overvoltage
(>VovVBAT)
FOV = 1
WSPx ON
WSLSx ON
WSSQx ON
WSPx OFF
WSLSx OFF
WSSQx OFF
All of the enable bits for these
functions are cleared
nRST pin externally driven
low
Erst = 1
WSPx ON
WSLSx ON
WSSQx ON
WSPx OFF
WSLSx OFF
WSSQx OFF
All of the enable bits for these
functions are cleared
Overcurrent in WSPx
WSPxILIMIT = 1
WSPx ON
WSLSx ON
WSSQx ON
WSPx OFF
WSLSx ON
WSSQx ON
WSSQx and WSLSx remain on but
no wheel-speed output is produced
because the sensor has no power.
The enable bits for WSPx remain 1
Overcurrent in WSSx-WSLSx
WSSxOC = 1
WSPx ON
WSLSx ON
WSSQx ON
WSPx ON
WSLSx OFF
WSSQx ON
WSPx and WSSQx remain on but no
wheel-speed output is produced
because the sensor has no ground.
The enable bits for WSLSx remain 1
Overcurrent in WSSQx
WSSQxILIMIT = 1
WSPx ON
WSLSx ON
WSSQx ON
WSPx ON
WSLSx ON
WSSQx OFF
Short to VBAT on WSPx
WSPx_VBAT = 1
WSPx OFF
WSLSx ON
WSSQx ON
WSPx OFF
WSLSx ON
WSSQx ON
This fault is detected only while
WSPx are OFF. WSLSx and WSSQx
remain unaffected while WSPx is on
and shorted to VBAT.
Short to GND on WSLSx
WSSxFAULT = 1
WSPx ON
WSLSx ON
WSSQx ON
WSPx ON
WSLSx ON
WSSQx ON
WSSQx and WSPx remain on;
wheel-speed outputs may be
produced but the wheel-speed
ground path is not through
TPIC7218-Q1 anymore
Short to GND on WSSQx
WSSQxFAULT = 1
WSPx ON
WSLSx ON
WSSQx OFF
WSPx ON
WSLSx ON
WSSQx OFF
This fault is detected only while
WSSQx are off. WSPx and WSLSx
remain on and wheel-speed outputs
can still be observed.
WSLSx and WSPx remain on. The
enable bits for WSSQx remain 1
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The wheel-speed internal equivalent model, shown in Figure 5-7 and Figure 5-8, describe how this
functional block works. Users need only select a wheel-speed sensor, current sense resistor, RLOAD, and
VREF voltage for basic operation. The wheel-speed functionality is designed to accommodate both Active
and Intelligent sensors; the WSSTYPE bit in register 0x1D must be set appropriately.
Figure 5-7. Internal Diagram Using Intelligent Type Sensor (WssTYPE = 0)
Table 5-10. Intelligent Sensor Wheel-Speed Thresholds
(1)
32
THRESHOLD
SIGNIFICANCE
PERCENTAGE OF MAXIMUM
THRESHOLD (1)
VTHRESH4
ISENSOR > ITHRESH4
Overcurrent (possible short to battery)
100% (40 mA)
VTHRESH3
ITHRESH4 > ISENSOR > ITHRESH3
Rotational Wheel-Speed Logic- High
50% (20 mA)
VTHRESH2
ITHRESH3 > ISENSOR > ITHRESH2
Diagnostic sensor Information (9-bit)
25% (10 mA)
VTHRESH1
ISENSOR < ITHRESH1
Undercurrent (possible short to ground)
11.25% (4.5 mA)
The current is based on maximum of 40 mA, RLOAD OF 50 Ω, and VREF of 2 V
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Figure 5-8. Internal Diagram Using Active Type Sensor (WssTYPE = 1)
Table 5-11. Active Sensor Wheel-Speed Thresholds
(1)
THRESHOLD
SIGNIFICANCE
PERCENTAGE OF MAXIMUM THRESHOLD (1)
VTHRESH4
ISENSOR > ITHRESH4
*Not used
100% (20 mA)
*Not used
VTHRESH3
ISENSOR > ITHRESH3
Overcurrent (possible short to battery)
100% (20 mA)
VTHRESH2
ITHRESH3 > ISENSOR > ITHRESH2
Rotational wheel-speed logic- high
50% (10 mA)
VTHRESH1
ISENSOR < ITHRESH1
Undercurrent (possible short to ground)
22.5% (4.5 mA)
The current is based on maximum of 40 mA, RLOAD OF 50 Ω, and VREF of 2 V.
Both types of sensors provide information based on varying current levels. The TPIC7218-Q1 device
provides a way to select different current thresholds by adjusting a voltage on the VREF pin. Internally, the
voltage on VREF governs all four thresholds in a ratio metric manner. VREF voltage actually sets the
maximum threshold (100%), then, all the other thresholds are automatically set. Intelligent sensors require
ITHRESH4 to be set to the maximum threshold, IWSS(overcurrent), and Active sensors require ITHRESH3 to be set
to the maximum threshold. For both Intelligent sensors (requiring four thresholds) and Active sensors
(requiring three thresholds) use Equation 4 to select a value for VREF.
VREF = RLOAD * IWSS ( over -current )
(4)
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For example, a typical Intelligent wheel-speed sensor may have a maximum typical current less than 40
mA. This 40-mA current must be set to correspond to VTHRESH4 (100%). If the value of RLOAD is selected
as 50 Ω, then the resulting VREF voltage is calculated to be 2 V. Similarly, a typical Active wheel-speed
sensor may have a maximum typical current less than 20 mA. This 20-mA current must be set to
correspond to VTHRESH3 (100%). However, by setting the WSSTYPE bit, the digital decoder uses VTHRESH3
threshold to actually determine if an overcurrent condition is occurring. By effectively removing the
VTHRESH4 resistor in the comparator resistor chain, shown in Figure 5-9, a VREF voltage of 2.4 V and an
RLOAD of 120 Ω, are needed to properly set the current thresholds. The ratio of the resistor chain did not
change, however the current threshold detection levels did. See Figure 5-9 for more detail.
100%
ITHRESH4
100%
mA
mA
I THRESH3
14
50%
I THRESH2
ITHRESH3
50%
ITHRESH2
25%
ITHRESH1
11.25%
14
7
0
Intelligent Wheel Speed Sensor
28
Active Wheel Speed Sensor
7
22.5%
I THRESH1
0
time
time
Figure 5-9. Example Wheel-Speed Current Pulse Diagram
While selecting RLOAD and VREF, care must be taken so that all electrical specification values are not
violated. When the maximum current threshold is selected, the other three thresholds are automatically
set.
During normal operation, the WSSOUTx pins provide a digital signal that is high whenever sensor current
creates a voltage drop across RLoad that is above the VTHRESH3 level for intelligent sensors and VTHRESH2
level for Active sensors. If the current is less than these respective thresholds, the WSSOUTx pins return
to ground. The WSSQ1 and WSSQ2 pins are open-drain outputs that reproduce signals on the
WSSOUT1 and WSSOUT2 pins after a propagation delay time of twss_delay. A high level on WSSOUT1 or
WSSOUT2 results in low level on WSSQ1 or WSSQ2 pin. These two pins are useful for providing wheelspeed information in a high voltage signal form. The WSSQ1 and WSSQ2 pins also have short-to-ground
and open-load detection functionality. The WSSQxFAULT and WSSQxILIMIT bits in register 0x05 report these
faults and are cleared by reading them after the removal of the fault condition. During an overcurrent fault
the WSSQ1 and WSSQ2 pins remain enabled for a time of tdelay_WSSQx. After this time these pins are
disabled.
The TPIC7218-Q1 device also features an 8-bit wheel-speed pulse counter. This counter increments on
every rising and falling edge of a selected WSSOUTx. A MUX selects which the WSSOUTx signal is input
to the counter; bits WS_Cnt_MUX[1] and WS_Cnt_MUX[0] program the MUX as listed in Table 5-12.
Count data is reported in register 0x04. A high on the CNT_EN pin allows the counter to increment. A high
on the CNT_CLR pin forces the counter to reset to 0. The count value is available for read through SPI at
any point. If the counter is allowed to reach maximum value, the count value remains at maximum but an
overflow bit, WSS_OV_Cnt is set. If both CNT_CLR and CNT_EN pins are in a high logic state then the
WS_Fail_Cnt bit is set. These bits clear on read after the fault conditions have been removed.
Table 5-12. Wheel-Speed Counter Input
34
WS_Cnt_MUX[1]
WS_Cnt_MUX[0]
SELECTED INPUT
0
0
WSSOUT1
1
0
WSSOUT2
0
1
WSSOUT3
1
1
WSSOUT4
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When the TPIC7218-Q1 device is paired with VDA protocol compatible Intelligent wheel-speed sensors,
additional functionality for processing and reporting diagnostic information can be enabled. Diagnostic
encoded data (Manchester encoded) in the form of current pulses reaching the ITHRESH2 (10 mA) threshold
are decoded and placed in the WSSxDx bits. All nine bits are available for reading. If any of the (nine) bit
pulse widths were outside the allowed pulse width range (36 μs to 64 μs including variations) then the
pulse widths are not counted as valid. As each of the nine bits are input, only valid bits cause the
WSSx_Valid counter to increment. In this way information about bit errors, or fewer than nine bits being
sent from the sensor is recorded and available for each wheel-speed channel. The TPIC7218-Q1 device
also contains logic to determine when a new 9-bit frame has started to be input. When detected, the
WSSx_New bit is set. If the wheel-speed sensor is in stand still mode then the TPIC7218-Q1 device
detects this current pulse activity, resulting in the WSS_MODE bit being set. Both of these bits can be
cleared upon read.
5.3.10 K-Line
The TPIC7218-Q1 device includes a serial communication transceiver for K-Line. K-Line provides a bidirectional half-duplex interface for automotive diagnostic communication with data transfer rates of up to
10.4 kbps. The integrated transceiver conforms to the ISO-9141 standard and meets the on-board
diagnostic (OBD) requirements of the California Air Resources Board (CARB). For more information on
the K-Line protocol see the compete K-Line standard.
Features of the K-Line module include the following:
• ISO-K operates over a wide signal voltage range and is capable of driving high currents.
• ISO-K pin can tolerate a parasitic capacitance of up to 10 nF.
• ISO-K pin is electrically protected to withstand short-to-ground and overcurrent faults.
• The driver stage of the ISO-K pin is thermally protected. A temperature fault disables the bus. Thermal
protection also includes hysteresis and blank time before restarting.
• KRx and KTx directly interface to both 5-V and 3.3-V microprocessors without the need for pullup
resistors.
• K-Line continues to function regardless of any TPIC7218-Q1 fault conditions with the exception of VDD
undervoltage reset condition which powers down the entire TPIC7218-Q1 device.
V_BAT
KRx
µP
KTx
DIGITAL CORE
K-LINE
DRIVER/
RECEIVER
ISO-K
DIAGNOSTIC
EQUIPMENT
Figure 5-10. K-Line Application Schematic
Detailed Description
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5.3.11 Warning Lamp Drivers
The TPIC7218-Q1 device features three output pins for warning lamps. The WLQ1 and WLQ2 pins are
high voltage low-side drivers. The WL_LS pin is a low voltage low-side driver.
The WL_LS driver enables whenever the watchdog controlled bit, WD_STAT, is high. This low-side driver
is an open-drain MOSFET; to realize a high logic level and external pullup resistor must be used. Driver
operation is only dependent on a watchdog fault.
The WLQ1 driver enables whenever the WLG1 pin and the GE_9 bit is set. The WLQ2 driver works in the
same way utilizing the WLG2 pin and the GE_10 bit. Each driver is monitored for three fault conditions:
overcurrent, open-load, and over-temperature. However, driver operation also depends on other fault
conditions: VDD undervoltage, and watchdog fault. See the application circuit and register diagram in
Figure 5-11.
WLG1
VBAT
WLG2
DIGITAL CORE
WLQ1
SPI
4
VBAT
nRST
µP
WLQ2
WDin
VIO
WATCHDOG
WL_LS
LOW VOLTAGE WARNING
LAMP DRIVER
Figure 5-11. Warning Lamp Driver Register and Application Circuit Diagram
Each digital driver monitors, reports, and has integrated protection for many electrical fault conditions.
Overcurrents are reported as a 1 in register 0x03, (bits 0 and 2 are referenced by bits F9, F10) and do not
cause the affected driver to disable. Overcurrents are merely reported after a deglitch time of toff_blank_WLQx.
Over-temperature (junction) faults are reported in register 0x03, (bit-6 OTSD) and cause both drivers to
disable after a deglitch time of toff_tmp_WLQx.. The high-voltage warning-lamp drivers are also checked for an
open-load or short to ground condition whenever they are not enabled. This type of fault causes register
0x03, (bits 1 and 3 are referenced by bits S9 and S10) to be reported as a 1. A master low-side fault bit in
register 0x00, (bit-0) becomes high whenever an overcurrent or open-load fault occurs. Faults can be
cleared by reading the appropriate fault reporting register. When this occurs, the low-side master fault bit
(FAIL) can be cleared by reading it.
The high-voltage warning-lamp drivers also respond to fault conditions within other functional blocks.
These drivers are disabled whenever the VDD undervoltage fault bit in register 0x00 is set. Also, a
watchdog fault can cause these drivers to disable, if register 0x11, bit-4 (WD_EN) is set. This bit defaults
to 0 upon power up. Any of these faults do not cause the FAIL bit to be set.
Faults can be cleared by reading the appropriate fault reporting register. When this occurs the digital
drivers can be re-enabled. Fault reporting bits do not have any affect on these warning lamp drivers; only
the actual fault condition causes a driver to disable. Nevertheless, TI recommends clearing the fault bits
by reading them before enabling the drivers.
36
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Aside from monitoring and reporting faults, the high-voltage warning-lamp drivers have overvoltage
protection circuitry built in. An active-clamp monitors voltage on the pins of these drivers. Voltages larger
than Vcl_WLQx are clamped.
5.3.12 Watchdog Operation
The TPIC7218-Q1 device also features watchdog functionality. Watchdog functionality is programmable
and can be disabled. This functional block receives clock pulses from an external microprocessor through
WDIN pin to verify proper system operation. Whenever a watchdog fault occurs, the low-voltage warninglamp pin (WL_LS), the reset pin (nRST), and many of the other functional blocks within the TPIC7218-Q1
device are affected. The TPIC7218-Q1 device can be set to accept a range of different pulse widths for
easy connection to most microprocessors.
If watchdog functionality is enabled (WD_EN = 1), the TPIC7218-Q1 logic monitors WDIN pulse widths by
counting the number of internal clocks that occur between WDIN rising and falling edges. Two, 2-bit
values ( WDH, WDL) can be adjusted to select the length of a valid window range for a WDIN
pulse. Pulse widths inside of this window range are counted as a good pulse. A good pulse increments a
3-bit state machine counter by one (WDCNTx bits, in register 0x05). When a counter value of 7 is
reached, the status bit, WDSTAT , becomes a 1 and all TPIC7218-Q1 watchdog inhibited functionality is
enabled. If a bad pulse occurs then the state machine counter is decremented by three. The WD_FAULT
bit is set whenever the counter value is 0, causing the WD_STAT bit to become low. A fault turns off highside drivers, low-side drivers, wheel-speed functionality, and high-voltage warning-lamp drivers. Both the
low-voltage warning-lamp driver (WL_LS) and the reset pin (nRST) enables. The SPI continues to function
and the WD_FAULT and WDSTAT bits indicate a watchdog fault. When a full watchdog count is reached,
register bits and functionality would return to normal state. Refer to Figure 5-12 through Figure 5-14 for
more details on the state transitions and timing.
If the WDIN pin does not realize a transition after twice the length of time selected in the upper window,
which is set by bits WDH, then an out-of-range condition occurs. The watchdog fault becomes high
and the watchdog status bit becomes low (WD_FAULT = 1, and WDSTAT = 0).
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out-of-range
Single pulse
000
A
RST
on transition to 000
Stat=0
bad
out-of-range
A
001
bad
010
bad
011
bad
good
out-of-range
A
good
out-of-range
A
good
bad
out-of-range
A
100
good
bad
out-of-range
A
101
good
bad
out-of-range
A
110*
(*CNT value on PUC)
good
out-of-range
A
111
Stat=1
Figure 5-12. Watchdog State Transition Diagram
Internal
Clock
Internal
Clock
WDin
WDin
Lower Window
Lower Window
Upper Window
Upper Window
Out-of-range Window
Out-of-range Window
Figure 5-13. Timing Diagram Showing A Bad Pulse
Internal
Clock
WDin
Lower Window
Upper Window
Out-of-range Window
Figure 5-14. Timing Diagram Showing A Good Pulse
38
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5.4
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Device Functional Modes
The device operates in normal mode as described in Section 5.3 unless it is in the reset state.
5.4.1
Device Reset
Several events cause the TPIC7218-Q1 device to reset. For a compete view of TPIC7218-Q1 behavior
during reset, refer to Table 5-1.
Power-On Reset A power-on reset, POR, is caused when the VDD supply voltage falls below the reset
threshold. On POR the nRST pin is pulled low by the TPIC7218-Q1 device.
Watchdog Reset A watchdog reset is initiated whenever the Watchdog counter decrements to 000. Upon
Watchdog Reset, the nRST pin is pulsed low, and the WDSTAT flag is cleared. As the nRST
pin is released, the Watchdog state machine is restarted. The watchdog will re-enable after a
delay time TWD_PULSE to allow sufficient time for the microcontroller to reset.
External Reset An external reset is realized whenever the nRST pin is driven low by an external signal
(usually from a microprocessor). When nRST is released the Erst bit is set, indicating that an
external reset occurred.
5.5
5.5.1
Programming
Serial Peripheral Interface (SPI) Interface To Microcontroller
The TPIC7218-Q1 device uses a SPI communication interface. The TPIC7218-Q1 device operates as a
slave with full-duplex, synchronous, 8-bit transfer frames. The device can be controlled and monitored in
one of three modes: Read, Write, and Dummy. Read command returns data to the master. If a fault
register is read, then any faults will be cleared. However, if the fault still exists then the fault reporting
bit(s) will remain high. A write command sends data to the slave. Data is latched in on the rising edge of
the second chip select. A dummy command is used whenever the master and slave loose
synchronization. This happens whenever the master does not issue a normal 16 bit transfer using two
eight bit frames. Dummy commands essentially reset the SPI logic to the default state.
A typical SPI operation contains two full chip select frames; each containing eight clock pulses. All SPI
transaction starts when CSN transitions to a logic low. During this time 8-bits of mode, R/W, and address
data are clocked into SI. Finally, the CSN returns high, concluding the first half of the normal transaction.
The second half of the normal transaction starts when CSN again transitions to a logic low. During this
time 8-bits of data are clocked into SI. Finally, the CSN returns high, and a normal SPI transaction is
concluded. If one chip-select frame does not have exactly eight clocks, then the whole 16-bit transaction is
considered invalid and is ignored. The CSN must go high for a window of 2 μs to 28 μs (CSNtimeout)
between two 8-bit commands for the 16-bit command to be considered valid. A 16-bit read command
consists of an 8-bit read command of the intended address and an 8-bit dummy command. The SPI can
also operate in burst mode, whereby consecutive 8-bit read commands result in a consecutive 8-bit data
being returned to the master.
Table 5-13. SPI Instruction Encoding
MODE
R/Wn
STAT.
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Unused
0
1
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Read
1
0
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Write
0
0
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Dummy
1
1
X
X
X
X
X
X
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Figure 5-15. One Chip-Select Frame
The SO pin contains the register data in response to the previous eight bit frame. Data out is always
delayed by one SPI transfer (for example, response to the command N is shifted out at the same time
command N+1 is shifted in). Valid data is shifted out from the SO pin on the rising edge of SCLK. The
response to the SPI frame depends on which type of transaction mode is requested by the Master (read,
write, or dummy).
If the SPI transaction is valid, the Slave determines what type of operation is being requested. If a Read
transaction is requested, the Slave responds with the Read byte during the next SPI transaction. Figure 516 shows the SPI Read operation.
Figure 5-16. One Chip-Select Frame
A Write operation places the data byte into the address specified in the previous chip select frame.
Figure 5-17. One Chip-Select Frame
5.5.1.1
Summary and Description Of Control and Reporting Registers
The TPIC7218-Q1 device contains 30 registers that contain both fault reporting and control bits. Refer to
the following tables for register map and functional description of each bit.
40
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5.6
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Register Maps
5.6.1
SPI Registers
Table 5-14. SPI Registers Map
ADDRESS
R/W
b7
b6
b5
b4
b3
b2
b1
b0
0x00
R
HSDC2
FHSD
FOV
FUV
Erst
HSDC1
PORn
FAIL
0x01
R
S4
F4
S3
F3
S2
F2
S1
F1
0x02
R
S8
F8
S7
F7
S6
F6
S5
F5
0x03
R
WS_OV_Cnt
OTSD
WS_Fail_Cnt
KI
S10
F10
S9
F9
0x04
R
WS_Cnt_OUT7
WS_Cnt_OUT6
WS_Cnt_OUT5
WS_Cnt_OUT4
WS_Cnt_OUT3
WS_Cnt_OUT2
WS_Cnt_OUT1
WS_Cnt_OUT0
0x05
R
WSSQ2ILIMIT
WSSQ1ILIMIT
WSSQ2FAULT
WSSQ1FAULT
WDSTAT
WDCNT2
WDCNT1
WDCNT0
0x06
R
VLDDEG
OCPR
STGPR
FGPR
LMR
FGMR
STGMR
OCMR
0x07
R
WSS1D7
WSS1D6
WSS1D5
WSS1D4
WSS1D3
WSS1D2
WSS1D1
WSS1D0
0x08
R
WSS1_Valid3
WSS1_Valid2
WSS1_Valid1
WSS1_Valid0
WSP1_STB
WSS1_Mode
WSS1_New
WSS1D8
0x09
R
WSS2D7
WSS2D6
WSS2D5
WSS2D4
WSS2D3
WSS2D2
WSS2D1
WSS2D0
0x0A
R
WSS2_Valid3
WSS2_Valid2
WSS2_Valid1
WSS2_Valid0
WSP2_STB
WSS2_Mode
WSS2_New
WSS2D8
0x0B
R
WSS3D7
WSS3D6
WSS3D5
WSS3D4
WSS3D3
WSS3D2
WSS3D1
WSS3D0
0x0C
R
WSS3_Valid3
WSS3_Valid2
WSS3_Valid1
WSS3_Valid0
WSP3_STB
WSS3_Mode
WSS3_New
WSS3D8
0x0D
R
WSS4D7
WSS4D6
WSS4D5
WSS4D4
WSS4D3
WSS4D2
WSS4D1
WSS4D0
0x0E
R
WSS4_Valid3
WSS4_Valid2
WSS4_Valid1
WSS4_Valid0
WSP4_STB
WSS4_Mode
WSS4_New
WSS4D8
0x0F
R
WSS4OC
WSS3OC
WSS2OC
WSS1OC
WSS4FAULT
WSS3FAULT
WSS2FAULT
WSS1FAULT
0x10
RW
GE8
GE7
GE6
GE5
GE4
GE3
GE2
GE1
0x11
RW
WD_Fault
0
OV_GMR
WD_EN
GE_PR
GE_MR
GE10
GE9
0x12
RW
WDH
WDH
WDL
WDL
PWMFreq1
PWMFreq0
WS_Cnt _MUX[1]
WS_Cnt _MUX[0]
0x13
RW
PWMQ5
PWMQ5
PWMQ5
PWMQ5
PWMQ5
PWMQ5
PWMQ5
PWMQ5
0x14
RW
0
0
0
0
PWMQ5Phase
PWMQ5Phase
PWMQ5
PWMQ5
0x15
RW
PWMQ6
PWMQ6
PWMQ6
PWMQ6
PWMQ6
PWMQ6
PWMQ6
PWMQ6
0x16
RW
0
0
0
0
PWMQ6Phase
PWMQ6Phase
PWMQ6
PWMQ6
0x17
RW
PWMQ7
PWMQ7
PWMQ7
PWMQ7
PWMQ7
PWMQ7
PWMQ7
PWMQ7
0x18
RW
0
0
0
0
PWMQ7Phase
PWMQ7Phase
PWMQ7
PWMQ7
0x19
RW
PWMQ8
PWMQ8
PWMQ8
PWM4Q8
PWMQ8
PWMQ8
PWMQ8
PWMQ8
0x1A
RW
0
0
0
0
PWMQ8Phase
PWMQ8Phase
PWMQ8
PWMQ8
0x1B
RW
0
WSSP4
WSSP3
WSSP2
WSSP1
WSSTYPE
WSSQ2
WSSQ1
0x1C
RW
OCPRDIS
STGPRDIS
OCMRDIS
STGMRDIS
WSLS4
WSLS3
WSLS2
WSLS1
0x1D
RW/R*
VREFOK*
FGPRDIS
FGMRDIS
LMRDIS
WSP4ILIMIT
WSP3ILIMIT*
WSP2ILIMIT*
WSP1ILIMIT*
Detailed Description
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Table 5-15. Description Of Control and Reporting Bits
BIT NAME
Fail
PORn
HSDC1
Any fault on any digital or PWM low-side driver
0 = Fault not detected
1 = Fault detected
Power-on reset. Reset low when read by microcontroller.
0 = No power-on reset detected. Reset to this value when read by microcontroller.
1 = Power-on reset detected
High-side driver comparator1 for Master Relay (MR)
0 = Comparator output low
1 = Comparator output high
Erst
RST pin is pulled low by external source
0 = Fault not detected
1 = Fault detected
Fuv
Undervoltage on VBAT
0 = Fault not detected
1 = Fault detected
Fov
Overvoltage on VBAT
0 = Fault not detected
1 = Fault detected
FHSD
HSDC2
Any fault on the high-side drivers (either GMR or GPR). If set, this bit is latched until Address 6 is read. Then, it
clears on read.
0 = Fault not detected
1 = Fault detected
High-side driver comparator 2 for Master Relay (MR)
0 = Comparator output low
1 = Comparator output high
Sx
Open-load fault on the low-side output (S9 reports WLQ1 fault and S10 reports WLQ2 fault)
0 = Fault not detected on output x
1 = Fault detected on output x
Fx
Short-to-battery fault on the low-side output (F9 reports WLQ1 fault and F10 reports WLQ2 fault)
0 = Fault not detected on output x
1 = Fault detected on output x
WS_Fail_Cnt
Kl
OTSD
WS_OV_Cnt
42
DESCRIPTION
CNT_EN and CNT_CLR set at the same time
0 = Fault not detected
1 = Fault detected
Status bit for Kline current limit condition
0 = Fault not detected
1 = Fault detected
Any overtemperature fault
0 = Fault not detected
1 = Fault detected
Count overflow on the wheel-speed sensor (past 256)
0 = Overflow not detected
1 = Overflow detected
Detailed Description
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Table 5-15. Description Of Control and Reporting Bits (continued)
BIT NAME
WSSx_Valid4
DESCRIPTION
This word shows the valid number of bits in each wheel-speed channel.
WSSx_Valid3
WSSx_Valid2
WSSx_Valid1
WDCNT0
Status Bit 1 of three that is used to track the operation of the watchdog circuit (LSB)
WDCNT1
Status Bit 2 of three that is used to track the operation of the watchdog circuit
WDCNT2
Status Bit 3 of three that is used to track the operation of the watchdog circuit (MSB)
WDSTAT
Watchdog status bit
0 = Out-of-range
1 = In-range
WSSQ1FAULT
Open load or short to ground on WSSQ1
0 = Fault not detected
1 = Fault detected
WSSQ2FAULT
Open load or short to ground on WSSQ2
0 = Fault not detected
1 = Fault detected
WSSQ1ILIMIT
Overcurrent on WSSQ1
0 = Fault not detected
1 = Fault detected
WSSQ2ILIMIT
Overcurrent on WSSQ2
0 = Fault not detected
1 = Fault detected
OCMR
Overcurrent fault on MR
0 = Fault not detected
1 = Fault detected
STGMR
Short-to-ground fault on MR
0 = Fault not detected
1 = Fault detected
FGMR
LMR
FGPR
GMR disabled by external circuitry
0 = GMR not disabled
1 = GMR disabled
Load-leakage fault on MR (Master Relay)
0 = Fault not detected
1 = Fault detected
GPR disabled by external circuitry
0 = GPR not disabled
1 = GPR disabled
STGPR
Short-to-ground fault on PR
0 = Fault not detected
1 = Fault detected
OCPR
Overcurrent fault on PR
0 = Fault not detected
1 = Fault detected
VLD DEG
This bit is a replica of FOV
WSS1Dx
VDA data bits for wheel-speed channel 1
Detailed Description
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Table 5-15. Description Of Control and Reporting Bits (continued)
BIT NAME
VDA data bits for wheel-speed channel 2
WSS3Dx
VDA data bits for wheel-speed channel 3
WSS4Dx
VDA data bits for wheel-speed channel 4
WSSx_New
Flag bits that notify the availability of new data for each sensor channel
1 = new data since last read was performed
0 = old data since last read was performed
WSSx_Mode
Flag bits that notify the mode of operation for each sensor channel
1 = standstill mode
0 = normal mode
WSPx_STB
Flag bits that show a short to battery for each sensor channel in the off state
1 = short to battery
0 = normal operation
WS_Cnt_OUT7
Bit 7 of wheel-speed counter (value latched at CSN low-to-high transition)
WS_Cnt_OUT6
Bit 6 of wheel-speed counter
WS_Cnt_OUT5
Bit 5 of wheel-speed counter
WS_Cnt_OUT4
Bit 4 of wheel-speed counter
WS_Cnt_OUT3
Bit 3 of wheel-speed counter
WS_Cnt_OUT2
Bit 2 of wheel-speed counter
WS_Cnt_OUT1
Bit 1 of wheel-speed counter
WS_Cnt_OUT0
Bit 0 of wheel-speed counter
WSSxFAULT
WSSxOC
Open load or short to ground on WSSx pins
0 = Fault not detected
1 = Fault detected
Overcurrent fault on WSSx pins
0 = Fault not detected
1 = Fault detected
GE1
Enable and disable digital driver 1. It does not clear on Q1 fault
GE2
Enable and disable digital driver 2. It does not clear on Q2 fault
GE3
Enable and disable digital driver 3. It does not clear on Q3 fault
GE4
Enable and disable digital driver 4. It does not clear on Q4 fault
GE5
Enable and disable digital driver 5. It does not clear on Q5 fault
GE6
Enable and disable digital driver 6. It does not clear on Q6 fault
GE7
Enable and disable digital driver 7. It does not clear on Q7 fault
GE8
Enable and disable digital driver 8. It does not clear on Q8 fault
GE9
Enable and disable warning lamp driver 1. It does not clear on WLQ1 fault
GE10
Enable and disable warning lamp driver 2. It does not clear on WLQ2 fault
GE_MR
Enable and disable Master Relay (GMR). It clears on fault
GE_PR
Enable and disable pump motor relay (GPR). It clears on fault
WD_EN
Watchdog state machine enable.
1 = Enabled; Q1-Q8, GMR, GPR cannot be turned on unless WDSTAT =1
0 = Disabled; Q1-Q8, GMR, GPR can be controlled independent of WDstat. (WDSTAT =0 when
WD_EN=0)
OV_GMR
44
DESCRIPTION
WSS2Dx
Configure the response of GMR FET during overvoltage condition
0 = Maintain the previous state
1 = Disable GMR FET
Detailed Description
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Table 5-15. Description Of Control and Reporting Bits (continued)
BIT NAME
WD_FAULT
DESCRIPTION
Status bit that latches the watchdog fault WDSTAT=0. It clears on read and it is a read only bit
1 = watchdog fault has happened (WDSTAT =0)
0 = no watchdog fault has happened (WDSTAT =1)
WS_Cnt_MUX1
Control bit 1 for wheel-speed sensor multiplexer
WS_Cnt_MUX0
Control bit 0 for wheel-speed sensor multiplexer
PWMFreq
Control bits to set the PWM frequency
WDH
Control bits to set the watchdog upper window range
00 = 64 ms
01 = 32 ms
10 = 16 ms
11 = 8 ms
WDL
Control bits to set the watchdog lower window range
00 = 32 ms
01 = 16 ms
10 = 8 ms
11 = 4 ms
PWMQx
Control bits to set the duty cycle of each PWM channel. When changing from one duty cycle setting to another,
the new setting takes place in the next period.
PWMQxPhase
Control bits to set the phase shift for the PWM drivers
00=0°
01=90°
10=180°
11=270°
WSSQ1
Enable and disable wheel-speed output WSSQ1. It clears only on VBAT overvoltage fault
WSSQ2
Enable and disable wheel-speed output WSSQ1. It clears only on VBAT overvoltage fault
WSSTYPE
Type of sensor used
1 = Active
0 = Intelligent
WSPx
Control bit for the supply of the wheel-speed sensor. It clears only on VBAT overvoltage fault
1 = ON
0 = OFF
WSLSx
Control bit for the supply return of the wheel-speed sensor. It clears only on VBAT overvoltage fault
1 = ON
0 = OFF
STGMRDIS
Enable and disable MR short-to-ground protection (STGMR)
0 = Disabled (default after reset)
1 = Enabled
OCMRDIS
Enable and disable MR overcurrent protection (OCMR)
0 = Disabled (default after reset)
1 = Enabled
STGPRDIS
Enable and disable PR short-to-ground protection (STGPR)
0 = Disabled (default after reset)
1 = Enabled
OCPRDIS
Enable and disable PR overcurrent protection (OCPR)
0 = Disabled (default after reset)
1 = Enabled
Detailed Description
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Table 5-15. Description Of Control and Reporting Bits (continued)
BIT NAME
WSPxILIMIT
46
DESCRIPTION
Current limit fault on WSPx pins (read only bits)
0 = Fault not detected
1 = Fault detected
LMRDIS
Enable and disable MR leakage protection (LMR)
0 = Disabled (default after reset)
1 = Enabled
VREFOK
Status bit that indicates if VREF pin is more than 0.75 V (read only)
0 = VREF pin is less than 0.75 V
1 = VREF pin is more than 0.75 V
Detailed Description
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1
Application Information
The TPIC7218-Q1 device, as typically used in anti-lock braking systems, requires very few external
components; thus, the design is quite simple.
6.2
Typical Application
A simplified application diagram of the TPIC7218-Q1 device Figure 6-1 shows a simplified application
diagram.
Solenoid Valves
VCC3
V Relay
VDD
nRST
Vehicle Wheel Speed
Sensors
V Battery
REF
RLOAD
WSP1
WSLS1
WSS1
4 Channel
Digital On/off
Valve Driver
CLOAD
RLOAD
WSP2
WSLS2
WSS2
WSP3
WSLS3
WSS3
RLOAD
WSP4
WSLS4
WSS4
Pump Motor
FET
Motor FET
Control
CLOAD
RLOAD
Charge
Pump
Pump
Motor
CLOAD
CLOAD
Main Relay
FET
Relay FET
Control
TPIC7218
Wheel Speed
Sensor
Logic
V Relay
WSSOUT1
WSSOUT2
ISOK
K Line
WSSOUT3
To Micro
Cluster
Warning
Lamps
V Battery
Warning Lamp
Driver
WSSOUT4
CNT_CLR
CNT_EN
VREF
VDD
KTx Input
HSPC Input
KRx Output
HSMC Input
CSN Input
SCLK Input
SI Input
V Battery
Watchdog
WSSQ1
4 Channel PWM Valve
Driver
SO Output
WSSQ2
To Micro
To Micro
WDIN
VDD
WL_LS
V Relay
Solenoid Valves
Figure 6-1. Simplified Application Diagram
6.2.1
Design Requirements
The design of the components needed for the wheel speed sensor interface (VREF voltage and RLOAD) is
described in Section 5.3.9. The only other major design requirement is in choice of the resistors connected
to pins controlling the pump relay (PR) and main relay (MR) FETs as shown in Figure 6-2. The choice of
these resistors is described in Section 6.2.2.
Application and Implementation
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DMR, DPR
Motor FET
GMR, GPR
Relay FET
SMR, SPR
Figure 6-2. xPR and xMR Resistors in Application Diagram
6.2.2
Detailed Design Procedure
The resistor RDMR is to be chosen based on the overcurrent detection value needed for the system relay
and pump relay as explained in Section 5.3.8. RSMR resistor value to be chosen to limit the current into the
pin in a reverse battery situation - typically in the 1- to 2-kΩ range. See Section 6.2.2.1 for description of
the GMR and GPR resistor design procedure.
6.2.2.1
Gatedrive circuit Motor FET
When the pump relay driver at the GPR pin is enabled, it is charged in three different ways. The internal
pre-GPR node is shorted to the VBAT supply to give it battery voltage. There are also two current sources
that are then enabled at the same time, IDC_GPR and ITRAN_GPR as shown in Figure 6-3. The IDC_GPR current
is on any time the pump relay is turned ON. The ITRAN_GPR current source is only enabled for a time tSTGPR
after the GPR is turned on. The final voltage will not exceed CHP. The maximum charging time can be
obtained from the electrical characteristics table. The turnon time is set by the charging currents with the
gate resistor not affecting it significantly. A typical turnon timing characteristic is shown in Figure 6-4, in
this case with the IPB 80N06S3L-06 chosen as the pump relay FET.
When the pump relay driver is set to the off state all of the charging paths are disabled and the GPR pin is
shorted to GND. The external gate resistance is the primary determinant of the turnoff time. The gate
resistor should be sized based on the gate characteristics of the chosen FET and the desired turnoff time.
A typical turnoff characteristic with a 10-kΩ resistor is shown in Figure 6-5.
48
Application and Implementation
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HSPC
VBAT
CCHP
GATE DRIVE
150k
CPC
V _ BAT
Enable
V_ BAT
ITRAN _GPR
Enable
I DC_GPR
GPR
SPI
2 .5k
70 u
Disable
GE_motorFET
MOTOR GND
Figure 6-3. Pump Relay Gatedriver Circuit
6.2.2.2
Gatedrive circuit Master Relay FET
The circuit used for the gate drive for the master relay FET is similar to the pump motor FET gatedrive
with changes in the drive strength as reflected in the turnon times from the electrical characteristics table.
The gate resistor for the master relay FET should be chosen using the same procedure as for the pump
motor relay driver.
6.2.3
Application Curves
Figure 6-4. Turnon of the FET Gate With a 10-kΩ Gate Resistor.
Figure 6-5. Turnon of the FET Gate With a 10-kΩ Gate Resistor.
Application and Implementation
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7 Power Supply Recommendations
The TPIC7218-Q1 device requires three power supply input pins – (1) VBAT connected to the automotive
battery, (2) VDD connected to a 5-V regulated output from the battery and (3) VIO which can be optionally
connected to VDD or a 3.3-V regulated output. TI recommends that all power supply pins have decoupling
capacitors. Use good circuit board layout techniques to ensure each capacitor provides instantaneous
peak current to the TPIC7218-Q1 device. Care must be taken to avoid parasitic impedances which can
degrade decoupling performance. Poorly decoupled power pins are likely to cause unsatisfactory EMC
performance. TI recommends the following capacitor values:
• VBAT: recommended, 0.1 µF, X7R, 10%
• VDD: recommended, 0.1 µF, X7R, 10%
• VCC3: required, 100 pF, X7R, 10%
8 Layout
8.1
8.1.1
Layout Guidelines
Local Grounding Configuration
Route the ground pins 6, 24, 29, 30, 31, 32, 37, 63, 64, 69, 70, 71, 72 and 77 directly inward to pad.
Maximize plane area under the TPIC7218-Q1 device to be consistent with PCB design rules. Ensure
proper relief features for soldering thermal pad to plated through holes.
Add additional plated through holes as shown in the sketch to minimize loop area for ground return
currents. See Figure 8-1 for more information.
8.1.2
Board Level Grounding Configuration, TPIC7218-Q1 to System Connector
Ideally the inner PCB layer under the TPIC7218-Q1 device should be dedicated as plane ground, with
direct connection to wiring connector pin to vehicle ground. The layer should cover entire PCB area, with
only clearance holes for vias and so forth. No breaks or divisions. See Figure 8-2 for more information.
8.1.3
VCC3 Bypass Capacitor
Place 0402 package bypass capacitor for VCC3 node to ground as close as possible to the TPIC7218-Q1
device, absolute minimum loop width and trace length. Do not connect ground side of capacitor to any
plane; tie it directly with top layer trace to pin 6 as shown in Figure 8-3. Close placement, minimum loop
area is a priority.
8.1.4
VDD Bypass Capacitor
VDD bypass capacitor needs to be close to the TPIC7218-Q1 device, but not as critical as VCC3 cap. The
orientation and location shown in Figure 8-4 is just an example. Connection between capacitor and ground
node to be made through a through to the inner ground plane layer.
8.1.5
VBAT and CHP Capacitors
Three capacitors are used for bypassing the VBAT node. Prioritize placing an 0402 as close as possible to
pin 59. The other two need to be close but not as critical. Ground capacitors. Capacitor ground needs to
be connected to inner plane. The 0805 package is suitable for the other two capacitors.
Two capacitors are used between pin 59 and 60, and as with VBAT node, the 0402 capacitor needs to be
as close as possible to the TPIC7218-Q1 device. The 0805 package is suitable for the other capacitor.
See Figure 8-5 for more information.
50
Layout
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8.1.6
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Multiple Plane Layer Assignments
Place components associated with VCC3 (pin 3), VDD (pin 9), VBAT (pin 59), CHP (pin 60), DMR (pin
55), SMR (pin 56), GMR (pin 57), GPR (pin 58), SPR (pin 61) and DPR (pin 62) on top layer. Assign first
PCB layer under the top layer as an overall ground plane.
Placing components on top-side of board and assigning first inner layer as ground plane minimizes the
path length and loop area for EMC bypassing. See Figure 8-6 for more information.
8.1.7
Duplicate Pad Under TPIC7218-Q1 on All Non-Ground Plane Inner Layers
Duplicate the top layer pad underneath the TPIC7218-Q1 device on all of the inner layers. For the first
inner ground plane layer, entire plane is ground except for clearances around holes and unconnected
vias. Bottom layer copper pad directly under the TPIC7218-Q1 device is sized and has relief features as
required for the thermal slug. See Figure 8-6 for more information.
8.1.8
Flooding
Flooding places copper on all available area, subject to the clearance rules for the manufacture of the
PCB. Flooded areas should be connected by vias to the inner ground plane layer. Small, insignificant
flooded zones may be left unconnected or deleted from the design.
The additional copper connected to ground augments the effectiveness of the inner ground plane layer by
providing parallel paths, and also improves heat sink performance by increasing the thermal mass of the
PCB. See Figure 8-7 for more information.
Layout
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80 79 78
76 75 74 73
68 67 66 65
Pin 63, PGND5
Pin 64, PGND5
Pin 69, PGND6
Pin 70, PGND6
Pin 71, PGND7
Pin 72, PGND7
Layout Example
Pin 77, PGND8
8.2
www.ti.com
62 61
1
60
2
59
3
58
4
57
5
56
7
54
55
Pin 6,GND
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
41
Pin 32, PGND2
Pin 31, PGND2
Pin 30, PGND3
33 34 35 36
Pin 29, PGND3
Pin 24, PGND4
25 26 27 28
38 39 40
Pin 37, PGND1
20
21 22 23
Figure 8-1. Local Grounding Configuration Layout Example
PCB
TPIC7218
System Connector
Figure 8-2. Board Level Grounding Configuration, TPIC7218-Q1 to System Connector Layout Example
52
Layout
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80 79 78
Minimize Trace Loop Area
76 75 74 73
Pin 63, PGND5
Pin 64, PGND5
Pin 69, PGND6
Pin 70, PGND6
Pin 71, PGND7
Pin 72, PGND7
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Pin 77, PGND8
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68 67 66 65
62 61
1
60
2
59
3
58
4
57
5
56
Pin 6,GND
55
54
Pin 7,VCC3
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
41
Pin 32, PGND2
Pin 31, PGND2
Pin 30, PGND3
33 34 35 36
Pin 29, PGND3
Pin 24, PGND4
25 26 27 28
38 39 40
Pin 37, PGND1
20
21 22 23
Figure 8-3. VCC3 Bypass Capacitor Layout Example
Layout
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TPIC7218-Q1
80 79 78
76 75 74 73
68 67 66 65
Pin 63, PGND5
Pin 64, PGND5
Pin 69, PGND6
Pin 70, PGND6
Pin 71, PGND7
Pin 72, PGND7
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Pin 77, PGND8
SLDS182A – AUGUST 2010 – REVISED JULY 2015
62 61
1
60
2
59
3
58
4
57
5
56
Pin 6,GND
55
54
Pin 7,VCC3
8
53
52
Pin 9,VDD
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
41
Pin 32, PGND2
Pin 31, PGND2
33 34 35 36
Pin 30, PGND3
Pin 24, PGND4
25 26 27 28
38 39 40
Pin 37, PGND1
20
21 22 23
Pin 29, PGND3
Ground connection by via
to inner plane
10
Figure 8-4. VDD Bypass Capacitor Layout Example
54
Layout
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TPIC7218-Q1
80 79 78
76 75 74 73
68 67 66 65
Pin 63, PGND5
Pin 64, PGND5
Pin 69, PGND6
Pin 70, PGND6
Pin 71, PGND7
Pin 72, PGND7
SLDS182A – AUGUST 2010 – REVISED JULY 2015
Pin 77, PGND8
www.ti.com
Pin 60,CHP
62 61
1
Pin 59,VBAT
2
3
58
4
57
5
56
Ground connection by via
to inner plane
55
Pin 6,GND
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
21 22 23
41
38 39 40
Pin 37, PGND1
Pin 32, PGND2
Pin 31, PGND2
Pin 30, PGND3
33 34 35 36
Pin 29, PGND3
Pin 24, PGND4
25 26 27 28
0402 capacitors as close as
possible
Figure 8-5. VBAT and CHP Capacitors Layout Example
Top
Inner layer 1 ground plane
Inner layer 2
Inner layer 3
Inner layer 4
Inner layer 5
Bottom
TPIC7218
Thermal Slug
Note short path
back to ground
Figure 8-6. Multiple Plane Layer Assignments Layout Example
Layout
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TPIC7218-Q1
SLDS182A – AUGUST 2010 – REVISED JULY 2015
www.ti.com
TPIC7218
Top
Inner layer 1 ground plane
Inner layer 2
Inner layer 3
Inner layer 4
Inner layer 5
Bottom
Thermal Slug
Figure 8-7. Thermal Slug Layout Example
9 Device and Documentation Support
9.1
9.1.1
Documentation Support
Related Documentation
For related documentation see the following: TPIC7218-Q1 Thermal Design Considerations and Solution,
SLDA013
9.2
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools
and contact information for technical support.
9.3
Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
56
Device and Documentation Support
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Product Folder Links: TPIC7218-Q1
TPIC7218-Q1
www.ti.com
9.4
SLDS182A – AUGUST 2010 – REVISED JULY 2015
Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.5
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2015, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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57
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPIC7218QPFPRQ1
ACTIVE
HTQFP
PFP
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPIC7218Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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