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TPIC74101-Q1
SLIS140A – OCTOBER 2011 – REVISED DECEMBER 2014
TPIC74101-Q1 Buck and Boost Switch-Mode Regulator
1 Features
3 Description
•
•
The TPIC74101-Q1 is a switch-mode regulator with
integrated switches for voltage-mode control. With the
aid of external components (LC combination), the
device regulates the output to 5 V ±2% for a wide
input-voltage range.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device HBM ESD Classification level 1B for
pin 7 (L2), pin 8 (VOUT), pin 9 (5Vg)
– Device HBM ESD Classification 2 for pins 1–6
and 10–20
– Device CDM ESD Classification Level C4B
Switch-Mode Regulator
– 5 V ±2%, Buck Mode
– 5 V ±3%, Low-Power or Boost or Boost/buck
Crossover Mode
Switching Frequency, 380 kHz (typical)
Input Operating Range, 1.5 V to 40 V, (Vdriver)
– 1-A Load-Current Capability
– 200-mA Load-Current Capability Down to 2-V
Input (Vdriver)
– 120-mA Load-Current Capability Down to
1.5-V Input (Vdriver)
Enable Function
Low-Power Operation Mode
Switched 5-V Regulated Output on 5Vg With
Current Limit
Programmable Slew Rate and Frequency
Modulation for EMI Consideration
Reset Function With Deglitch Timer and
Programmable Delay
Alarm Function for Undervoltage Detection and
Indication
Thermally Enhanced Package for Efficient Heat
Management
The TPIC74101-Q1 offers a reset function to detect
and indicate when the 5-V output rail is outside of the
specified tolerance. This reset delay is programmable
using an external timing capacitor on the RESET Pin.
Additionally, an alarm (AOUT) feature is activated
when the input supply rail Vdriver is below a prescaled
specified value (set by the AIN pin).
The TPIC74101-Q1 has a frequency-modulation
scheme to minimize EMI. The clock modulator
permits a modulation of the switching frequency to
reduce interference energy in the frequency band.
The 5Vg output is a switched 5-V regulated output
with internal current limiting to prevent RESET from
being asserted when powering a capacitive load on
the supply line. This function is controlled by the
5Vg_ENABLE Pin. If there is a short to ground on this
output (5Vg output), the output self-protects by
operating in a chopping mode. This does, however,
increase the output ripple voltage on VOUT during this
fault condition.
Device Information(1)
PART NUMBER
TPIC74101-Q1
BODY SIZE (NOM)
HTSSOP (20)
6.50 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
22 µH–100 µH
2 Applications
•
•
PACKAGE
4.7 nF
4.7 nF
L1
L2
Cboot1
Automotive Infotainment & Cluster
Body Electronics
VOUT
5V
22 µF–470 µF
Cboot2
L
Vbattery
Vdriver
C
5Vg
R2
5V
AIN
1 µF–100 µF
R1
TPIC74101-Q1
5V
ENABLE
5 kW
Vlogic
470 nF
Optional
Connection
RESET
5 kW
5Vg_ENABLE
REST
2.2 nF–150 nF
CLP
AOUT
SCR1
SCR0
Rmod
12 kW
GND
PGND
S0183-01
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC74101-Q1
SLIS140A – OCTOBER 2011 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Dissipation Rating .....................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 25
11.1 Trademarks ........................................................... 25
11.2 Electrostatic Discharge Caution ............................ 25
11.3 Glossary ................................................................ 25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Original (October 2011) to Revision A
•
2
Page
Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLIS140A – OCTOBER 2011 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
20-PINS
PWP HTSSOP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
SCR1
Cboot2
Cboot1
Vdriver
L1
PGND
L2
VOUT
5Vg
AIN
20
19
18
17
16
15
14
13
12
11
SCR0
5Vg_ENABLE
ENABLE
Vlogic
GND
Rmod
REST
AOUT
RESET
CLP
P0021-02
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
SCR1
1
I
Programmable slew-rate control
Cboot2
2
I
External bootstrap capacitor
Cboot1
3
I
External bootstrap capacitor
Vdriver
4
I
Input voltage source
L1
5
I
Inductor input (an external Schottky diode (1) to GND must be connected to L1)
PGND
6
I
Power ground
L2
7
I
Inductor output
VOUT
8
O
5-V regulated output
5Vg
9
O
Switched 5-V supply
AIN
10
I
Programmable alarm setting
CLP
11
I/O
Low-power operation mode (digital input)
RESET
12
O
Reset function (open drain)
AOUT
13
O
Alarm output (open drain)
REST
14
O
Programmable reset timer delay
Rmod
15
I
Main switching frequency modulation setting to minimize EMI
GND
16
I
Ground
Vlogic
17
O
Supply decoupling output (may be used as a 5-V supply for logic-level inputs)
ENABLE
18
I
Switch-mode regulator enable/disable
5Vg_ENABLE
19
I
Switched 5-V voltage regulator output enable/disable
SCR0
20
I
Programmable slew-rate control
Exposed thermal pad of the package should be connected to GND or left floating.
(1)
Maximum 0.4 V at 1 A and 125°C
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SLIS140A – OCTOBER 2011 – REVISED DECEMBER 2014
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6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating free-air temperature range (unless otherwise noted) (1)
Unregulated input voltage, V(driver)
(2)
Unregulated inputs, V(AIN), V(ENABLE)
(2)
MIN
MAX
UNIT
–0.5
40
V
–0.5
40
V
Bootstrap
voltages
V(Cboot1)
52
V
V(Cboot2)
14
V
Switch mode
voltages
V(L1)
–1
40
V
V(L2)
–1
7
V
–0.5
7
V
–0.5
7
V
Logic input voltages, V(Rmod),V(SCR0),V(SCR1),V(CLP), and V(5Vg_ENABLE)
Low output voltages, V(RESET),V(AOUT),V(logic), and V(REST)
(2)
(2)
Continuous power dissipation, PD
See Dissipation Rating
Operating virtual junction temperature range, TJ
–40
150
°C
Operating ambient temperature range, TA
–40
125
°C
260
°C
125
°C
Lead temperature (soldering, 10 s), T(LEAD)
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to ground.
6.2 ESD Ratings
VALUE
Human body model (HBM), per JEDEC
V(ESD)
Electrostatic
discharge
Charged device model (CDM), per JEDEC
Pin 7 (L2), pin 8 (VOUT), Pin 9 (5Vg)
±800
Pins 1–6 and 10–20
±2000
Corner pins (SCR1, AIN, SCR0, and
CLP)
±750
Other pins
±750
UNIT
V
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Unregulated input voltage, V(driver)
6
24
V
Unregulated input voltages, V(AIN) and V(ENABLE)
0
24
V
V(L1)
–1
17
V(L2)
5
5.5
Switch-mode pins
Bootstrap voltages
V(Cboot1)
V(driver) + 10
V(Cboot2)
8
Logic levels (I/O), V(Rmod), V(logic),V(SCR0),V(SCR1),V(5Vg_ENABLE),V(RESET), V(AOUT), V(CLP),
and V(REST)
Operating ambient temperature range, TA
Logic levels (I/O), V(SCR0), V(SCR1), V(CLP) directly connected to V(logic)
4
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0
V
V
5.25
V
–40
125
°C
V(logic)
V(logic)
V
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SLIS140A – OCTOBER 2011 – REVISED DECEMBER 2014
6.4 Thermal Information
TPIC74101-Q1
THERMAL METRIC (1)
PWP
UNIT
20 PINS
RθJA (2)
Junction-to-ambient thermal resistance
32
(3)
RθJA
Junction-to-ambient thermal resistance
37.9
RθJC(top)
Junction-to-case (top) thermal resistance
22.7
RθJB
Junction-to-board thermal resistance
20.2
ψJT
Junction-to-top characterization parameter
0.7
ψJB
Junction-to-board characterization parameter
19.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.8
(1)
(2)
(3)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The thermal data is based on using 2-oz copper trace with at least four square inches of copper footprint for heat dissipation. The
copper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated.
The thermal data is based on using 1-oz copper trace with at least four square inches of copper footprint for heat dissipation. The
copper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated.
6.5 Dissipation Rating
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
32°C/W
3.9 W
40°C/W
3.125 W
RθJA
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
31.25 mW/°C
2.03 W
0.781 W
25 mW/°C
1.625 W
0.625 W
6.6 Electrical Characteristics
V(driver) = 6 V to 17 V, TA = -40°C to 125°C, unless otherwise noted
PARAMETERS
TEST CONDITIONS
V(driver)
Unregulated input voltage
V(driver)
Start-up condition voltage
SOM
Soft-start ramp
I(standby)
Standby current
ENABLE = low
Iq
Quiescent current
CLP = 0 V, V(driver) = 11 V, IO = 0 mA
VO
Output voltage
DC
MIN
TYP
1.5
IO = 600 mA
MAX
UNIT
40
V
5
V
CO = 36 μF (min) to 220 μF (max)
4
20
CO = 220 μF (min) to 470 μF (max) (1)
2
20
V/ms
10
20
μA
110
160
μA
5
V
Buck mode
2%
3%
VO
Output-voltage tolerance
Low-Power or Boost or Boost/buck
crossover mode
IO
Output current
V(driver)≥ 7 V
V(driver) = 2 V, see Note
1
(2)
200
A
IO(Boost)
Output current, boost mode
IPPn
Internal peak current limit (normal mode)
(1)
1.75
2.5
A
IPPl
Internal peak current limit (low-power
mode)
(1)
0.75
1.25
A
IP
Peak current
V(driver) = 16 V, IO = 1 A, and L = 33 μH
V(driver)
Boost/buck crossover voltage window
See Note
Tot
Thermal shutdown (4)
(1)
(2)
(3)
(4)
V(driver)= 1.5 V, see Note
(2)
(3)
120
mA
1.5
5
160
180
A
5.9
V
200
°C
Ensured by characterization
Tested with inductor having following characteristics: L = 33 μH, Rmax = 0.1 Ω, IR = 1.8 A. Output current must be verified in application
when inductor Rmax (ESR) is increased.
Ensured by characterization. For further details, see the Buck/Boost Transitioning section.
Ensured by characterization; hysteresis 15°C (typical)
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Electrical Characteristics (continued)
V(driver) = 6 V to 17 V, TA = -40°C to 125°C, unless otherwise noted
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
140
225
mΩ
400
mA
5Vg OUTPUT AND ENABLE
rDS(on)
On-state resistance
IO
Output current
VI
5Vg_ENABLE input-voltage range
VO
V
VIH
5Vg_ENABLE threshold high voltage
V(5Vg) = 5 V
2.5
3
3.5
V
VIL
5Vg_ENABLE threshold low voltage
V(5Vg) = 0 V
1.5
2
2.5
V
V(hys)
Hysteresis voltage
0.5
1
r(pd)
Internal pulldown resistor
300
500
VI
ENABLE input-voltage range
–0.5
VIH
ENABLE threshold high voltage
VIL
ENABLE threshold low voltage
V(hys)
Hysteresis voltage
–0.5
V
850
kΩ
40
V
ENABLE
8 V ≤ V(driver) ≤ 17 V
2.5
3
3.5
6 V ≤ V(driver) < 8 V
1.9
2.5
3.5
VO = 5 V
1.5
1.85
2.5
8 V ≤ V(driver) ≤ 17 V
0.5
1
6 V ≤ V(driver) < 8 V
0.1
V
V
V
RESET
V(th)
RESET threshold voltage
V(RESET)
RESET tolerance
t(RESET)
RESET time
VOL
RESET output low voltage
t(deglitch)
RESET deglitch time
4.51
4.65
4.79
8
10
12
80
100
120
V
3%
C(REST) = 10 nF
C(REST)= 100 nF, see Note
(1)
Isink = 5 mA
450
Isink = 1 mA
84
See Note (1)
8
ms
mV
10
12.5
μs
ALARM
VI
Alarm input-voltage range
40
V
VIL
Alarm threshold low voltage
2.2
2.3
2.35
V
VIH
Alarm threshold high voltage
2.43
2.5
2.58
V
V(hys)
Hysteresis voltage
VOL
Alarm output low voltage
–0.5
240
mV
Isink = 5 mA
450
Isink = 1 mA
84
mV
LOW-POWER MODE (PULSE MODE) PFM
IO(LPM)
Load current in low-power mode
V(driver) < 7 V
II(avg)
Average input current
V(driver) = 11 V, IO = 5 mA, CLP = low
VO
Output-voltage tolerance
VO = 5 V
2.4%
50
mA
3.55
mA
3%
DIGITAL LOW-POWER MODE (CLP)
VIH
High-level CLP input threshold voltage
Normal mode
VIL
Low-level CLP input threshold voltage
Low-power mode
2.6
V
1.15
V
SWITCHING PARAMETERS
f(sw)
Switching frequency
V(Rmod) = 0 V, modulator OFF
f(sw)ac
Operating-frequency accuracy
f(sw) = 380 kHz
f(sw)min
Modulation minimum frequency
230
285
385
kHz
f(sw)max
Modulation maximum frequency
390
480
590
kHz
f(mod)span
Modulation span
f(mod)
Modulation frequency
f(mod)ac
Modulation-frequency accuracy
6
380
kHz
20%
220
Rmod = 12 kΩ ±1%
kHz
28
kHz
12%
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6.7 Typical Characteristics
(Reference L1 Pin, see Figure 10 through Figure 12)
1.0
6
V(driver) = 11 V
V(driver) = 11 V
0.9
0.8
II − Input Current − mA
II − Input Current − mA
5
4
Maximum
3
TA = 125°
TA = 25°
2
0.7
0.6
Maximum
0.5
TA = 125°
0.4
TA = 25°
0.3
0.2
1
0.1
0.0
0.0
0
0
1
2
3
4
5
6
7
8
9
IO − Output Current − mA
10
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
IO − Output Current − mA
G001
1.0
G002
Maximum characteristic specified by design.
IO = 0 mA–1 mA
Maximum characteristic specified by design.
IO = 0 mA–10 mA
Figure 2. Low-Power-Mode Current
Figure 1. Low-Power Mode Current
1100
1000
IO − Output Current − mA
900
TA = 25°
800
V(L1)
700
600
TA = 125°
500
400
Input Current
(200 mA/div)
300
200
100
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
VI − Input Voltage − V
9.5 10.0
G003
(1) Typical representation of input voltage vs output load current at
TA = 25°C and 125°C, after the correct power-up sequence is
invoked.
(2) The dip in the output current at 5.8 V is caused by the
buck/boost transition of the IC.
(3) The output current is clipped to 1 A by the measurement setup.
Figure 3. Typical Input Voltage (V(driver)) vs
Maximum Output Load Current (IO)
G005
\
SCR0 = 0, SCR1 = 0, Input-Current Slew Rate = 2.8 A/μs,
IL = 500 mA, V(driver) = 15 V
Figure 4. Input Current With Slope Control
G011
G010
SCR1 = 0, SCR0 = 1, Input-Current Slew Rate = 6.25 A/μs,
IL = 500 mA, V(driver) = 15 V
Figure 5. Input Current With Slope Control
SCR1 = 1, SCR0 = 0, Input-Current Slew Rate = 9.4 A/μs,
IL = 500 mA, V(driver) = 15 V
Figure 6. Input Current With Slope Control
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Typical Characteristics (continued)
(Reference L1 Pin, see Figure 10 through Figure 12)
G009
G008
SCR0 = 1, SCR1 = 1, Input-Current Slew Rate = 18.8 A/μs,
IL = 500 mA, V(driver) = 15 V
Figure 7. Input Current With Slope Control
IL = 15 mA, CO = 47 μF
Figure 8. Low-Power-Mode Operation
G013
G012
IL = 200 mA
Rmod = 12 kΩ, IL = 200 mA
Figure 9. Nominal Switching Frequency of Q1 Switch
(446 kHz) with Modulation Function Disabled
Figure 10. Minimum Switching Frequency (333 kHz)
With Modulation Enabled
G007
G006
Rmod = 12 kΩ, IL = 200 mA
Figure 11. Maximum Switching Frequency (555 kHz)
with Modulation Enabled
8
Figure 12. Modulation Frequency (Full Span) of 28 kHz
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Typical Characteristics (continued)
(Reference L1 Pin, see Figure 10 through Figure 12)
VO
11 V, IL = 700 mA
V(driver)
5V, IL = 700 mA
2V, IL = 225 mA
G015
G014
IL = 400 mA
Figure 14. Switch-Mode Regulator Transition From Buck
Mode to Boost Mode
Figure 13. Input Voltage Excursions (Similar to Low-Crank
Conditions)
Modulation Off
LO G 10 dB /div
Modulation = 28 kHz
G017
G016
.
IL = 400 mA
These values represent conducted EMI results of a test board for
display purposes only. Actual results may vary greatly depending
on board layout and external components and must be verified in
actual application
LO G 10 dB /div
Figure 15. Switch-Mode Regulator Transition From Boost
Mode to Buck Mode
Figure 16. Conducted Emissions on Test Board Showing
Effects of Switching-Frequency Modulation
Slew Rate = 11
Slew Rate = 00
G018
These values represent conducted EMI results of a test board for display purposes only. Actual results may vary greatly depending on
board layout and external components and must be verified in actual application.
Figure 17. Conducted Emissions on Test Board Showing Effects of Minimum and Maximum Slew Rate Settings
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7 Detailed Description
7.1 Overview
The TPIC74101-Q1 is a buck/boost switch-mode regulator that operates in a power-supply concept to ensure a
stable output voltage with input voltage excursions and specified load range.
The device provides an alarm indicator and reset output to interface with systems that require supervisory
function.
The switching regulator offers a clock modulator and a current-mode slew-rate control for the internal switching
transistor (Q1) to minimize EMI.
An internal low-rDS(on) switch has a current-limit feature to prevent inadvertent reset when turning on the 5Vg
output.
7.2 Functional Block Diagram
Cboot1
Q1
Vdriver
L
Osc
Vreg
Vbattery
Charge
Pump
L1
External Schottky
Diode Required,
Max. 0.4 V
4.7 nF
@1A
@ 125ºC
Q2
22 mH–
100 mH
C
L2
ENABLE
Switch-Mode
Controller With
Dead Time
Vlogic
R2
470 nF
Cboot2
Bandgap
Ref
Q4
AIN
Rmod
R1
4.7 nF
Q3
-
Clock
Modulator
+
12 kW
+
5Vg_ENABLE
VOUT
PGND
Vref
Inrush
Current Limit
5Vg
-
Low-Power Mode
Digital Signal
CLP
Shutdown
Regulator
Low-Power
Mode
Control
Bandgap
Ref
5Vg_Supply
1 µF–100 µF
SCR0
Slew Rate
Control
22 µF–470 µF
Charge
Pump
+
SCR1
5 V Supply
AOUT
Temp
Monitor
POR With
Delay Timer
GND
5 kW
5 kW
RESET
REST
2.2 nF–150 nF
B0130-01
NOTE: All component values are typical.
10
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7.3 Feature Description
7.3.1 Switch-Mode Input/Output Pins (L1, L2)
The external inductor for the switch-mode regulator is connected between pins L1 and L2. This inductor is placed
close to the pins to minimize parasitic effects. For stability, an inductor with 20 μH to 100 μH should be used.
7.3.2 Supply Pin (Vdriver)
The input voltage of the device is connected to the Vdriver pin. This input line requires a filter capacitor to minimize
noise. A low-ESR aluminum or tantalum input capacitor is recommended. The relevant parameters for the input
capacitor are the voltage rating and RMS current rating. The voltage rating should be approximately 1.5 times the
maximum applied voltage for an aluminum capacitor and 2 times for a tantalum capacitor. In buck mode, the
ǸD * D2
RMS current is I OUT
, where D is the duty cycle and its maximum RMS current value is reached when
D = 50% with IRMS = IOUT/2. In boost mode, the RMS current is 0.3 × ΔI, where ΔI is the peak-to-peak ripple
current in the inductor. To achieve this, ESR ceramic capacitors are used in parallel with the aluminum or
tantalum capacitors.
7.3.3 Internal Supply Decoupling Pin (Vlogic)
The Vlogic pin is used to decouple the internal power-supply noise by use of a 470-nF capacitor. This pin can also
be used as an output supply for the logic-level inputs for this device (SCR0, SCR1, ENABLE, CLP, and
5Vg_ENABLE).
7.3.4 Input Voltage Monitoring Pin (AIN)
The AIN pin is used to program the threshold voltage for monitoring and detecting undervoltage conditions on the
input supply. A maximum of 40 V may be applied to this pin and the voltage at this pin may exceed the V(driver)
input voltage without effecting the device operation. The resistor divider network is programmed to set the
undervoltage detection threshold on this pin (see the application schematic). The input has a typical hysteresis of
200 mV with a typical upper limit threshold of 2.5 V and a typical lower limit threshold of 2.3 V. When V(AIN) falls
below 2.3 V, V(AOUT) is asserted low; when V(AIN) exceeds 2.5 V, V(AOUT) is in the high-impedance state.
The equations to set the upper and lower thresholds of V(AIN) are:
.
Upper:
V(driver) = 2.5 V ×
Lower:
V(driver) = 2.3 V ×
R1 + R2
R1
R1 + R2
R1
(1)
7.3.5 Input Undervoltage Alarm Pin (AOUT)
The AOUT pin is an open-drain output that asserts low when the input voltage falls below the set threshold on the
AIN input.
7.3.6 Reset Delay Timer Pin (REST)
The REST pin sets the desired delay time to assert the RESET pin low after the 5-V supply has exceeded 4.65 V
(typical). The delay can be programmed in the range of 2.2 ms to 150 ms using capacitors in the range of 2.2 nF
to 150 nF. The delay time is calculated using the following equation:
RESET delay = C(REST) × 1 ms, where C(REST) has nF units
7.3.7 Reset Pin (RESET)
The RESET pin is an open-drain output. The power-on reset output is asserted low until the output voltage
exceeds the 4.65-V threshold and the reset delay timer has expired. Additionally, whenever the ENABLE pin is
low, RESET is immediately asserted low regardless of the output voltage.
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Feature Description (continued)
7.3.8 Main Regulator Output Pin (VOUT)
The VOUT pin is the output of the switch-mode regulated supply. This pin requires a filter capacitor with low-ESR
characteristics to minimize output ripple voltage. For stability, a capacitor with 22 μF to 470 μF should be used.
The total capacitance at pin VOUT and pin 5Vg must be less than or equal to 470 μF.
7.3.9 Low-Power-Mode Pin (CLP)
The CLP pin controls the low-power mode of the device. An external low digital signal switches the device to lowpower mode or normal mode when the input is high.
7.3.10 Switch-Output Pin (5Vg)
The 5Vg pin switches the 5-V regulated output. The output voltage of the regulator can be enabled or disabled
using this low-rDS(on) internal switch. This switch has a current-limiting function to prevent generation of a reset
signal at turnon caused by the capacitive load on the output or overload condition. When the switch is enabled,
the regulated output may deviate and drop momentarily to a tolerance of 7% until the 5Vg capacitor is fully
charged. This deviation depends on the characteristics of the capacitors on VOUT and 5Vg.
7.3.11 5Vg-Enable Pin (5Vg_ENABLE)
The 5Vg_ENABLE is a logic-level input for enabling the switch output on 5Vg.
For the functional pin, 5Vg_ENABLE results in Table 1:
Table 1. 5Vg_ENABLE, Functional Pin
12
5Vg_ENABLE
FUNCTION
0
5Vg is off
Open (internal pulldown = 500 kΩ)
5Vg is off
1
5Vg is on
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Vdriver
Q1
Peak Current Limit
Switch
Control
Slew Rate Control
L1
Buck/Boost
33 µH
L2
Q4
VOUT
Gate Driver
Q3
47 µF
Q2
Gate
Driver
VOUT
5Vg
5Vg
Charge Pump
typ ~VOUT – 100 mV
100 µF
VOUT
RESET
typ 4.65 V
RESET Deglitch
5Vg_ENABLE
RESET
S0174-01
Figure 18. Current-Limit Switched Output 5Vg
7.3.12 Slew-Rate Control Pins (SCR0, SCR1)
The slew rate of the switching transistor Q1 is set using the SCR0 and SCR1 pins.
Table 2 shows the values of the slew rate (SR):
Table 2. Slew Rate Values (SR)
SCR1
SCR0
0
0
SRQ1
Slow
0
1
Medium-slow
1
0
Medium-fast
1
1
Fast
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See the converter efficiency plots in the Typical Characteristics section to determine power dissipation.
7.3.13 Modulator Frequency Setting (Pin Rmod)
The Rmod pin adjusts the clock modulator frequency. A resistor of Rmod = 12 kΩ generates a modulation
frequency of 28 kHz. The modulator function may be disabled by connecting Rmod to GND and the device
operates with the nominal frequency. The modulator function cannot be activated during IC operation, only at IC
start-up.
7.3.14 Ground Pin (PGND)
The PGND pin is the power ground for the device.
7.3.15 Enable Pin (ENABLE)
The ENABLE pin allows the enabling and disabling of the switch mode regulator. A maximum of 40 V may be
applied to this pin to enable the device and increasing it above the V(driver) input voltage does not affect the
device operation.
Table 3 describes the functionality of the ENABLE pin.
Table 3. Functionality of the ENABLE Pin
ENABLE
FUNCTION
0
Vreg is off.
Open
Undefined
1
Vreg is on.
7.3.16 Bootstrap Pins (Cboot1 and Cboot2)
An external bootstrap capacitor is required for driving the internal high-side MOSFET switch. A 4.7-nF ceramic
capacitor is typically required.
7.4 Device Functional Modes
7.4.1 Clock Modulator
To minimize EMI issues associated with the switch-mode regulator, the device offers an integrated clock
modulator. The function of the clock modulator is to modulate the switching frequency and to distribute the
energy over the wave band.
The average switching frequency is 380 kHz (typical) and varies between 285 kHz and 480 kHz at a rate set by
the Rmod resistor. A typical value of 12 kΩ on the Rmod pin relates to a 28-kHz modulation frequency. The clock
modulator function can only be activated during IC start-up, not during IC operation.
Equation 2 is for the modulation frequency.
f(mod) (Hz) = (–2.2 × Rmod) + 54.5 kHz,
(2)
when Rmod = 8 kΩ to 16 kΩ. Bigger resistor values like 100 kΩ are also allowed for Rmod.
7.4.2 Buck/Boost Transitioning
The operation mode switches automatically between buck and boost modes depending on the input voltage of
V(driver) and output load conditions. During start up, when V(driver) is less than 5.8 V (typical), the device starts in
boost mode and continues to run in boost mode until V(driver) exceeds 5.8 V; at which time, the device switches
over to buck mode. In buck mode, the device continues to run in buck mode until it is required to switch back to
boost to hold regulation. This crossover window to switch to boost mode is when V(driver) is between 5.8 V and
5 V and depends on the loading conditions. When Vdriver drops below 5.8 V but the device is holding regulation
(~2%), the device remains in buck mode. However, when V(driver) is within the 5.8-V to 5-V window and VOUT
drops to 4.9 V, the device crosses over to boost mode to hold regulation. In boost mode, the device remains in
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Device Functional Modes (continued)
boost mode until V(driver) exceeds 5.8 V; at which time, the device enters the buck mode. When the device is
operating in boost mode and V(driver) is in the crossover window of 5.8 V to 5 V, the output regulation may contain
a higher than normal ripple and only maintain a 3% tolerance. This ripple and tolerance depends on the loading
and improves with a higher loading condition. When the device is operated with low-power mode active (CLP =
low) and high output currents (>50 mA), the buck/boost transitioning can cause a reset signal at the RESET pin.
7.4.3 Buck SMPS
In buck mode, the duty cycle of transistor Q1 sets the voltage VOUT. The duty cycle of transistor Q1 varies 10%
to 99% depending on the input voltage, V(driver). If the peak inductor current (measured by Q1) exceeds 450 mA
(typical), Q2 is turned on for this cycle (synchronized rectification). Otherwise, the current recirculates through Q2
as a free-wheeling diode. The detection for synchronous or asynchronous mode is done cycle-by-cycle.
To avoid a cross-conduction current between Q1 and Q2, an inherent delay is incorporated when switching Q1
off and Q2 on and vice versa.
In buck mode, transistor Q3 is not required and is switched off. Transistor Q4 is switched on to reduce power
dissipation.
The switch timings for transistors Q3 and Q4 are not considered. In buck mode, the logical control of the
transistors does not change.
Vdriver
Input
Voltage
SMPS
Q1
Current
Control
L1
Q2
33 µH
Switch
Control
L2
Q4
VOUT
Q3
22 µF–470 µF
FB
S0182-01
Figure 19. Buck/Boost Switch Mode Configuration
7.4.4 Boost SMPS
In boost mode, the duty cycle of transistor Q3 controls the output voltage VOUT. The duty cycle is internally
adjusted 5% to 85% depending on the internally sensed voltage of the output. Synchronized rectification occurs
when V(driver) is below 5 V.
To avoid a discharging of the buffer capacitor, a simultaneous switching on of Q3 and Q4 is not allowed. An
inherent delay is incorporated between Q3 switching off and Q4 switching on and vice versa.
In boost mode, transistor Q2 is not required and remains off. Transistor Q1 is switched on for the duration of the
boost-mode operation (serves as a supply line).
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Device Functional Modes (continued)
The switch timings of transistors Q1 and Q2 are not considered. In boost mode, the logical control of the
transistors does not change.
7.4.5 Extension of the Input Voltage Range on V(driver)
To ensure a stable 5-V output voltage with the output load in the specified range, the V(driver) supply must be
greater than or equal to 5 V for greater than 1 ms (typical). After a period of 1 ms (typical), the logic may be
supplied by the VOUT regulator and the V(driver) supply may be capable of operating down to 1.5 V.
The switch-mode regulator does not start at V(driver) less than 5 V.
7.4.6 Low-Power Mode
To reduce quiescent current and to provide efficient operation, the regulator enters a pulsed mode.
The device enters this mode by a logic-level low on this pin.
Automatic low-power mode is not available. The low-power-mode function is not available in boost mode. The
device leaves low-power mode during boost mode regardless of the logic level on the CLP pin.
7.4.7 Temperature and Short-Circuit Protection
To prevent thermal destruction, the device offers overtemperature protection to disable the IC. Also, short-circuit
protection is included for added protection on VOUT and 5Vg.
7.4.8 Switch Output Pin (5Vg) Current Limitation
A charge pump drives the internal FET, which switches the primary output voltage VOUT to the 5Vg pin.
Protection is implemented to prevent the output voltage from dropping below its specified value while enabling
the secondary output voltage. An explanation of the block diagram (see Figure 1) is given by the following
example:
• Device is enabled, output voltage VOUT is up and stable.
• 5Vg is enabled (pin 5Vg_ENABLE set to high) with load resistance connected to 5Vg pin.
• If output voltage VOUT drops below typical ( VOUT – 100 mV), the charge pump of the 5Vg FET is switched off
and the FET remains on for a while as the gate voltage drops slowly.
• If VOUT drops below the RESET threshold of 4.65 V (typical), the FET of the secondary output voltage 5Vg is
switched off (gate drawn to ground level).
• A deglitch time ensures that a device reset does not occur if VOUT drops to the reset level during the 5Vg
turnon phase.
• If VOUT rises above typical (VOUT – 100 mV), the charge pump of the 5Vg FET is switched on and drives the
gate of the 5Vg FET on.
7.4.9 Soft Start
On power up, the device offers a soft-start feature which ramps the output of the regulator at a slew of 10 V/ms.
When a reset occurs, the soft start is reenabled. Additionally, if the output capacitor is greater than 220 μF
(typical), the slew rate decreases to a value set by the internal current limit. In boost mode, the soft-start feature
is not active.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPIC74100-Q1 is a switch-mode regulator with integrated switches for voltage-mode control. With the help
of external LC components, the device regulates the output to 5V +-2% for a wide input voltage range. The
device can monitor the output voltage as well as the input voltage.
8.2 Typical Application
22 µH–100 µH
4.7 nF
4.7 nF
L1
L2
Cboot1
VOUT
5V
22 µF–470 µF
Cboot2
L
Vbattery
Vdriver
5Vg
R2
C
5V
AIN
1 µF–100 µF
R1
TPIC74101-Q1
5V
ENABLE
5 kW
Vlogic
470 nF
Optional
Connection
RESET
5 kW
5Vg_ENABLE
REST
2.2 nF–150 nF
CLP
AOUT
SCR1
SCR0
Rmod
12 kW
GND
PGND
S0183-01
A.
To minimize voltage ripple on the output due to transients, it is recommended to use a low-ESR capacitor on the VOUT
line.
B.
The L and C component values are system application dependent for EMI consideration.
Figure 20. Application Schematic
8.2.1 Design Requirements
Plot the converter efficiency with four different slew rate controls (SCRx) at an input voltage of 11 V and 17 V.
The slew rate of the switching transistor Q1 can be changed using the SCR0 and SCR1 pins.
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Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Buck Mode
• Select inductor ripple current ΔIL: for example ΔIL = 0.2 × IOUT
• Calculate inductor L
ǒV IN * V OUTǓ V OUT
L+
(H)
f SW DI L V IN
•
•
where fSW is the regulator switching frequency.
Inductor peak current
DI
I L,max + I OUT ) L (A)
2
Output voltage ripple
DV OUT + DI L
ǒESR ) 8
Ǔ
1
f SW
COUT
(5)
(6)
8.2.2.2 Boost Mode
• Select inductor ripple current ΔIL: for example ΔIL = 0.2 × IIN
• Calculate inductor L
ǒV OUT * V INǓ V IN
L+
(H)
f SW DI L V OUT
•
where fSW is the regulator switching frequency.
Inductor peak current
DI
I p + I L,max + I IN ) L (A)
2
Output voltage ripple
I OUT
DV OUT + I p
18
ESR )
f SW
ǒ1 *
(4)
(V (p−p))
Usually, the first term is dominant.
I pk(t on ) t off)
C OUT +
(F)
8 Vripple
•
(3)
V IN
V
Ǔ
OUT
COUT
(V(p−p))
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Typical Application (continued)
8.2.3 Application Curves
85
SCR: 11, V(driver) = 11 V
80
Efficiency − %
75
70
65
SCR: 10, V(driver) = 17 V
SCR: 10, V(driver) = 11 V
60
SCR: 01, V(driver) = 17 V
SCR: 01, V(driver) = 11 V
SCR: 00, V(driver) = 11 V
55
50
100
SCR: 00, V(driver) = 17 V
SCR: 11, V(driver) = 17 V
150
200
250
300
350
400
450
IO − Output Current − mA
500
550
600
G004
NOTE: The average converter efficiency with four different slew rate controls (SCRx) on the Q1 switching FET with input
voltage V(driver) = 11 V and 17 V, TA = 125°C.
Figure 21. Converter Efficiency
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9 Power Supply Recommendations
The input decoupling capacitors and bootstrap capacitor must be located as close as possible to the device.
Ensure that input power supply is clean. To minimize voltage ripple on the output due to transients, it is
recommended to use a low-ESR capacitor on the VOUT line. The L and C component values are system
application dependent for EMI consideration. TI recommends using a low EMI Inductor with a ferrite-type closed
core.
10 Layout
10.1 Layout Guidelines
10.1.1 Switch-Mode Power Supply
The following guidelines are recommended for PCB layout of the TPIC74100 device.
10.1.1.1 Inductor
Use a low-EMI inductor with a ferrite-type closed core. Other types of inductors may be used; however, they
must have low-EMI characteristics and be located away from the low-power traces and components in the circuit.
10.1.1.2 Filter Capacitors
Input ceramic filter capacitors should be located in the close proximity of the Vdriver pin. Surface-mount capacitors
are recommended to minimize lead length and reduce noise coupling.
10.1.1.3 Traces and Ground Plane
All power (high-current) traces should be thick and as short as possible. The inductor and output capacitors
should be as close to each other as possible. This reduces EMI radiated by the power traces due to high
switching currents.
In a two-sided PCB, it is recommended to have ground planes on both sides of the PCB to help reduce noise
and ground-loop errors. The ground connection for the input and output capacitors and IC ground should be
connected to this ground plane.
In a multilayer PCB, the ground plane is used to separate the power plane (where high switching currents and
components are placed) from the signal plane (where the feedback trace and components are) for improved
performance.
Also, arrange the components such that the switching-current loops curl in the same direction. Place the highcurrent components such that during conduction, the current path is in the same direction. This prevents
magnetic field reversal caused by the traces between the two half-cycles, helping to reduce radiated EMI.
10.1.2 Package and PCB Land Configuration for a Multilayer PCB
To maximize the efficiency of this package for application on a single-layer or multilayer PCB, certain guidelines
must be followed when laying out this device on the PCB.
The following information is to be used as a guideline only.
For further information see the PowerPAD Thermally Enhanced Package technical brief (SLMA002).
The following are guidelines for mounting the PowerPAD™ IC on a multilayer PCB with a ground plane.
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Layout Guidelines (continued)
Solder Pad (Land Pattern)
Package Thermal Pad
Thermal Vias
Package Outline
M0026-01
Figure 22. Package and PCB Land Configuration for a Multilayer PCB
10.1.3 Multilayer (Side View)
In a multilayer board application, the thermal vias are the primary method of heat transfer from the package
thermal pad to the internal ground plane.
The efficiency of this method depends on several factors (die area, number of thermal vias, thickness of copper,
etc.). See the PowerPAD Thermally Enhanced Package technical brief (SLMA002).
Layout recommendation is to use as much copper area for the power-management section of a single-layer
board as possible. In a single-layer board application, the thermal pad is attached to a heat spreader (copper
areas) by using a low-thermal-impedance attachment method (solder paste or thermal-conductive epoxy). In both
of these cases, it is advisable to use as much copper and as many traces as possible to dissipate the heat.
Power Pad
Package Solder Pad
Component Traces
1,5038-mm–1,5748-mm
Component Trace
(2-oz. Cu)
2 Plane
4 Plane
Thermal Via
1,5748 mm
Thermal Isolation
Power Plane Only
1,0142-mm–1,0502-mm
Ground Plane
(1-oz. Cu)
0,5246-mm–0,5606-mm
Power Plane
(1-oz. Cu)
0-mm–0,071-mm Board
Base and Bottom Pad
Package Solder Pad
(Bottom Trace)
M0027-01
Figure 23. Multilayer Board (Side View)
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Layout Guidelines (continued)
10.1.4 Single-Layer
Use as Much Copper Area
as Possible for Heat Spread
Package Thermal Pad
Package Outline
M0028-01
Figure 24. Land Configuration for Single-Layer PCB
When this attachment method is not implemented correctly, this product may operate inefficiently. Power dissipation capability
may be adversely affected when the device is incorrectly mounted onto the circuit board.
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10.2 Layout Example
Switching Components (L1, D2, C1, C2)
Minimize this loop area to reduce ringing
Supply Decoupling Capacitor
Place Nearby
Figure 25. Layout Example 1
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Layout Example (continued)
Multiple vias connect the input, output, and package pad to the ground plane
Large gound plane to reduce
noise and ground-loop errors
Figure 26. Layout Example 2
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11 Device and Documentation Support
11.1 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPIC74101QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
T74101D5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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