TPS1100D

TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 D D D D D D D Low rDS(on) . . . 0.18 Ω Typ at VGS = – 10 V 3 V Compatible Requires No External VCC TTL and CMOS Compatible Inputs VGS(th) = – 1.5 V Max Available in Ultrathin TSSOP Package (PW) ESD Protection Up to 2 kV Per MIL-STD-883C, Method 3015 D OR PW PACKAGE (TOP VIEW) SOURCE SOURCE SOURCE GATE 1 8 2 7 3 6 4 5 DRAIN DRAIN DRAIN DRAIN D PACKAGE PW PACKAGE description The TPS1100 is a single P-channel enhancement-mode MOSFET. The device has been optimized for 3-V or 5-V power distribution in battery-powered systems by means of Texas Instruments LinBiCMOS process. With a maximum VGS(th) of – 1.5 V and an IDSS of only 0.5 µA, the TPS1100 is the ideal high-side switch for low-voltage, portable battery-management systems where maximizing battery life is a primary concern. The low rDS(on) and excellent ac characteristics (rise time 10 ns typical) make the TPS1100 the logical choice for low-voltage switching applications such as power switches for pulse-width-modulated (PWM) controllers or motor/bridge drivers. schematic SOURCE ESDProtection Circuitry GATE The ultrathin thin shrink small-outline package or TSSOP (PW) version with its smaller footprint and reduction in height fits in places where other P-channel MOSFETs cannot. The size advantage is especially important where board real estate is at a premium and height restrictions do not allow for a small-outline integrated circuit (SOIC) package. DRAIN NOTE A: For all applications, all source pins should be connected and all drain pins should be connected. AVAILABLE OPTIONS PACKAGED DEVICES TA – 40°C to 85°C SMALL OUTLINE (D) TPS1100D PLASTIC DIP (P) TPS1100PWLE CHIP FORM (Y) TPS1100Y The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS1100DR). The PW package is available only left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TPS1100PWLE). The chip form is tested at 25°C. Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. LinBiCMOS is a trademark of Texas Instruments Incorporated. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 description (continued) Such applications include notebook computers, personal digital assistants (PDAs), cellular telephones, and PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other p-channel MOSFETs in SOIC packages. TPS1100Y chip information This chip, when properly assembled, displays characteristics similar to the TPS1100. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (4) SOURCE SOURCE SOURCE (5) (3) GATE (1) (8) (2) (7) (3) TPS1100Y (4) (6) (5) DRAIN DRAIN DRAIN DRAIN (6) 57 CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C (8) (1) TOLERANCES ARE ± 10% (7) (2) ALL DIMENSIONS ARE IN MILS 64 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† UNIT Drain-to-source voltage, VDS –15 Gate-to-source voltage, VGS 2 or –15 D package PW package TA = 25°C TA = 125°C ± 0.23 D package TA = 25°C TA = 125°C ± 0.33 PW package TA = 25°C TA = 125°C ± 0.53 D package TA = 25°C TA = 125°C ±1 PW package TA = 25°C TA = 125°C D package TA = 25°C TA = 125°C PW package TA = 25°C TA = 125°C VGS = – 3 V Continuous drain current (TJ = 150°C) 150°C), ID‡ 5V VGS = – 4 4.5 VGS = – 10 V Pulsed drain current, ID‡ TA = 25°C TA = 25°C Continuous source current (diode conduction), IS V ± 0.41 TA = 25°C TA = 125°C VGS = – 2 2.7 7V V ± 0.28 ± 0.4 ± 0.6 ± 0.27 A ± 0.47 ± 0.81 ± 0.37 ± 1.6 ± 0.72 ± 1.27 ± 0.58 ±7 A –1 A Storage temperature range, Tstg – 55 to 150 °C Operating junction temperature range, TJ – 40 to 150 °C Operating free-air temperature range, TA – 40 to 125 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Maximum values are calculated using a derating factor based on RθJA = 158°C/ W for the D package and RθJA = 248°C/ W for the PW package. These devices are mounted on a FR4 board with no special thermal considerations. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING D 791 mW 6.33 mW/°C PW 504 mW 4.03 mW/°C TA = 85°C POWER RATING TA = 125°C POWER RATING 506 mW 411 mW 158 mW 323 mW 262 mW 101 mW ‡ Maximum values are calculated using a derating factor based on RθJA = 158°C/ W for the D package and RθJA = 248°C/ W for the PW package. These devices are mounted on an FR4 board with no special thermal considerations when tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 electrical characteristics at TJ = 25°C (unless otherwise noted) static PARAMETER Gate-to-source VGS(th) threshold voltage VDS = VGS, ID = – 250 µA VSD Source-to-drain voltage (diode-forward voltage)† IS = – 1 A, VGS = 0 V IGSS Reverse gate current, drain short circuited to source VDS = 0 V, VGS = – 12 V IDSS Zero-gate-voltage g g drain current VDS = – 12 V V, VGS = 0 V VGS = – 10 V VGS = – 4.5 V ID = – 1.5 A ID = – 0.5 A VGS = – 3 V VGS = – 2.7 V ID = – 0 0.2 2A VDS = – 10 V, ID = – 2 A rDS( DS(on)) gfs Static drain-to-source on-state resistance† Forward transconductance† TPS1100 TEST CONDITIONS TPS1100Y MIN TYP MAX –1 – 1.25 – 1.50 MIN – 0.9 TYP MAX – 1.25 V – 0.9 V ± 100 TJ = 25°C TJ = 125°C UNIT nA – 0.5 µA – 10 180 180 291 400 291 476 700 476 606 850 606 2.5 mΩ 2.5 S † Pulse test: pulse duration ≤ 300 µs, duty cycle ≤ 2% dynamic PARAMETER TPS1100, TPS1100Y TEST CONDITIONS MIN TYP MAX UNIT Qg Total gate charge Qgs Gate-to-source charge Qgd Gate-to-drain charge 1.4 td(on) td(off) Turn-on delay time 4.5 ns 13 ns tr tf Rise time trr(SD) Source-to-drain reverse recovery time 4 5.45 VDS = – 10 V, Turn-off delay time VDD = – 10 V,, RG = 6 Ω, VGS = – 10 V, RL = 10 Ω,, See Figures 1 and 2 Fall time ID = – 1 A ID = – 1 A,, 0.87 10 2 IF = 5.3 A, di/dt = 100 A /µs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 nC 16 ns TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 PARAMETER MEASUREMENT INFORMATION VGS 90% RL VDS VGS RG 0V – + VDD 10% DUT VDS – 10 V td(on) td(off) tr Figure 1. Switching-Time Test Circuit tf Figure 2. Switching-Time Waveforms TYPICAL CHARACTERISTICS Table of Graphs FIGURE Drain current vs Drain-to-source voltage 3 Drain current vs Gate-to-source voltage 4 Static drain-to-source on-state resistance vs Drain current 5 Capacitance vs Drain-to-source voltage 6 Static drain-to-source on-state resistance (normalized) vs Junction temperature 7 Source-to-drain diode current vs Source-to-drain voltage 8 Static drain-to-source on-state resistance vs Gate-to-source voltage 9 Gate-to-source threshold voltage vs Junction temperature 10 Gate-to-source voltage vs Gate charge 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE –7 –7 VGS = – 8 V VGS = – 7 V I D – Drain Current – A VGS = – 6 V –6 VGS = – 4 V TJ = 25°C –5 VGS = – 5 V –4 VGS = – 3 V ÁÁ ÁÁ –3 –2 VGS = – 2 V –1 I D – Drain Current – A –6 VDS = –10 V TJ = 150°C –5 TJ = – 40°C –4 ÁÁ ÁÁ –3 –2 –1 TJ = 25°C 0 0 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 – 10 VDS – Drain-to-Source Voltage – V 0 –1 –2 –3 –4 –5 Figure 3 CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 350 0.7 VGS = 0 f = 1 MHz TJ = 25°C Ciss† TJ = 25°C 300 VGS = – 2.7 V 0.5 0.2 C – Capacitance – pF On-State Resistance – Ω r DS(on) – Static Drain-to-Source 0.6 0.3 –7 Figure 4 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 0.4 –6 VGS – Gate-to-Source Voltage – V VGS = – 3 V VGS = – 4.5 V VGS = –10 V 0.1 0 – 0.1 250 200 Coss 150 Crss‡ 100 50 –1 0 – 10 ID – Drain Current – A 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 –10 –11 –12 VDS – Drain-to-Source Voltage – V + Cgs ) Cgd, Cds(shorted) iss C gs C gd ‡ C rss + C gd, C oss + C ds ) C ) C gs † C gd Figure 5 6 Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ≈ C ds ) Cgd TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE (NORMALIZED) vs JUNCTION TEMPERATURE On-State Resistance (normalized) r DS(on) – Static Drain-to-Source 1.4 –10 VGS = – 10 V ID = – 1A Pulse Test I SD – Source-to-Drain Diode Current – A 1.5 SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE 1.3 1.2 1.1 1 0.9 0.8 0.7 TJ = 150°C –1 TJ = 25°C TJ = – 40°C – 0.1 0.6 – 50 0 50 100 0 150 – 0.2 – 0.4 – 0.6 – 0.8 – 1 –1.2 –1.4 –1.6 –1.8 TJ – Junction Temperature – °C VSD – Source-to-Drain Voltage – V Figure 8 Figure 7 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs GATE-TO-SOURCE VOLTAGE VGS(th) – Gate-to-Source Threshold Voltage – V r DS(on) – Static Drain-to-Source On-State Resistance – Ω 0.7 ID = – 1 A TJ = 25°C 0.6 0.5 0.4 0.3 0.2 0.1 0 –1 –3 –5 –7 –9 – 11 – 13 GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE – 15 VGS – Gate-to-Source Voltage – V – 1.5 ID = – 250 µA – 1.4 – 1.3 – 1.2 – 1.1 ÁÁ ÁÁ ÁÁ –1 – 0.9 – 50 Figure 9 0 50 100 150 TJ – Junction Temperature – °C Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS GATE-TO-SOURCE VOLTAGE vs GATE CHARGE VGS – Gate-to-Source Voltage – V – 10 VDS = – 10 V ID = – 1 A TJ = 25°C –8 –6 –4 –2 0 0 1 2 3 4 5 Qg – Gate Charge – nC Figure 11 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 THERMAL INFORMATION TRANSIENT JUNCTION-TO-AMBIENT THERMAL IMPEDANCE vs PULSE DURATION DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE – 10 100 Single Pulse See Note A 0.001 s ZθJA – Transient Junction-to-Ambient Thermal Impedance – °C/W Single Pulse See Note A I D – Drain Current – A 0.01 s –1 0.1 s 1s – 0.1 10 s DC TJ = 150°C TA = 25°C – 0.001 – 0.1 –1 – 10 10 1 0.1 0.001 – 100 0.01 0.1 1 10 tw – Pulse Duration – s VDS – Drain-to-Source Voltage – V Figure 12 Figure 13 NOTE A: Values are for the D package and are FR4-board mounted only. APPLICATION INFORMATION 3 V or 5 V 5V Microcontroller Driver Load Figure 14. Notebook Load Management POST OFFICE BOX 655303 Microcontroller Charge Pump –4 V GaAs FET Amplifier Figure 15. Cellular Phone Output Drive • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS1100D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 1100 TPS1100DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 1100 TPS1100PW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM PS1100 TPS1100PWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM PS1100 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of