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TPS1HA08-Q1
SLVSDM4D – NOVEMBER 2018 – REVISED DECEMBER 2019
TPS1HA08-Q1, 40-V, 8-mΩ Single-Channel Smart High-Side Switch
1 Features
3 Description
•
The device is a single-channel smart high-side switch
intended for use with 12-V automotive systems. The
device integrates robust protection and diagnostic
features to ensure output port protection even during
harmful events like short circuits. The device protects
against faults through a reliable current limit, which,
depending on device variant, is available at both 80 A
and 20 A and can be configured to react to an
overcurrent event by either instantly turning the
switch off or by regulating the output current at the
set point. The high current limit option allows for
usage in loads that require large transient currents,
while the low current limit option provides improved
protection for loads that do not require high peak
current.
1
•
•
•
•
•
•
Single-channel smart high-side switch with 8-mΩ
RON (TJ = 25°C)
Qualified for automotive applications:
– AEC Q-100 Qualified
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature range
– Withstands 40-V load dump
Functional safety capable
– Documentation available to aid functional
safety system design
Improve reliability through selectable current
limiting
– Current limit set-point at 20 A or 80 A
– Overcurrent response of current clamping or
instant shutdown
Robust integrated output protection:
– Integrated thermal protection
– Protection against short to ground and battery
– Automatic switch-on during reverse battery
– Automatic shut off if loss of battery and ground
occurs
– Integrated output clamp to demagnetize
inductive loads
– Configurable fault handling
Analog sense output can be configured to
accurately measure:
– Load current
– Supply voltage
– Device temperature
Provides FLT indication back to MCU
– Detection of open load and short-to-battery
The also provides a high accuracy analog current
sense that allows for improved diagnostics when
driving varied load profiles. By reporting load current,
device temperature, and supply voltage to a system
MCU, the device enables predictive maintenance and
load diagnostics that lengthen the system lifetime.
The is available in a small 16-pin HTSSOP package
which allows for reduced PCB footprint.
Device Information(1)
PART NUMBER
TPS1HA08-Q1
PACKAGE
HTSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
DIA_EN
SEL1
SEL2
µC
SNS
ST
2 Applications
•
•
•
•
•
•
•
Body control modules
Incandescent and LED lighting
Heating elements:
– Seat heaters
– Glow plug
– Tank heaters
Transmission control unit
Climate control
Infotainment display
ADAS modules
LATCH
TPS1HA08-Q1
EN
12-V Battery
VBB
VOUT
GND
Load
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS1HA08-Q1
SLVSDM4D – NOVEMBER 2018 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
1
1
1
2
3
4
7
Specifications......................................................... 6
6.1 Recommended Connections for Unused Pins .......... 5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
9
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Switching Characteristics .......................................... 9
SNS Timing Characteristics .................................... 10
Typical Characteristics ............................................ 12
Parameter Measurement Information ................ 18
Detailed Description ............................................ 19
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
20
21
36
10 Application and Implementation........................ 38
10.1 Application Information.......................................... 38
10.2 Typical Application ............................................... 41
11 Power Supply Recommendations ..................... 45
12 Layout................................................................... 46
12.1 Layout Guidelines ................................................. 46
12.2 Layout Example .................................................... 46
13 Device and Documentation Support ................. 47
13.1
13.2
13.3
13.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
47
47
47
47
14 Mechanical, Packaging, and Orderable
Information ........................................................... 47
4 Revision History
Changes from Revision C (May 2019) to Revision D
•
Page
Added functional safety capable link to the Features section ................................................................................................ 1
Changes from Revision B (January 2019) to Revision C
Page
•
Added links to reference App Notes in the Features and Description sections ..................................................................... 1
•
Removed the Product Preview note from Device Version B,D,E in the Device Comparison Table ...................................... 3
•
Updated the Absolute Maximum Ratings and Electrical Characteristics tables in the Specifications section ....................... 6
•
Updated Figure 7.................................................................................................................................................................. 13
•
Added paragragh to the Undervoltage Lockout (UVLO) section .......................................................................................... 22
•
Added app note link to Figure 41 title .................................................................................................................................. 24
Changes from Revision A (December 2018) to Revision B
•
Deleted note from Device Version C in the Device Comparison Table ................................................................................ 3
Changes from Original (September 2017) to Revision A
•
2
Page
Page
Changed from Advance Information to Production Data ....................................................................................................... 1
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TPS1HA08-Q1
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SLVSDM4D – NOVEMBER 2018 – REVISED DECEMBER 2019
5 Device Comparison Table
Device Version
Full Device Number
Current Limit (ICL)
Overcurrent Behavior
Watchdog Feature
A
TPS1HA08A-Q1
20 A
Disable Switch Immediately
Disabled
B
TPS1HA08B-Q1
80 A
Disable Switch Immediately
Disabled
C
TPS1HA08C-Q1
20 A
Clamp Current at ICL until Thermal
Shutdown
Disabled
D
TPS1HA08D-Q1
80 A
Clamp Current at ICL until Thermal
Shutdown
Disabled
E
TPS1HA08E-Q1
20 A
Disable Switch Immediately
Enabled
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SLVSDM4D – NOVEMBER 2018 – REVISED DECEMBER 2019
www.ti.com
6 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
GND
1
16
DIA_EN
SNS
2
15
SEL2
LATCH
3
14
SEL1
EN
4
13
NC
VBB
ST
5
12
NC
VOUT
6
11
VOUT
VOUT
7
10
VOUT
VOUT
8
9
VOUT
Pin Functions
PIN
4
I/O
DESCRIPTION
NO.
NAME
1
GND
—
Device ground
2
SNS
O
Sense output
3
LATCH
I
Sets fault handling behavior (latched or auto-retry)
4
EN
I
Switch control input, active high
5
ST
O
Switch diagnostic feedback, active low
6, 7, 8, 9, 10, 11
VOUT
O
Switch output
12
NC
--
No Connect
13
NC
--
No Connect
14
SEL1
I
Diagnostics Select 1
15
SEL2
I
Diagnostics Select 2
16
DIA_EN
I
Diagnostic enable, active high
Exposed pad
VBB
I
Power supply input
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SLVSDM4D – NOVEMBER 2018 – REVISED DECEMBER 2019
6.1 Recommended Connections for Unused Pins
The device is designed to provide an enhanced set of diagnostic and protection features. However, if the system
design only allows for a limited number of I/O connections, some pins may be considered as optional.
Table 1. Connections for Optional Pins
PIN NAME
CONNECTION IF NOT USED
SNS
Ground through 1-kΩ resistor
LATCH
Float or ground through
RPROT resistor
IMPACT IF NOT USED
Analog sense is not available.
With LATCH unused, the device will auto-retry after a fault. If latched
behavior is desired it is possible to use one microcontroller output to
control the latch function of several high-side channels.
All faults are indicated by the analog SNS pin. The ST pin provides the
additional benefits:
•
Provide fault indication when DIA_EN = 0
•
Provide fault indication regardless of SELx pin conditions
•
Provide fault indication to a simple digital I/O (rather than ADC or
comparator used with the SNS signal)
ST
Float
SEL1
Float or ground through
RPROT resistor
SEL1 selects between the VBB and TJ sensing features. With SEL1
unused, only load diagnostics are available.
SEL2
Ground through RPROT
resistor
With SEL2 = 0 V, VBB measurement diagnostics are not available.
DIA_EN
Float or ground through
RPROT resistor
With DIA_EN unused, analog sense, open-load and short-to-battery
diagnostics are not available.
RPROT is used to protect the pins from excess current flow during reverse battery conditions, for more information
please see the section on Reverse Battery protection.
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SLVSDM4D – NOVEMBER 2018 – REVISED DECEMBER 2019
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VBB
Maximum continuous supply voltage
VLD
Load dump voltage
VRev
Reverse battery voltage, VREV ≤ 3 minutes
VEN
Enable pin voltage
–1
7
V
VLATCH
LATCH pin voltage
–1
7
V
VST
Status pin voltage
–1
7 (2)
V
VDIA_EN
Diagnostic Enable pin voltage
–1
7
V
VSNS
Sense pin voltage
–1
7
V
VSEL1,
VSEL2
Select pin voltage
–1
7
V
IGND
Reverse ground current
ISO16750-2:2010(E)
Energy dissipation during turn-off
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
V
40
V
–18
V
VBB < 0 V
ETOFF
36
–50
mA
Single pulse, LOUT = 5 mH, TA = 125°C
95
mJ
Repetitive pulse, 10 Hz, LOUT = 5 mH, TA = 125°C
56
mJ
150
°C
150
°C
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These pins are adjacent to pins that will handle high-voltages. In the event of a pin-to-pin short, there will not be device damage.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
Charged-device model (CDM), per AEC Q100-011
(1)
All pins except exposed pad and
pins 6 to 11
±2000
Exposed pad and pins 6 to 11
±4000
All pins
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
8
18
V
3
28
V
Enable voltage
–1
5.5
V
VLATCH
LATCH voltage
–1
5.5
V
VDIA_EN
Diagnostic enable voltage
–1
5.5
V
VSEL1,
VSEL2
Select voltage
–1
5.5
V
VST
Status voltage
0
5.5
V
VSNS
Sense voltage
–1
VSNSclamp
V
IMAX
Continuous load current
0
10
A
VBB
Nominal supply voltage
VBB
Extended operating range
VEN
(1)
6
(1)
TA = 70°C
UNIT
Device will function within extended operating range, however some parametric values might not apply
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SLVSDM4D – NOVEMBER 2018 – REVISED DECEMBER 2019
7.4 Thermal Information
TPS1HA08-Q1
THERMAL METRIC (1) (2)
PWP (HTSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
32.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
30.7
°C/W
RθJB
Junction-to-board thermal resistance
9.3
°C/W
ψJT
Junction-to-top characterization parameter
2.6
°C/W
ψJB
Junction-to-board characterization parameter
9.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The thermal parameters are based on a 4-layer PCB according to the JESD51-5 and JESD51-7 standards.
7.5 Electrical Characteristics
VBB = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE AND CURRENT
VClamp
VDS clamp voltage
58
V
VUVLOF
VBB undervoltage lockout falling
2.5
3
V
VUVLOR
VBB undervoltage lockout rising
2.5
3
V
VBB = 13.5 V, TJ = 25°C
VEN = VDIA_EN = 0 V, VOUT = 0 V
0.5
µA
VBB = 13.5 V, TJ = 85°C
VEN = VDIA_EN = 0 V, VOUT = 0 V
0.5
µA
VBB = 13.5 V, TJ = 125°C,
VEN = VDIA_EN = 0 V, VOUT = 0 V
3
µA
0.5
µA
3
µA
ISB
IOUT(standby)
Standby current (includes
MOSFET leakage)
Output leakage current
40
VBB = 13.5 V, TJ = 25°C
VEN = VDIA_EN = 0 V, VOUT = 0 V
0.01
VBB = 13.5 V, TJ = 125°C
VEN = VDIA_EN = 0 V, VOUT = 0 V
IDIA
Current consumption in
diagnostic mode
VBB = 13.5 V, ISNS = 0 mA
VEN = 0 V, VDIA_EN = 5 V, VOUT = 0V
3
6
mA
IQ
Quiescent current
VBB = 13.5 V
VEN = VDIA_EN = 5 V, IOUT = 0 A, VSELX = 0 V
3
6
mA
tSTBY
Standby mode delay time
VEN = VDIA_EN = 0 V to Standby
20
ms
RON CHARACTERISTICS
TJ = 25°C, 6 V ≤ VBB ≤ 28 V
On-resistance
T = 150°C, 6 V ≤ VBB ≤ 28 V
Includes MOSFET and package J
TJ = 25°C, 3 V ≤ VBB ≤ 6 V
9
RON
RON(REV)
On-resistance during reverse
polarity
TJ = 25°C, -18 V ≤ VBB ≤ -8 V
9
TJ = 105°C, -18 V ≤ VBB ≤ -8 V
mΩ
20
mΩ
15
mΩ
mΩ
20
mΩ
CURRENT SENSE CHARACTERISTICS
KSNS
Current sense ratio
IOUT / ISNS
4600
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Electrical Characteristics (continued)
VBB = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
–5
–5
IOUT = 3 A
5
–5
5
–5
5
–12
–42
%
mA
12
0.022
IOUT = 100 mA
%
mA
0.065
IOUT = 300 mA
%
mA
0.217
IOUT = 1 A
%
mA
0.65
VEN = VDIA_EN = 5 V, VSEL1 =
VSEL2 = 0 V
UNIT
mA
5
1.74
IOUT = 8 A
Current sense current and
current sense accuracy
MAX
4.35
IOUT = 20 A
ISNSI
TYP
%
mA
42
%
TJ SENSE CHARACTERISTICS
ISNST
Temperature sense current
dISNST/dT
VDIA_EN = 5 V, VSEL1 = 5 V, VSEL2
=0V
TJ = –40°C
0.12
mA
TJ = 25°C
0.85
mA
TJ = 85°C
1.52
mA
TJ = 150°C
2.25
Coefficient
mA
0.0112
mA/°C
VBB SENSE CHARACTERISTICS
ISNSV
Voltage sense current
dISNSV/dV
VDIA_EN = 5 V, VSEL1 = 5 V, VSEL2
=5V
VBB = 3 V
0.26
mA
VBB = 8 V
0.69
mA
VBB = 13.5 V
1.17
mA
VBB = 18 V
1.56
mA
VBB = 28 V
2.43
Coefficient
mA
0.0867
mA/V
SNS CHARACTERISTICS
ISNSFH
ISNS fault high level
VDIA_EN = 5 V, VSEL1 = 0 V, VSEL2 = 0
6
ISNSleak
ISNS leakage
VDIA_EN = 0 V
0
VSNSclamp
VSNS clamp
6.9
7.6
mA
1
µA
5.9
V
CURRENT LIMIT CHARACTERISTICS
TJ = –40°C
Device Version B/D
ICL
Current Limit
75.5
88.8
102.1
TJ = 25°C
68
80
92
TJ = 150°C
51
60
69
27.8
TJ = –40°C
Device Version A/C/E
A
16
22.2
TJ = 25°C
14.4
20
25
TJ = 150°C
10.8
15
18.8
2
2.5
4
V
300
500
700
µs
A
ST PIN CHARACTERISTICS
VOL
Open-load detection voltage
VEN = 0 V, VDIA_EN = 5 V
tOL1
OL and STB indication time switch disabled
From falling edge of EN
VEN= 5 V to 0 V, VDIA_EN = 5 V, VSELx = 00
IOUT = 0 mA, VOUT = 4 V
tOL2
OL and STB indication time switch disabled
From rising edge of DIA_EN
VEN = 0 V, VDIA_EN = 0 V to 5 V, VSELx = 00
IOUT = 0 mA, VOUT = 4 V
50
µs
tOL3
OL and STB indication time switch disabled
From rising edge of VOUT
VEN = 0 V, VDIA_EN = 5 V, VSELx = 00
IOUT = 0 mA, VOUT = 0 V to 4 V
50
µs
TABS
Thermal shutdown
THYS
Thermal shutdown hysteresis
160
tRETRY
Retry time
Minimum time from fault shutdown to switch re-enable (for
thermal shutdown, current limit, and energy limit)
tWD
Watchdog timer
Device version E
8
°C
20
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°C
1
2
3
ms
350
400
450
ms
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SLVSDM4D – NOVEMBER 2018 – REVISED DECEMBER 2019
Electrical Characteristics (continued)
VBB = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN PIN CHARACTERISTICS (1)
VIL, EN
Input voltage low level
VIH,
Input voltage high level
No GND network Diode
Input voltage hysteresis
No GND network Diode
250
mV
IIL, EN
Input current low level
VEN = 0.8 V
0.8
µA
IIH,
Input current high level
VEN = 2.0 V
2
µA
1
MΩ
EN
VIHYS,
EN
EN
REN
0.8
V
Internal pulldown resistor
DIA_EN PIN CHARACTERISTICS
(1)
VIL,
DIA_EN
Input voltage low level
No GND network Diode
VIH,
DIA_EN
Input voltage high level
No GND network Diode
VIHYS,
DIA_EN
V
2
0.8
V
2
V
Input voltage hysteresis
250
mV
µA
IIL, DIA_EN
Input current low level
VDIA_EN = 0.8 V
0.8
IIH,
Input current high level
VDIA_EN = 2.0 V
2
µA
1
MΩ
DIA_EN
RDIA_EN
Internal pulldown resistor
SEL1 AND SEL2 PIN CHARACTERISTICS
VIL, SELx
Input voltage low level
VIH,
Input voltage high level
SELx
VIHYS,
SELx
(1)
No GND network Diode
0.8
V
2
V
Input voltage hysteresis
250
mV
µA
IIL, SELx
Input current low level
VSELx = 0.8 V
0.8
IIH,
Input current high level
VSELx = 2.0 V
2
µA
1
MΩ
SELx
RSELx
Internal pulldown resistor
LATCH PIN CHARACTERISTICS
(1)
VIL, LATCH
Input voltage low level
No GND network Diode
VIH, LATCH
Input voltage high level
No GND network Diode
VIHYS, LATCH
Input voltage hysteresis
IIL, LATCH
Input current low level
IIH, LATCH
Input current high level
RLATCH
Internal pulldown resistor
ST PIN CHARACTERISTICS
VOL,
ST
ISTleak
(1)
0.8
V
2
V
250
mV
VLATCH = 0.8 V
0.8
µA
VLATCH = 2.0 V
2
µA
1
MΩ
(1)
Output voltage low level
IST = 1 mA
Leakage current
VST = 5 V
0.4
V
2
µA
VBB = 3 to 28 V
7.6 Switching Characteristics
VBB = 13.5 V, TJ = –40°C to 150°C (unless otherwise noted)
MIN
TYP
MAX
UNIT
tDR
Turn-on delay time
PARAMETER
VBB = 13.5 V, RL = 2.6 Ω
TEST CONDITIONS
20
70
100
µs
tDF
Turn-off delay time
VBB = 13.5 V, RL = 2.6 Ω
20
50
100
µs
SRR
VOUT rising slew rate
VBB = 13.5 V, 20% to 80% of VOUT,
RL = 2.6 Ω
0.1
0.35
0.7
V/µs
SRF
VOUT falling slew rate
VBB = 13.5 V, 80% to 20% of VOUT,
RL = 2.6 Ω
0.1
0.5
0.7
V/µs
tON
Turn-on time
VBB = 13.5 V, RL = 2.6 Ω
39
80
145
µs
tOFF
Turn-off time
VBB = 13.5 V, RL = 2.6 Ω
39
75
145
µs
tON - tOFF
Turn-on and off matching
200-µs enable pulse
–50
0
50
EON
Switching energy losses during turn-on
VBB = 13.5 V, RL = 2.6 Ω
0.4
mJ
EOFF
Switching energy losses during turn-off
VBB = 13.5 V, RL = 2.6 Ω
0.4
mJ
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7.7 SNS Timing Characteristics
VBB = 8 to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNS TIMING - CURRENT SENSE
tSNSION1
Settling time from rising edge of DIA_EN
VEN = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, RL = 2.6 Ω
tSNSION2
Settling time from rising edge of EN
tSNSION3
40
µs
VEN = VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, RL = 2.6 Ω
180
µs
Settling time from rising edge of EN
VEN = 0 V to 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, RL = 2.6 Ω
180
µs
tSNSIOFF1
Settling time from falling edge of DIA_EN
VEN = 5 V, VDIA_EN = 5 V to 0 V
RSNS = 1 kΩ, RL = 2.6 Ω
20
µs
tSETTLEH
Settling time from rising edge of load step
VEN = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 1 A to 5 A
20
µs
tSETTLEL
Settling time from falling edge of load step
VEN = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 5 A to 1 A
20
µs
SNS TIMING - TEMPERATURE SENSE
tSNSTON1
Settling time from rising edge of DIA_EN
VEN = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ
40
µs
tSNSTON2
Settling time from rising edge of DIA_EN
VEN = 0 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ
70
µs
tSNSTOFF
Settling time from falling edge of DIA_EN
VEN = X, VDIA_EN = 5 V to 0 V
RSNS = 1 kΩ
20
µs
SNS TIMING - VOLTAGE SENSE
tSNSVON1
Settling time from rising edge of DIA_EN
VEN = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ
40
µs
tSNSVON2
Settling time from rising edge of DIA_EN
VEN = 0 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ
70
µs
tSNSVOFF
Settling time from falling edge of DIA_EN
VEN = X, VDIA_EN = 5 V to 0 V
RSNS = 1 kΩ
20
µs
Settling time from temperature sense to current
sense
VEN= X, VDIA_EN = 5 V
VSEL1 = 5 V to 0 V, VSEL2 = 0 V
RSNS = 1 kΩ, RL = 2.6 Ω
60
µs
Settling time from temperature sense to voltage
sense
VEN = X, VDIA_EN = 5 V
VSEL1 = 5 V, VSEL2 = 0 V to 5 V
RSNS = 1 kΩ
60
µs
Settling time from voltage sense to temperature
sense
VEN = X, VDIA_EN = 5 V
VSEL1 = 5 V, VSEL2 = 5 V to 0 V
RSNS = 1 kΩ
60
µs
Settling time from voltage sense to current sense
VEN = X, VDIA_EN = 5 V
VSEL1 = VSEL2 = 5 V to 0 V,
RSNS = 1 kΩ, RL = 2.6 Ω
60
µs
Settling time from current sense to temperature
sense
VEN = X, VDIA_EN = 5 V
VSEL1 = 0 V to 5 V, VSEL2 = 0 V
RSNS = 1 kΩ, RL = 2.6 Ω
60
µs
Settling time from current sense to voltage sense
VEN = X, VDIA_EN = 5 V
VSEL1 = VSEL2 = 0 V to 5 V
RSNS = 1 kΩ, RL = 2.6 Ω
60
µs
SNS TIMING - MULTIPLEXER
tMUX
10
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VEN
VDIA_EN
IOUT
ISNS
tSNSION1
tSNSION2
tSETTLEH
tSETTLEL
tSNSTON1
tSNSTON2
tSNSION3
tSNSIOFF1
VEN
VDIA_EN
IOUT
ISNS
VEN
VDIA_EN
TJ
ISNS
tSNSTOFF
NOTES: Rise and fall times of control signals are 100 ns. Control signals include: EN, DIA_EN, SEL1, SEL2.
SEL1 and SEL2 must be set to the appropriate values.
The temperature sense timing diagram can also be used to depict the voltage sense timings.
Figure 1. SNS Timing Characteristics Definitions
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VEN(1)
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50%
50%
90%
90%
tDR
tDF
VOUT
10%
10%
tON
tOFF
Rise and fall time of VEN is 100 ns.
Figure 2. Switching Characteristics Definitions
7.8 Typical Characteristics
1.25
2.65
1
2.6
0.75
ISB (µA)
UVLO Falling (V)
2.7
2.55
2.5
VBB
8V
13.5 V
18 V
0.5
0.25
2.45
-40
-10
20
VBB = 13.5 V to 0 V
VEN = 5 V
50
80
Temperature (°C)
110
0
-40
140
ROUT = 1 kΩ
VDIAG__EN = 0 V
0
VOUT = 0 V
Figure 3. Falling Undervoltage Lockout (VUVLOF) vs
Temperature
20
40
60
Temperature (°C)
80
100
120
SLVS
VEN = 0 V
VDIAG_EN = 0 V
Figure 4. Standby Current (ISB) vs Temperature
5
0.8
8V
13.5 V
18 V
VBB
8V
13.5 V
18 V
0.6
4
IQ (mA)
IOUT(standby) (PA)
-20
SLVS
0.4
3
0.2
0
-40
-20
VOUT = 0 V
0
20
40
60
Temperature (qC)
VEN = 0 V
80
100
120
-20
0
SLVS
VDIAG_EN = 0 V
Figure 5. Output Leakage Current (IOUT(standby)) vs
Temperature
12
2
-40
IOUT = 0 A
RSNS = 1 kΩ
20
40
60
Temperature (qC)
VEN = 5 V
VSEL1 = VSEL2 = 0 V
80
100
120
SLVS
VDIAG_EN = 5 V
Figure 6. Quiescent Current (IQ) vs Temperature
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Typical Characteristics (continued)
20
18
VBB
8V
13.5 V
18 V
16
16
RON (m:)
RON (m:)
14
12
12
-40qC
25qC
60qC
85qC
105qC
125qC
150qC
8
10
4
8
6
-40
0
-15
10
IOUT = 200 mA
RSNS = 1 kΩ
35
60
85
Temperature (qC)
110
135 150
0
4
8
SLVS
VEN = 5 V
VDIAG_EN = 0 V
IOUT = 200 mA
RSNS = 1 kΩ
Figure 7. On Resistance (RON) vs Temperature
12
16
VBB (V)
20
VEN = 5 V
VBB = 13.5 V
24
28
SLVS
VDIAG_EN = 0 V
Figure 8. On Resistance (RON) vs VBB
55
75
54.5
54
TOFF Delay (Ps)
TON Delay (Ps)
73
71
69
53.5
53
52.5
52
67
51.5
65
-40
-15
10
ROUT = 2.6 Ω
RSNS = 1 kΩ
35
60
85
Temperature (qC)
VEN = 0 V to 5 V
VBB = 13.5 V
110
51
-40
135 150
-15
10
SLVS
VDIAG_EN = 0 V
ROUT = 2.6 Ω
RSNS = 1 kΩ
Figure 9. Turn-on Delay Time (tDR) vs Temperature
35
60
85
Temperature (qC)
VEN = 5 V to 0 V
VBB = 13.5 V
110
135 150
SLVS
VDIAG_EN = 0 V
Figure 10. Turn-off Delay Time (tDF) vs Temperature
0.5
0.37
VOUT Slew Rate Falling (V/Ps)
VOUT Slew Rate Rising (V/Ps)
0.495
0.36
0.35
0.34
0.33
0.49
0.485
0.48
0.475
0.47
0.465
0.46
0.455
0.32
-40
-15
ROUT = 2.6 Ω
RSNS = 1 kΩ
10
35
60
85
Temperature (qC)
VEN = 0 V to 5 V
VBB = 13.5 V
110
135 150
0.45
-40
-15
SLVS
VDIAG_EN = 0 V
Figure 11. VOUT Slew Rate Rising (SRR) vs Temperature
ROUT = 2.6 Ω
RSNS = 1 kΩ
10
35
60
85
Temperature (qC)
VEN = 5 V to 0 V
VBB = 13.5 V
110
135 150
SLVS
VDIAG_EN = 0 V
Figure 12. VOUT Slew Rate Falling (SRF) vs Temperature
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Typical Characteristics (continued)
76.5
83
82
75
80
Turn-off Time (Ps)
Turn-on Time (Ps)
81
79
78
77
76
75
73.5
72
74
73
72
-40
-15
10
ROUT = 2.6 Ω
RSNS = 1 kΩ
35
60
85
Temperature (qC)
110
70.5
-40
135
VEN = 0 V to 5 V
VBB = 13.5 V
VDIAG_EN = 0 V
10
ROUT = 2.6 Ω
RSNS = 1 kΩ
Figure 13. Turn-on Time (tON) vs Temperature
35
60
85
Temperature (qC)
VEN = 5 V to 0 V
VBB = 13.5 V
110
135 150
SLVS
VDIAG_EN = 0 V
Figure 14. Turn-off Time (tOFF) vs Temperature
0.2
10
-40qC
25qC
60qC
85qC
105qC
125qC
150qC
0.18
0.16
8
0.14
6
ISNSI (mA)
Turn-on and off matching (Ps)
-15
SLVS
4
0.12
0.1
0.08
0.06
0.04
2
0.02
0
-40
0
-15
10
ROUT = 2.6 Ω
RSNS = 1 kΩ
35
60
85
Temperature (qC)
VEN = 0 V to 5 V
and 5 V to 0 V
VBB = 13.5 V
110
0
135 150
VDIAG_EN = 0 V
200
VSEL1 = VSEL2 = 0 V
RSNS = 1 kΩ
300 400 500 600
ILOAD (mA), VBB=13.5
VEN = 5 V
VBB = 13.5 V
700
800
900
SLVS
VDIAG_EN = 5 V
Figure 16. Current Sense Output Current (ISNSI ) vs Load
Current (IOUT) across Temperature
Figure 15. Turn-on and Turn-off Matching (tON - tOFF) vs
Temperature
3
0.2
VBB
8V
13.5 V
18 V
0.18
0.16
2.5
0.14
8V
13.5 V
18 V
2
ISNST (mA)
ISNSI (mA)
100
SLVS
0.12
0.1
0.08
1.5
1
0.06
0.04
0.5
0.02
0
0
100
200
VSEL1 = VSEL2 = 0 V
RSNS = 1 kΩ
300
400 500
ILOAD (mA)
VEN = 5 V
TA = 25°C
600
700
800
900
-15
10
SLVS
VDIAG_EN = 5 V
Figure 17. Current Sense Output Current (ISNSI) vs Load
Current (IOUT) across VBB
14
0
-40
VSEL1 = 5 V
RSNS = 1 kΩ
35
60
85
Temperature (qC)
VSEL2 = 0 V
VEN = 0 V
110
135 150
SLVS
VDIAG_EN = 5 V
Figure 18. Temperature Sense Output Current (ISNST) vs
Temperature
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Typical Characteristics (continued)
2.5
6.95
-40qC
25qC
60qC
85qC
105qC
125qC
150qC
1.5
6.85
ISNSFH (mA)
ISNSV (mA)
2
8V
13.5 V
18 V
6.9
1
6.8
6.75
6.7
0.5
6.65
0
0
4
8
VSEL1 = VSEL2 = 5 V
RSNS = 1 kΩ
12
16
VBB (V)
20
VEN = 0 V
IOUT = 0 A
24
6.6
-40
28
VDIAG_EN = 5 V
35
60
85
Temperature (qC)
110
135 150
SLVS
VEN = 0 V
VOUT Floating
VDIAG_EN = 5 V
Figure 20. Fault High Output Current (ISNSFH) vs
Temperature
6.4
26
8V
13.5 V
18 V
24
ILIM (A) (Version A/C)
6.3
6.2
VSNS Clamp (V)
10
VSEL1 = VSEL2 = 0 V
RSNS = 500 Ω
Figure 19. Voltage Sense Output Current (ISNSV) vs VBB
6.1
6
5.9
5.8
22
20
18
16
14
12
5.7
-40
-15
10
VSEL1 = VSEL2 = 0 V
RSNS = 10 kΩ
35
60
85
Temperature (qC)
VEN = 5 V
IOUT = 4 A
110
10
-40
135 150
-15
10
SLVS
VDIAG_EN = 5 V
VBB = 13.5 V
Device Version C
Figure 21. Sense Pin Clamp Voltage (VSNSCLAMP) vs
Temperature
35
60
85
Temperature (qC)
VOUT = 0 V
VEN = 5 V
110
135 150
SLVS
VDIAG_EN = 0 V
VLATCH = 5 V
Figure 22. Current Limit (ICL) vs Temperature
1.54
2.85
VBB
8V
13.5 V
18 V
2.75
VBB
8V
13.5 V
18 V
1.535
1.53
1.525
2.65
VIL (V)
VOL Threshold (V)
-15
SLVS
1.52
1.515
1.51
2.55
1.505
1.5
2.45
1.495
2.35
-40
-15
VEN = 0 V
VDIAG_EN= 5 V
10
35
60
85
Temperature (qC)
VOUT = 0 V to 5 V
VSEL1 = VSEL2 = 0 V
110
135 150
1.49
-40
-15
10
SLVS
IOUT = 0 A
VEN = 3.3 V to 0 V
ROUT = 1 kΩ
Figure 23. Open Load Detection Voltage (VOL) vs
Temperature
35
60
85
Temperature (qC)
VOUT = 0 V
110
135 150
SLVS
VDIAG_EN = 0 V
Figure 24. VIL vs Temperature
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Typical Characteristics (continued)
325
1.86
1.85
VBB
8V
13.5 V
18 V
VBB
8V
13.5 V
18 V
320
315
VHYST (mV)
VIH (V)
1.84
1.83
1.82
305
300
1.81
1.8
-40
310
295
-15
10
VEN = 0 V to 3.3 V
ROUT = 1 kΩ
35
60
85
Temperature (qC)
110
290
-40
135 150
-15
VOUT = 0 V
VDIAG_EN = 0 V
VEN = 0 V to 3.3 V
and 3.3 V to 0 V
ROUT = 1 kΩ
Figure 25. VIH vs Temperature
3.2
IIH (PA)
IIL (PA)
135 150
SLVS
VOUT = 0 V
VDIAG_EN = 0 V
8V
13.5 V
18 V
2.8
1
2.4
0.8
2
0.6
1.6
-15
VEN = 0.8 V
ROUT = 1 kΩ
10
35
60
85
Temperature (qC)
110
135 150
1.2
-40
-15
10
SLVS
VOUT = 0 V
VDIAG_EN = 0 V
VEN = 2 V
ROUT = 1 kΩ
Figure 27. IIL vs Temperature
ROUT = 2.6 Ω
RSNS = 1 kΩ
VDIA_EN = 5 V
VSEL1 = VSEL2 = 0 V
Figure 29. Turn-on Time (tON)
16
110
3.6
8V
13.5 V
18 V
1.2
0.4
-40
35
60
85
Temperature (qC)
Figure 26. VIHYS vs Temperature
1.6
1.4
10
SLVS
35
60
85
Temperature (qC)
110
135 150
SLVS
VOUT = 0 V
VDIAG_EN = 0 V
Figure 28. IIH vs Temperature
ROUT = 2.6 Ω
RSNS = 1 kΩ
VDIA_EN = 5 V
VSEL1 = VSEL2 = 0 V
Figure 30. Turn-off Time (tOFF) and Sense Settle Time
(tSNSION2)
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Typical Characteristics (continued)
VDIA_EN= 0 V to 5 V
VSEL1 = VSEL2 = 0 V
IOUT = 1 A to 5 A
Figure 31. ISNS Settling Time (tSNSION1) on DIA_EN Transition
RSNS = 1 kΩ
VDIA_EN = 5 V
VSEL1 = VSEL2 = 0 V
Figure 32. ISNS Settling Time (tSETTLEH) on Rising Load Step
100
11
IVBB (A) 10
ST (V)
SNS (V) 9
EN (V)
8
90
80
Current (A)
70
60
7
50
6
40
5
30
4
20
3
10
2
0
1
-10
0
-20
0
VOUT = VBB
VEN = 0 V
RSNS = 1 kΩ
VDIAG_EN = 5 V
VSEL1 = VSEL2 = 0 V
VBB = 13.5 V
VEN = 0 V to 5 V
Figure 33. Open Load Detection Time (tOL2) on Rising
DIAG_EN
Current (A)
20
15
12
10
8
5
4
0.0004
BPer
B Device Version
TA = 25°C
VOUT = 0 V
15
10
10
5
5
0
0
-5
-5
-10
-10
-15
-15
-20
-20
IVBB
VBB -25
VOUT -30
EN
-35
0.0056
-25
0
0
-5
0
0.00015
VBB = 13.5 V
VEN = 0 V to 5 V
0.0003
0.00045
Time (s)
0.0006
C Device Version
TA = 25°C
-1
0.0005
15
Current (A)
25
0.0002
0.0003
Time (s)
Figure 34. Short Circuit Behavior with B Device Version
24
IVBB (A)
ST (V)
20
SNS (V)
EN (V)
16
Voltage (V)
30
0.0001
-4
0.00075
-30
-35
0.0008
0.0016
0.0024
C_Pe
VOUT = 0 V
Voltage (V)
RSNS = 1 kΩ
VBB = 13.5 V
VEN = 0 V to 5 V, 5
V to 0 V
0.0032 0.004
Time (s)
TA = 125°C
0.0048
Voltage (V)
ROUT = 2.6 Ω
Indu
LOUT = 5 mH
Figure 35. Short Circuit Behavior with C Device Version
Figure 36. Inductive Load Demagnetization
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8 Parameter Measurement Information
IBB
ISNS
ILATCH
DIA_EN
SNS
SEL2
LATCH
SEL1
IDIA_EN
ISEL2
ISEL1
IOUT
ST
VOUT
GND
IGND
VST
VEN
VSEL1
IST
VLATCH
VSNS
VBB
VOUT
VDIA_EN
EN
VSEL2
IEN
VBB
Figure 37. Parameter Definitions
18
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9 Detailed Description
9.1 Overview
The device is a single-channel smart high-side power switch intended for use with 12 V automotive batteries.
Many protection and diagnostic features are integrated in the device.
Diagnostics features include the analog SNS output and the open-drain fault indication (ST). The analog SNS
output is capable of providing a signal that is proportional to device temperature, supply voltage, or load current.
The high-accuracy load current sense allows for diagnostics of complex loads.
This device includes protection through thermal shutdown, current limit, transient withstand, and reverse battery
operation. For more details on the protection features, refer to the Feature Description and Application
Information sections of the document.
9.1.1 Device Nomenclature
The is one device in the TI family of Smart High Side Switches. Figure 38 shows the family part number
nomenclature and explains how to determine device characteristics from the part number for TI Smart High Side
Switches.
TPS
1
H
A
08
X
Q
PWPR
Q1
Prefix
Auto Qual
No. of Channels
Packaging
H
12-V HSS
T
24-V HSS
AEC Temp Grade
Generation
Version
RON (PŸ)
Figure 38. Naming Convention
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9.2 Functional Block Diagram
VBB
VBB to GND
Clamp
Internal Power
Supply
VBB to VOUT
Clamp
GND
VOUT
Gate Driver
Power FET
EN
Current Limit
LATCH
Energy Limit
DIA_EN
Thermal
Shutdown
SEL1
SEL2
VBB
Open-load /
Short-to-Bat
Detection
Voltage Sense
Fault Indication
SNS
SNS Mux
ST
Current Sense
Temperature
Sense
20
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9.3 Feature Description
9.3.1 Protection Mechanisms
The is designed to operate in the automotive environment. The protection mechanisms allow the device to be
robust against many system-level events such as load dump, reverse battery, short-to-ground and more.
There are three protection features which, if triggered, will cause the switch to automatically disable:
• Thermal Shutdown
• Current Limit (Versions A,B,E)
• Energy Limit
When any of these protections are triggered, the device will enter the FAULT state. In the FAULT state, the fault
indication will be available on both the SNS pin and the ST pin (see the diagnostic section of the data sheet for
more details).
The switch is no longer held off and the fault indication is reset when all of the below conditions are met:
• LATCH pin is low
• tRETRY has expired
• All faults are cleared (thermal shutdown, current limit, energy limit)
9.3.1.1 Thermal Shutdown
The includes temperature sensors on the FET and inside of the device controller. When TJ,FET > TABS, the device
will see a thermal shutdown fault. After the fault is detected, the switch will turn off. The fault is cleared when the
switch temperature decreases by the hysteresis value, THYS.
9.3.1.2 Current Limit
When IOUT reaches the current limit threshold, ICL, the device can switch off immediately (Versions A,B,E), or the
device can remain enabled and limit IOUT (Versions C/D) to ICL (see Device Comparison Table section for more
details). In the case that the device remains enabled and limits IOUT, the thermal shutdown and/or energy limit
protection feature may be triggered due to the high amount of power dissipation in the device.
During a short circuit event, the device will hit the ICL threshold that is listed in the Specifications (for the given
device version) and then turn the output off or regulate the output current to protect the device. The device will
register a short circuit event when the output current exceeds ICL, however the measured maximum current may
exceed the ICL threshold due to the deglitch filter and turn-off time. The device is guaranteed to protect itself
during a short circuit event over the nominal supply voltage range (as defined in the Specifications section) at
125°C.
9.3.1.2.1 Current Limit Foldback
The implements a current limit foldback feature that is designed to protect the device in the case of a long-term
fault condition. If the device undergoes three consecutive fault shutdown events (any of thermal shutdown,
current limit, or energy limit), the current limit will be reduced to half of the original value. The device will revert
back to the original current limit threshold if either of the following occurs:
• The device goes to Standby Delay.
• The switch turns-on and turns-off without any fault occurring.
9.3.1.2.2 Selectable Current Limit Threshold
The offers two current limit thresholds. The high threshold is designed to allow for a large transient load current
(for example, inrush current of a 65-W bulb). The low threshold is designed to provide improved system-level
protection for loads that do not have large transient currents (for example, heating element). The lower threshold
can allow for reduced size/cost in the current carrying components such as PCB traces and module connectors.
Version A (20 A current limit) is ideal for charging capacitors, as it will enable the device to prevent inrush current
and clamp the overcurrent to linearly charge the capacitor.
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Feature Description (continued)
9.3.1.2.3 Undervoltage Lockout (UVLO)
The device monitors the supply voltage VBB to prevent unpredicted behaviors in the event that the supply voltage
is too low. When the supply voltage falls down to VUVLOF, the output stage is shut down automatically. When the
supply rises up to VUVLOR, the device turns back on.
During an initial ramp of VBB from 0 V at a ramp rate slower than 1 V/ms, VEN pin will have to be held low until
VBB is above UVLO threshold (with respect to board ground) and the supply voltage to the device has reliably
reached above the UVLO condition. For best operation, ensure that VBB has risen above UVLO before setting the
VEN pin to high.
9.3.1.2.4 VBB during Short-to-Ground
When VOUT is shorted to ground, the module power supply (VBB) can have a transient decrease. This is caused
by the sudden increase in current flowing through the wiring harness cables. To achieve ideal system behavior, it
is recommended that the module maintain VBB > 3 V during VOUT short-to-ground. This is typically accomplished
by placing bulk capacitance on the power supply node.
9.3.1.3 Energy Limit
The energy limiting feature is implemented to protect the switch from excessive stress. The device will
continuously monitor the amount of energy dissipated in the FET. If the energy limit threshold is reached, the
switch will automatically disable. In practice, the energy limit will only be reached during a fault event such as
short-to-ground.
Energy limit events have the same system-level behavior as thermal shutdown events.
9.3.1.4 Voltage Transients
The contains two voltage clamps which protect the device against system-level voltage transients.
The clamp from VBB to GND is primarily used to protect the controller from positive transients on the supply line
(for example, ISO7637-2). The clamp from VBB to VOUT is primarily used to limit the voltage across the FET when
switching off an inductive load. Both clamp levels are set to protect the device during these fault conditions. If the
voltage potential from VBB to GND exceeds the VBB clamp level, the clamp will allow current to flow through the
device from VBB to GND (Path 2). If the voltage potential from VBB to VOUT exceeds VCLAMP, the power FET will
allow current to flow from VBB to VOUT (Path 3).
Ri
Positive Supply Transient
(e.g. ISO7637 pulse 2a/3b)
(1)
VBB
VDS
Clamp
(3)
(2)
Controller
VBB
Clamp
VOUT
Load
GND
Figure 39. Current Path During Supply Voltage Transient
22
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Feature Description (continued)
9.3.1.4.1 Load Dump
The is tested according to ISO 16750-2:2010(E) suppressed load dump pulse. The device supports up to 40 V
load dump transient. The switch will maintain normal operation during the load dump pulse. If the switch is
enabled, it will stay enabled. If the switch is disabled, it will stay disabled.
9.3.1.4.2 Driving Inductive and Capacitive Loads
15
15
10
10
5
5
0
0
-5
-5
-10
-10
-15
-15
-20
-20
IVBB
VBB -25
VOUT -30
EN
-35
0.0056
-25
-30
-35
0.0008
0.0016
0.0024
0.0032 0.004
Time (s)
0.0048
Voltage (V)
Current (A)
When switching off an inductive load, the inductor may impose a negative voltage on the output of the switch.
The includes a voltage clamp to limit voltage across the FET. The maximum acceptable load inductance is a
function of the device robustness. With a 5 mH load, the can withstand a single pulse of 95 mJ inductive
dissipation at 125°C and can withstand 56 mJ of inductive dissipation with a 10 Hz repetitive pulse. If the
application parameters exceed this device limit, it is necessary to use a protection device like a freewheeling
diode to dissipate the energy stored in the inductor. Figure 40 shows the discharging a 5 mH load that is driven
at 5 A.
Indu
Figure 40. Inductive Discharge (5 mH, 5 A)
In addition, the current limit provides an ideal way to charge a capacitive load safely with limited inrush current.
With no protection, charging a large capacitive load can lead to high inrush currents that pull a supply down,
however by using the low current limit device options the capacitive load can be safely charged.
For more information on driving inductive or capacitive loads, reference TI's "How To Drive Inductive, Capacitive,
and Lighting Loads with Smart High Side Switch application report.
9.3.1.5 Reverse Battery
In the reverse battery condition, the switch will automatically be enabled (regardless of EN status) to prevent
power dissipation inside the MOSFET body diode. In many applications (for example, resistive load), the full load
current may be present during reverse battery. In order to activate the automatic switch on feature, the SEL2 pin
must have a path to module ground. This may be path 1 as shown below, or, if the SEL2 pin is unused, the path
may be through RPROT to module ground.
Protection features (for example, thermal shutdown) are not available during reverse battery. Care must be taken
to ensure that excessive power is not dissipated in the switch during the reverse battery condition.
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Feature Description (continued)
There are two options for blocking reverse current in the system. Option 1 is to place a blocking device (FET or
diode) in series with the battery supply. This will block all current paths. Option 2 is to place a blocking diode in
series with the GND node of the high-side switch. This method will protect the controller portion of the switch
(path 2), but it will not prevent current from flowing through the load (path 3). The diode used for Option 2 may be
shared amongst multiple high-side switches.
Path 1 shown in Figure 41 is blocked inside of the device.
Reverse blocking
FET or diode
BAT
Option 1
0V VBB
µC
VDD
(3)
(2)
Controller
GPIO
GPIO
RPROT
VOUT
VBB
Clamp
Load
(1)
GND
Option 2
13.5V
Figure 41. Current Path During Reverse Battery
9.3.1.6 Fault Event – Timing Diagrams
NOTE
All timing diagrams assume that the SELx pins are set to 00.
The LATCH, DIA_EN, and EN pins are controlled by the user. The timing diagrams
represent a possible use-case.
Figure 42 shows the immediate current limit switch off behavior of Versions A,B,E. The diagram also illustrates
the retry behavior. As shown, the switch will remain latched off until the LATCH pin is low.
24
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Feature Description (continued)
µC resets
the latch
LATCH
DIA_EN
ISNSFH
SNS
High-z
Current
Sense
High-z
High-z
Current
Sense
High-z
ST
VOUT
EN
tRETRY
ICL
IOUT
t
Load reaches limit.
Switch is Disabled.
Switch follows EN. Normal
operation.
Figure 42. Current Limit – Version A,B,E - Latched Behavior
Figure 43 shows the immediate current limit switch off behavior of versions A,B,E. In this example, LATCH is tied
to GND; hence, the switch will retry after the fault is cleared and tRETRY has expired.
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Feature Description (continued)
DIA_EN
ISNSFH
SNS
High-z
Current
Sense
High-z
High-z
Current
Sense
High-z
ST
VOUT
EN
tRETRY
ICL
IOUT
t
Load reaches limit.
Switch is Disabled.
Switch follows EN. Normal
operation.
Figure 43. Current Limit – Version A,B,E - LATCH = 0
Figure 44 shows the active current limiting behavior of versions C,D. In versions C,D, the switch will not
shutdown until either the energy limit or the thermal shutdown is reached.
26
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Feature Description (continued)
µC resets
the latch
LATCH
DIA_EN
ISNSFH
SNS
High-z
Current
Sense
High-z
High-z
Current
Sense
High-z
ST
VOUT
EN
TABS
THYS
TJ
tRETRY
ICL
IOUT
t
Load reaches limit. Current is limited. Temp
reaches limit.
Switch is disabled. Temp decreases by
THYS
Switch follows EN. Normal
operation.
Figure 44. Current Limit – Version C,D - Latched Behavior
Figure 45 shows the active current limiting behavior of versions C,D. The switch will not shutdown until either
thermal shutdown or energy limit is tripped. In this example, LATCH is tied to GND.
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Feature Description (continued)
DIA_EN
ISNSFH
SNS
High-z
Current
Sense
ISNSFH
High-z
High-z
Current
Sense
High-z
ST
VOUT
EN
TABS
THYS
TJ
tRETRY
ICL
IOUT
t
Load reaches limit. Current is limited.
Temp reaches limit.
Switch is disabled. TJ decreases by
THYS
Switch follows EN. Normal operation.
Figure 45. Current Limit – Version C,D - LATCH = 0
When the switch retries after a shutdown event, the SNS fault indication will remain until VOUT has risen to VBB –
1.8 V. Once VOUT has risen, the SNS fault indication is reset and current sensing is available. ST fault indication
is reset as soon as the switch is re-enabled (does not wait for VOUT to rise). If there is a short-to-ground and VOUT
is not able to rise, the SNS fault indication will remain indefinitely. The following diagram illustrates auto-retry
behavior and provides a zoomed-in view of the fault indication during retry.
NOTE
Figure 46 assumes that tRETRY has expired by the time that TJ reaches the hysteresis
threshold.
LATCH = 0 V and DIA_EN = 5 V
28
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Feature Description (continued)
ISNSFH
ISNSFH
ISNSFH
ISNSFH
SNS
ST
VOUT
EN
TABS
THYS
TJ
t
ISNSFH
ISNSI
SNS
ST
VBB ± 1.8 V
VOUT
EN
TABS
THYS
TJ
t
Figure 46. Fault Indication During Retry
9.3.2 Diagnostic Mechanisms
9.3.2.1 VOUT Short-to-Battery and Open-Load
9.3.2.1.1 Detection With Switch Enabled
When the switch is enabled, the VOUT short-to-battery and open-load conditions can be detected with the current
sense feature. In both cases, the load current will be measured through the SNS pin and will be below the
expected value.
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Feature Description (continued)
9.3.2.1.2 Detection With Switch Disabled
While the switch is disabled, if DIA_EN is high, an internal comparator will detect the condition of VOUT. If the
load is disconnected (open load condition) or there is a short to battery the OUT voltage will be higher than the
open load threshold (VOL,off) and a fault is indicated on the SNS pin. An internal pull-up of 1 MΩ is in series with
an internal MOSFET switch, so no external component is required if only a completely open load needs to be
detected. However, if there is significant leakage or other current draw even when the load is disconnected, a
lower value pull-up resistor and switch can be added externally to set the VOUT voltage above the VOL,off during
open load conditions.
(1)
This figure assumes that the device ground and the load ground are at the same potential. In application, there may
be a ground shift voltage of 1 V to 2 V.
Figure 47. Short to Battery and Open Load Detection
The detection circuitry is only enabled when DIA_EN = HIGH and EN = LOW.
If VOUT > VOL, the SNS pin will go to the fault level.
If VOUT < VOL, then there is no fault indication.
The fault indication will only occur if the SEL1 pin is set to diagnose the channel.
While the switch is disabled and DIA_EN is high, the fault indication mechanisms will continuously represent the
present status. For example, if VOUT decreases from >VOL to 200µs
ENABLE
PWM (up to 99%
duty cycle)
VOUT
t < tWD
On
(100% Duty
Cycle)
5µs < t <
20µs(1)
ENABLE
VOUT
t = tWD
ENABLE
Fault Condition
VOUT
t = tWD
ENABLE
Fault Recovery
VOUT
The watchdog feature requires that a PWM is applied to the switch enable pin. To maintain VOUT at 100% duty cycle,
the microcontroller should periodically apply a short pulse to the enable pin. This short pulse will reset the watchdog
timer, but will not cause the switch to turn-off. The pulse must be >5 μs to ensure that it is recognized by the device.
There is no upper limit on the pulse width; however, if the pulse is longer than 20 μs, the switch may start to transition
from enabled to disabled.
Figure 51. Enable Watchdog - Overview
Figure 52 illustrates the behavior of the watchdog feature.
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DIA_EN
ISNSFH
SNS
High-z
Current
Sense
High-z
High-z
Current
Sense
High-z
ST
VOUT
t = tWD
EN
t
(QDEOH SLQ LV KLJK IRU W • WWD.
Switch is disabled until a rising edge of
EN.
Normal operation.
Figure 52. Enable Watchdog Timing Diagram
9.4 Device Functional Modes
9.4.1 Off
Off state occurs when the device is not powered.
9.4.2 Standby
Standby state is a low-power mode used to reduce power consumption to the lowest level. Diagnostic
capabilities are not available in Standby mode.
9.4.3 Diagnostic
Diagnostic state may be used to perform diagnostics while the switch is disabled.
9.4.4 Standby Delay
The Standby Delay state is entered when EN and DIA_EN are low. After tSTBY, if the EN and DIA_EN pins are
still low, the device will go to Standby State.
9.4.5 Active
In Active state, the switch is enabled. The diagnostic functions may be turned on or off during Active state.
9.4.6 Fault
The Fault state is entered if a fault shutdown occurs (thermal shutdown, current limit, energy limit). After all faults
are cleared, the LATCH pin is low, and the retry timer has expired, the device will transition out of Fault state. If
the Enable pin is high, the switch will re-enable. If the Enable pin is low, the switch will remain off.
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Device Functional Modes (continued)
VBB < UVLO
OFF
ANY STATE
VBB > UVLO
EN = Low
DIA_EN = Low
t > tSTBY
STANDBY
EN = Low
DIA_EN = High
EN = Low DIA_EN = Low
EN = High
DIA_EN = X
DIAGNOSTIC
STANDBY DELAY
EN = Low DIA_EN = High
EN = High
DIA_EN = X
EN = Low
DIA_EN = High
ACTIVE
EN = Low
DIA_EN = Low
EN = High
DIA_EN = X
!OT_ABS & !OT_REL & !ILIM & !ELIMIT &
LATCH = Low & tRETRY expired
OT_ABS || OT_REL || ILIM ||
ELIMIT
FAULT
Figure 53. State Diagram
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
VBB
BAT
DIA_EN
RPROT
CVBB
SEL1
RPROT
GND
RGND
SEL2
RPROT
DGND
(1)
EN
RPROT
Microcontroller
(1)
LATCH
Load
RPROT
VOUT
COUT
RPU
ST
RPROT
Legend
ADC
SNS
RPROT
Chassis GND
RSNS
Module GND
Device GND
CSNS
(1) With the ground protection network, the
device ground will be offset relative to the
microcontroller ground.
With the ground protection network, the device ground will be offset relative to the microcontroller ground.
Figure 54. System Diagram
Table 4. Recommended External Components
COMPONENT
TYPICAL VALUE
RPROT
15 kΩ
Protect microcontroller and device I/O pins
RSNS
1 kΩ
Translate the sense current into sense voltage
RPU
10 kΩ
Provide pull-up source for open-drain output
CSNS
100 pF - 10 nF
RGND
4.7 kΩ
DGND
BAS21 Diode
CVBB
COUT
38
PURPOSE
Low-pass filter for the ADC input
Stabilize GND potential during turn-off of inductive load
Protects device during reverse battery
220 nF to Device GND
Filtering of voltage transients (for example, ESD, ISO7637-2) and improved
emissions
100 nF to Module GND
Stabilize the input supply and filter out low frequency noise.
22 nF
Filtering of voltage transients (for example, ESD, ISO7637-2)
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10.1.1 Ground Protection Network
As discussed in the section regarding Reverse Battery, DGND may be used to prevent excessive reverse current
from flowing into the device during a reverse battery event. Additionally, RGND is placed in parallel with DGND if
the switch is used to drive an inductive load. The ground protection network (DGND and RGND) may be shared
amongst multiple high-side switches.
A minimum value for RGND may be calculated by using the absolute maximum rating for IGND. During the reverse
battery condition, IGND = VBB / RGND:
RGND ≥ VBB / IGND
• Set VBB = –13.5 V
• Set IGND = –50 mA (absolute maximum rating)
RGND ≥ –13.5 V / –50 mA = 270 Ω
(1)
In this example, it is found that RGND must be at least 270 Ω. It is also necessary to consider the power
dissipation in RGND during the reverse battery event:
PRGND = VBB2 / RGND
(2)
2
PRGND = (13.5 V) / 270 Ω = 0.675 W
In practice, RGND may not be rated for such a high power. In this case, a larger resistor value should be selected.
10.1.2 Interface With Microcontroller
The ground protection network will cause the device ground to be at a higher potential than the module ground
(and microcontroller ground). This offset will impact the interface between the device and the microcontroller.
Logic pin voltage will be offset by the forward voltage of the diode. For input pins (for example, EN), the designer
must consider the VIH specification of the switch and the VOH specification of the microcontroller. For a system
that does not include DGND, it is required that VOH > VIH. For a system that does include DGND, it is required that
VOH > (VIH + VF). VF is the forward voltage of DGND.
For use of the status pin, ST, a similar consideration is necessary. The designer must consider the VOL, ST
specification and the VIL specification of the microcontroller. For a system that includes DGND, it is required that
VOL, ST + VF < VIL, µC.
The sense resistor, RSNS, should be terminated to the microcontroller ground. In this case, the ADC can
accurately measure the SNS signal even if there is an offset between the microcontroller ground and the device
ground.
10.1.3
I/O Protection
RPROT is used to protect the microcontroller I/O pins during system-level voltage transients such as ISO pulses or
reverse battery. A large resistance value ensures that current through the pin is limited to a safe level.
10.1.4 Inverse Current
Inverse current occurs when 0 V < VBB < VOUT. In this case, current may flow from VOUT to VBB. Inverse current
cannot be caused by a purely resistive load. However, a capacitive or inductive load can cause inverse current.
For example, if there is a significant amount of load capacitance and the VBB node has a transient droop, VOUT
may be greater than VBB.
will not detect inverse current. When the switch is enabled, inverse current will pass through the switch. When
the switch is disabled, inverse current may pass through the MOSFET body diode. The device will continue
operating in the normal manner during an inverse current event.
10.1.5 Loss of GND
The ground connection may be lost either on the device level or on the module level. If the ground connection is
lost, both switches will be disabled. If the switch was already disabled when the ground connection was lost, the
switch will remain disabled. When the ground is reconnected, normal operation will resume.
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10.1.6 Automotive Standards
10.1.6.1 ISO7637-2
is tested according to the ISO7637-2:2011 (E) standard. The test pulses are applied both with the switches
enabled and disabled. The test setup includes only the DUT and minimal external components: CVBB, COUT,
DGND, and RGND.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as: “The function does not
perform as designed during the test but returns automatically to normal operation after the test”.
Table 5. ISO7637-2:2011 (E) Results
TEST PULSE SEVERITY LEVEL WITH
STATUS II FUNCTIONAL PERFORMANCE
LEVEL
US
MINIMUM NUMBER
OF PULSES OR TEST
TIME
IV
–150 V
500 pulses
2a
III
+55 V
2b
IV
+10 V
3a
III
3b
III
TEST
PULSE
1
BURST CYCLE / PULSE REPETITION TIME
MIN
MAX
0.5 s
--
500 pulses
0.20
5s
10 pulses
0.5 s
5s
–165 V
1 hour
90 ms
100 ms
+112 V
1 hour
90 ms
100 ms
10.1.6.2 AEC – Q100-012 Short Circuit Reliability
The is tested according to the AEC - Q100-012 Short Circuit Reliability standard. This test is performed to
demonstrate the robustness of the device against VOUT short-to-ground events. Test results are summarized in
Table 6. For further details, refer to the AEC - Q100-012 standard document or TI's Short Circuit Reliability Test
for Smart Power Switches application report.
Test conditions:
• LATCH = 0 V
• TA = –40ºC
• 10 units from 3 separate lots for a total of 30 units
• Lsupply = 5 μH, Rsupply = 10 mΩ
• VBB = 14 V
Test procedure:
• Parametric data is collected on each unit pre-stress
• Each unit is enabled into a short circuit with the required short circuit cycles or duration as specified
• Parametric data is re-collected on each unit post-stress to verify that no parametric shift is observed
The cold repetitive test is run at –40ºC which is the worst case condition for the . The current limit threshold is
highest at cold temperature; hence, the short-circuit pulse contains more energy at cold temperature. The cold
repetitive test refers to the device being given time to cool down between pulses, within than being run at a cold
temperature. The load short circuit is the worst case situation, since the energy stored in the cable inductance
can cause additional harm. The fast response of the device ensures current limiting occurs quickly and at a
current close to the load short condition. In addition, the hot repetitive test is performed as well.
Table 6. AEC - Q100-012 Test Results
TEST
LOCATION OF SHORT
DEVICE
VERSION
NO. OF
CYCLES
NO. OF
UNITS
NO. OF
FAILS
Cold Repetitive - Long Pulse
Load Short Circuit, Lshort = 5 μH,
Rshort = 100 mΩ, TA = –40ºC
D
200 k
30
0
Hot Repetitive - Long Pulse
Terminal Short Circuit, Lshort = 5 μH,
Rshort = 100 mΩ, TA = 25ºC
D
100 hours
30
0
40
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10.1.7 Thermal Information
When outputting current, the will heat up due to the power dissipation. Figure 55 shows the transient thermal
impedance curve that can be used to determine the device temperature during 1 W pulse of a given length.
35
30
ZTTJ (qC/W)
25
20
15
10
5
0
0.0001
0.001 0.002
0.005 0.01 0.02
0.05
0.1
0.2 0.3 0.5
Time (s)
1
2
3 4 5 67 10
20 30 50
100
200
400
TPS1
Figure 55. Transient Thermal Impedance
10.2 Typical Application
This application example demonstrates how the device can be used to power resistive heater loads as in seat
heaters. Figure 56 shows a typical application where the load is a resistive seat heater. This document highlights
the basics of this type of application, however for a more detailed discussion reference TI's Smart Power Switch
Seat Heater Reference Design.
DIA_EN
SEL1
SEL2
µC
SNS
ST
LATCH
TPS1HA08-Q1
EN
12-V Battery
VBB
VOUT
GND
Load
Figure 56. Block Diagram for Powering Heater Loads
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Typical Application (continued)
10.2.1 Design Requirements
For this design example, use the input parameters shown in Table 7.
Table 7. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VBB
12.8 V
Heater Load
90 W max
Load Current Sense
100 mA to 20 A
Ambient temperature
85°C
RθJA
32.8°C/W (depending on PCB)
10.2.2 Detailed Design Procedure
10.2.2.1 Thermal Considerations
The DC current under maximum load power condition will be around 7.03 A. Power dissipation in the switch is
calculated in Equation 3. RON is assumed to be 20 mΩ because this is the maximum specification. In practice,
RON will be lower.
PFET = I2 × RON
PFET = (7.03 A)2 × 20 mΩ = 0.988 W
(3)
(4)
The junction temperature of the device can be calculated using Equation 5 and the RθJA value from the
Specifications section.
TJ = TA + RθJA × PFET
TJ = 85°C + 32.8°C/W × 0.988 W = 117.4°C
(5)
The maximum junction temperature rating for device is TJ = 150°C. Based on the above example calculation, the
device temperature will stay below the maximum rating.
10.2.2.2 Diagnostics
If the resistive heating load is disconnected (heater malfunction), an alert is desired. Open-load detection can be
performed in the switch-enabled state via the current sense feature of the device. Alternatively, under open load
condition in off-state with diagnostics enabled, the current in the SNS pin will be the fault current and the can be
detected from the sense voltage measurement.
10.2.2.2.1 Selecting the RISNS Value
Table 8 shows the requirements for the load current sense in this application. The KSNS value is specified for the
device and can be found in the Specifications section.
Table 8. RSNS Calculation Parameters
PARAMETER
EXAMPLE VALUE
Current Sense Ratio (KSNS)
4600
Largest diagnosable load current
20 A
Smallest diagnosable load current
50 mA
Full-scale ADC voltage
5V
ADC resolution
10 bit
The load current measurement requirements of 20 A ensures that current can be sensed up to the 20 A current
limit, while the low level of 100 mA allows for accurate measurement of low load currents.
The RSNS resistor value should be selected such that the largest diagnosable load current puts VSNS at about
90% of the ADC full-scale. With this design, any ADC value above 90% can be considered a fault. Additionally,
the RSNS resistor value should ensure that the smallest diagnosable load current does not cause VSNS to fall
below 1 LSB of the ADC. With the given example values, a 1-kΩ sense resistor satisfies both requirements
shown in Table 9.
42
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Table 9. VSNS Calculation
LOAD (A)
SENSE RATIO
ISNS (mA)
RSNS (Ω)
VSNS (V)
% OF 5-V ADC
0.050
4600
0.011
1000
0.011
0.22%
20.000
4600
4.348
1000
4.348
87%
10.2.3 Application Curves
Figure 57 shows the behavior of the in this application when the MCU provides an enable pulse to beginning
heating the resistive element. Shortly after the EN pin goes high, the load current begins to flow and the SNS pin
measures the output current.
Figure 57. Heater Turn-on Time
By measuring the voltage on the SNS pin, the can communicate back to the system MCU what the load current
is. Figure 58 shows that when the seat heater approaches full load and IOUT jumps from a low load current of 1 A
up to a 5 A load current, the load step is mirrored on the SNS pin.
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Figure 58. SNS Response During Heater Load Step
One common concern in these type of applications is that the heating element can accidentally lose connection,
creating an open load situation. In this case, it is ideal for the to recognize that the load has been removed and
report a FLT to the MCU. Figure 59 shows the behavior of the when there is no load attached. As soon as the
DIAG_EN pin is engaged, the SNS output goes high and the ST output engages low. By monitoring these pins,
the MCU can recognize there is a fault and notify the user that maintenance is required.
Figure 59. Open Load Detection If Heating Element is Missing
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30
20
24
IVBB (A)
ST (V)
20
SNS (V)
EN (V)
16
15
12
10
8
5
4
0
0
Current (A)
25
-5
0
0.00015
0.0003
0.00045
Time (s)
0.0006
Voltage (V)
Importantly, the will also protect the system in the event of a short-circuit. Figure 60 shows the behavior of the
device if it is enabled into a short circuit condition. If this is using the device option C, the current will be clamped
to the current limit ICL until it hits an over temperature event, at which point it will shut down. In this way, the
system is protected from unchecked overcurrent in the event of a short circuit.
-4
0.00075
C_Pe
Figure 60. Overcurrent Behavior During Short Circuit Event
11 Power Supply Recommendations
The is designed to operate in a 12-V automotive system. The nominal supply voltage range is 8 V to 18 V. The
device is also designed to withstand voltage transients beyond this range. When operating outside of the nominal
voltage range, the device will exhibit normal functional behavior. However, parametric specifications may not be
guaranteed.
Table 10. Operating Voltage Range
VBB Voltage Range
Note
3 V to 8 V
Transients such as cold crank and start-stop, functional operation
guaranteed but some parametric specifications may not apply. The
device is completely short-circuit protected up to 125°C
8 V to 18 V
Nominal supply voltage, all parametric specifications apply. The
device is completely short-circuit protected up to 125°C
18 V to 40 V
Transients such as jump-start and load-dump, functional operation
guaranteed but some parametric specifications may not apply
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12 Layout
12.1 Layout Guidelines
To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer,
the pour may extend beyond the pad dimensions as shown in the example below. In addition to this, it is
recommended to also have a VBB plane either on one of the internal PCB layers or on the bottom layer. Vias
should connect this plane to the top VBB pour.
has 6 VOUT pins. All VOUT pins must be shorted together on the PCB. Additionally, the layout should ensure that
the current path is symmetrical for both sides of the device. If the path is not symmetrical, there will be some
imbalance in current spreading across the power FET. This can impact accuracy of the current sense
measurement.
12.2 Layout Example
GND
DIA_EN
SNS
SEL2
LATCH
SEL1
To µC
To µC
EN
NC
VBB
ST
NC
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
Figure 61. PWP Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Related Documentation
For related documentation see the following:
• TI's "How To Drive Inductive, Capacitive, and Lighting Loads with Smart High Side Switch
• Short Circuit Reliability Test for Smart Power Switches
• TI's Smart Power Switch Seat Heater Reference Design
• Reverse Battery Protection for High Side Switches
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS1HA08AQPWPRQ1
ACTIVE
HTSSOP
PWP
16
3000
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168HRS
-40 to 125
1HA08A
TPS1HA08BQPWPRQ1
ACTIVE
HTSSOP
PWP
16
3000
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168HRS
-40 to 125
1HA08B
TPS1HA08CQPWPRQ1
ACTIVE
HTSSOP
PWP
16
3000
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168HRS
-40 to 125
1HA08C
TPS1HA08DQPWPRQ1
ACTIVE
HTSSOP
PWP
16
3000
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168HRS
-40 to 125
1HA08D
TPS1HA08EQPWPRQ1
ACTIVE
HTSSOP
PWP
16
3000
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168HRS
-40 to 125
1HA08E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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