TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
POWER-DISTRIBUTION SWITCHES
Check for Samples: TPS2020-Q1, TPS2021-Q1, TPS2022-Q1, TPS2024-Q1
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
33-mΩ (5-V Input) High-Side MOSFET Switch
Short-Circuit and Thermal Protection
Overcurrent Logic Output
Operating Range: 2.7 V to 5.5 V
Logic-Level Enable Input
Typical Rise Time: 6.1 ms
Undervoltage Lockout
Maximum Standby Supply Current: 10 mA
No Drain-Source Back-Gate Diode
Available in 8-Pin SOIC Package
•
•
•
Ambient Temperature Range: –40°C to 85°C
ESD Protection: 2-kV Human-Body Model,
200-V Machine Model
UL Listed - File No. E169910
D PACKAGE
(TOP VIEW)
GND
IN
IN
EN
1
8
2
7
3
6
4
5
OUT
OUT
OUT
OC
DESCRIPTION
The TPS202x family of power distribution switches is intended for applications where heavy capacitive loads and
short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power
switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS202x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a
thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present.
The TPS202x devices differ only in short-circuit current threshold. The TPS2020 limits at 0.3-A load, the
TPS2021 at 0.9-A load, the TPS2022 at 1.5-A load, and the TPS2024 at 3-A load. The TPS202x is available in
an 8-pin small-outline integrated-circuit (SOIC) package and operates over a junction temperature range of
–40°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
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ORDERING INFORMATION (1)
TA
ENABLE
–40°C to 85°C
(1)
(2)
PACKAGED DEVICES (2)
RECOMMENDED MAXIMUM
CONTINUOUS LOAD
CURRENT
(A)
TYPICAL SHORT-CIRCUIT
CURRENT LIMIT AT 25°C
(A)
0.2
0.3
TPS2020IDRQ1
0.6
0.9
TPS2021IDRQ1
1
1.5
TPS2022DRQ1
2
3
TPS2024IDRQ1
Active low
SMALL OUTLINE
(D)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTIONAL BLOCK DIAGRAM
Power Switch
†
CS
IN
OUT
Charge
Pump
EN
Current
Limit
Driver
OC
UVLO
Thermal
Sense
GND
†Current
Sense
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
EN
4
I
Enable input. Logic-low turns on power switch.
GND
1
I
Ground
2, 3
I
Input voltage
5
O
Overcurrent. Logic output, active-low
6, 7, 8
O
Power-switch output
IN
OC
OUT
2
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
DETAILED DESCRIPTION
Power Switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled.
Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
Enable (EN)
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce the
supply current to less than 10 mA when a logic-high is present on EN. A logic-zero input on EN restores bias to
the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS
logic levels.
Overcurrent (OC)
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed.
Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
Thermal Sense
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately
140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20°C, the
switch turns back on. The switch continues to cycle off and on until the fault is removed.
Undervoltage Lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
Copyright © 2004–2010, Texas Instruments Incorporated
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VI(IN)
(2)
VO(OUT)
Input voltage range
(2)
–0.3 V to 6 V
Output voltage range
VI(EN)
Input voltage range
IO(OUT)
Continuous output current
–0.3 V to VI(IN) + 0.3 V
–0.3 V to 6 V
Internally limited
Continuous total power dissipation
See Dissipation Rating Table
TJ
Operating virtual junction temperature range
–40°C to 125°C
Tstg
Storage temperature range
–65°C to 150°C
ESD
Electrostatic discharge protection
Human body model
(1)
(2)
2 kV
Machine model
200 V
Charged device model (CDM)
750 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
RECOMMENDED OPERATING CONDITIONS
VI(IN)
VI(EN)
IO
TJ
4
MIN
MAX
2.7
5.5
V
0
5.5
V
TPS2020
0
0.2
TPS2021
0
0.6
TPS2022
0
1
TPS2024
0
2
–40
125
Input voltage
Continuous output current
Operating virtual junction temperature
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UNIT
A
°C
Copyright © 2004–2010, Texas Instruments Incorporated
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TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 0 V (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
TJ (2)
MIN
TYP
MAX
25°C
33
43.5
85°C
38
57.5
125°C
44
62.5
25°C
37
48.5
85°C
43
68.5
125°C
51
87
25°C
30
43.5
125°C
43
62.5
UNIT
Power Switch
VI(IN) = 5 V, IO = 1.8 A
VI(IN) = 3.3 V, IO = 1.8 A
VI(IN) = 5 V, IO = 1 A
VI(IN) = 3.3 V, IO = 1 A
rDS(on)
Static drain-source on-state
resistance
VI(IN) = 5 V, IO = 0.18 A
VI(IN) = 3.3 V, IO = 0.18 A
tr
Rise time, output
tf
Fall time, output
VI(IN) = 5 V, IO = 0.6 A
TPS2021
VI(IN) = 3.3 V, IO = 0.6 A
TPS2021
VI(IN) = 5.5 V, CL = 1 mF, RL = 10 Ω
25°C
31
48.5
125°C
48
87
25°C
30
34
85°C
35
41
125°C
39
47
25°C
33
37
85°C
39
46
125°C
44
56
25°C
33
36
125°C
44
48
25°C
37
40
125°C
51
59
6.1
25°C
VI(IN) = 2.7 V, CL = 1 mF, RL = 10 Ω
VI(IN) = 5.5 V, CL = 1 mF, RL = 10 Ω
ms
8.6
3.4
25°C
VI(IN) = 2.7 V, CL = 1 mF, RL = 10 Ω
mΩ
ms
3
Enable Input (EN)
VIH
High-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
Full range
4.5 V ≤ VI(IN) ≤ 5.5 V
Full range
0.8
2.7 V ≤ VI(IN) ≤ 4.5 V
Full range
0.5
2
V
VIL
Low-level input voltage
II
Input current
EN = 0 V or EN = VI(IN)
Full range
ton
Turnon time
CL = 100 mF, RL= 10 Ω
Full range
20
toff
Turnoff time
CL = 100 mF, RL= 10 Ω
Full range
40
–0.5
0.5
V
mA
ms
Current Limit
IOS
Short-circuit output current
VI = 5.5 V,
OUT connected to GND,
Device enabled into short circuit
TPS2020
0.22
0.3
0.4
TPS2021
0.66
0.9
1.1
1.1
1.5
1.8
2
3
4.2
TPS2022
25°C
TPS2024
(1)
(2)
A
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
Full range TJ = -40°C to 125°C
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 0 V (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
TJ (2)
MIN
TYP
MAX
UNIT
Supply Current
Supply current, low-level output
No load on OUT, EN = VI(IN)
Supply current, high-level output
No load on OUT, EN = 0 V
Leakage current
OUT connected to ground, EN = VI(IN)
25°C
0.3
Full range
1
10
25°C
58
75
Full range
75
100
Full range
10
mA
mA
mA
Undervoltage Lockout
Low-level input voltage
Full range
Hysteresis
25°C
2
2.5
100
V
mV
Overcurrent (OC)
Output low voltage
IO = 10 mA, VOL(OC)
Full range
0.4
V
Off-state current (3)
VO = 5 V, VO = 3.3 V
Full range
1
mA
(3)
6
Specified by design.
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TPS2022-Q1, TPS2024-Q1
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
PARAMETER MEASURMENT INFORMATION
OUT
RL
tf
tr
CL
VO(OUT)
90%
10%
90%
10%
TEST CIRCUIT
50%
VI(EN)
50%
toff
ton
90%
VO(OUT)
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
Table 1. Timing Diagrams
FIGURE
Turnon Delay and Rise TIme
2
Turnoff Delay and Fall Time
3
Turnon Delay and Rise TIme with 1-mF Load
4
Turnoff Delay and Rise TIme with 1-mF Load
5
Device Enabled into Short
6
TPS2020 Ramped Load on Enabled Device
7
TPS2021 Ramped Load on Enabled Device
8
TPS2022 Ramped Load on Enabled Device
9
TPS2024 Ramped Load on Enabled Device
10
TPS2024, Inrush Current
11
7.9-Ω Load Connected to an Enabled TPS2020 Device
12
3.7-Ω Load Connected to an Enabled TPS2020 Device
13
3.7-Ω Load Connected to an Enabled TPS2021 Device
14
2.6-Ω Load Connected to an Enabled TPS2021 Device
15
2.6-Ω Load Connected to an Enabled TPS2022 Device
16
1.2-Ω Load Connected to an Enabled TPS2022 Device
17
0.9-Ω Load Connected to an Enabled TPS2024 Device
18
0.5-Ω Load Connected to an Enabled TPS2024 Device
19
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
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VI(EN) (5 V/div)
VI(EN) (5 V/div)
VI(EN)
VI(EN)
VI(IN) = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VO(OUT) (2 V/div)
VIN = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT)
0
2
4
6
8
10
12
14
16
18
VO(OUT)
0
20
2
4
6
Figure 2. Turnon Delay and Rise Time
10
12
14
16
18
20
Figure 3. Turnoff Delay and Fall Time
VI(EN) (5 V/div)
VI(EN) (5 V/div)
VI(EN)
VI(EN)
VO(OUT) (2 V/div)
VO(OUT) (2 V/div)
VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT)
0
2
4
6
8
10
12
14
16
18
20
Figure 4. Turnon Delay and Rise Time with 1-mF
Load
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VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT)
t − Time − ms
8
8
t − Time − ms
t − Time − ms
0
2
4
6
8
10
12
14
16
18
20
t − Time − ms
Figure 5. Turnoff Delay and Fall Time with 1-mF
Load
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
VO(OC) (5 V/div)
VI(EN)
VI(EN) (5 V/div)
VO(OC)
VI(IN) = 5 V
TA = 25°C
VI(IN) = 5 V
TA = 25°C
TPS2024
TPS2023
IO(OUT) (500 mA/div)
TPS2022
TPS2021
TPS2020
IO(OUT)
IO(OUT)
IO(OUT) (1 A/div)
0
1
2
3
4
5
6
7
8
9
0
10
20
40
60
80 100 120 140 160 180 200
t − Time − ms
t − Time − ms
Figure 6. Device Enabled Into Short
Figure 7. TPS2020, Ramped Load on Enabled
Device
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VO(OC)
VI(IN) = 5 V
TA = 25°C
VI(IN) = 5 V
TA = 25°C
IO(OUT) (1 A/div)
IO(OUT) (1 A/div)
IO(OUT)
IO(OUT)
0
20
40
60
80 100 120 140 160 180 200
t − Time − ms
Figure 8. TPS2021, Ramped Load on Enabled
Device
Copyright © 2004–2010, Texas Instruments Incorporated
0
20
40
60
80 100 120 140 160 180 200
t − Time − ms
Figure 9. TPS2022, Ramped Load on Enabled
Device
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
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VO(OC) (5 V/div)
VI(EN)
VI(EN) (5 V/div)
VO(OC)
VI(IN) = 5 V
TA = 25°C
470 µF
150 µF
IO(OUT) (1 A/div)
II(IN) (500 mA/div)
II(IN)
IO(OUT)
RL = 10 Ω
TA = 25°C
47 µF
0
20
40
60
0
80 100 120 140 160 180 200
1
2
3
4
5
6
7
8
9
10
t − Time − ms
t − Time − ms
Figure 10. TPS2024, Ramped Load on Enabled
Device
Figure 11. TPS2024, Inrush Current
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VO(OC)
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
IO(OUT) (200 mA/div)
IO(OUT) (500 mA/div)
VI(IN) = 5 V
RL = 7.9 Ω
TA = 25°C
IO(OUT)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
Figure 12. 7.9-Ω Load Connected to an Enabled
TPS2020 Device
10
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IO(OUT)
0
50 100 150 200 250 300 350 400 450 500
t − Time − µs
Figure 13. 3.7-Ω Load Connected to an Enabled
TPS2020 Device
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VO(OC)
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
IO(OUT) (1 A/div)
IO(OUT) (1 A/div)
IO(OUT)
IO(OUT)
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
50 100 150 200 250 300 350 400 450 500
t − Time − µs
t − Time − µs
Figure 14. 3.7-Ω Load Connected to an Enabled
TPS2021 Device
Figure 15. 2.6-Ω Load Connected to an Enabled
TPS2021 Device
VO(OC)
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VI(IN) = 5 V
RL = 1.2 Ω
TA = 25°C
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
IO(OUT) (1 A/div)
IO(OUT)
IO(OUT) (1 A/div)
IO(OUT)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
Figure 16. 2.6-Ω Load Connected to an Enabled
TPS2022 Device
Copyright © 2004–2010, Texas Instruments Incorporated
0
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
Figure 17. 1.2-Ω Load Connected to an Enabled
TPS2022 Device
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
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VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VO(OC)
VI(IN) = 5 V
RL = 0.5 Ω
TA = 25°C
VI(IN) = 5 V
RL = 0.9 Ω
TA = 25°C
IO(OUT) (5 A/div)
IO(OUT) (5 A/div)
IO(OUT)
IO(OUT)
0
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
Figure 18. 0.9-Ω Load Connected to an Enabled
TPS2024 Device
12
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0
50 100 150 200 250 300 350 400 450
500
t − Time − µs
Figure 19. 0.5-Ω Load Connected to an Enabled
TPS2024 Device
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TPS2022-Q1, TPS2024-Q1
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
TYPICAL CHARACTERISTICS
Table 2. Typical Characteristics Graphs
FIGURE
td(on)
Turnon delay time
vs Output voltage
23
td(off)
Turnoff delay time
vs Input voltage
24
tr
Rise time
vs Load current
25
tf
Fall time
vs Load current
26
Supply current (enabled)
vs Junction temperature
27
Supply current (disabled)
vs Junction temperature
28
Supply current (enabled)
vs Input voltage
29
Supply current (disabled)
vs Input voltage
30
vs Input voltage
31
vs Junction temperature
32
vs Input voltage
33
vs Junction temperature
34
vs Input voltage
35
vs Junction temperature
36
Undervoltage lockout
37
IOS
Short-circuit current limit
rDS(on)
Static drain-source on-state resistance
VI
Input voltage
TURNON DELAY TIME
vs
OUTPUT VOLTAGE
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
7.5
18
6.5
6
5.5
5
t d(off)
t d(on) − Turn-on Delay Time − ms
7
− Turn-off Delay Time − ms
TA = 25°C
CL = 1 µF
4.5
TA = 25°C
CL = 1 µF
17.5
17
16.5
4
3.5
2.5
3
5
3.5
4
4.5
VI − Input Voltage − V
Figure 20.
Copyright © 2004–2010, Texas Instruments Incorporated
5.5
6
16
2.5
3
3.5
4
4.5
5
VI − Input Voltage − V
5.5
6
Figure 21.
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TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
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RISE TIME
vs
LOAD CURRENT
FALL TIME
vs
LOAD CURRENT
6.5
3.5
TA = 25°C
CL = 1 µF
TA = 25°C
CL = 1 µF
t f − Fall Time − ms
t r − Rise Time − ms
3.25
6
5.5
3
2.75
5
2.5
0
0.5
1.5
1
IL − Load Current − A
2
0
Figure 23.
SUPPLY CURRENT (ENABLED)
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT (DISABLED)
vs
JUNCTION TEMPERATURE
VI(IN) = 5.5 V
Supply Current (Disabled) − µ A
Supply Current (Enabled) − µ A
2
5
VI(IN) = 5 V
55
VI(IN) = 4 V
45
VI(IN) = 3.3 V
VI(IN) = 5.5 V
VI(IN) = 5 V
4
3
2
1
VI(IN) = 4 V
VI(IN) = 3.3 V
0
VI(IN) = 2.7 V
VI(IN) = 2.7 V
35
−1
−50 −25
0
25
50
75
100 125
TJ − Junction Temperature − °C
Figure 24.
14
1
1.5
IL − Load Current − A
Figure 22.
75
65
0.5
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150
−50 −25
75
100 125
0
25
50
TJ − Junction Temperature − °C
150
Figure 25.
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TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
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SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
SUPPLY CURRENT (ENABLED)
vs
INPUT VOLTAGE
SUPPLY CURRENT (DISABLED)
vs
INPUT VOLTAGE
75
5
TJ = 85°C
Supply Current (Disabled) − µ A
Supply Current (Enabled) − µ A
TJ = 125°C
65
55
45
TJ = 25°C
3
TJ = 85°C
2
1
TJ = 25°C
0
TJ = 0°C
TJ = 0°C
TJ = −40°C
TJ = −40°C
35
−1
2.5
3
3.5
4
4.5
5
VI − Input Voltage − V
5.5
6
2.5
5
3.5
4
4.5
VI − Input Voltage − V
3
Figure 26.
Figure 27.
SHORT-CIRCUIT CURRENT LIMIT
vs
INPUT VOLTAGE
SHORT-CIRCUIT CURRENT LIMIT
vs
JUNCTION TEMPERATURE
3.5
5.5
6
3.5
TPS2024
TPS2024
I OS − Short-Circuit Current Limit − A
TA = 25°C
I OS − Short-Circuit Current Limit − A
TJ = 125°C
4
3
2.5
TPS2023
2
TPS2022
1.5
1
TPS2021
0.5
TPS2020
0
2
3
5
4
VI − Input Voltage − V
Figure 28.
Copyright © 2004–2010, Texas Instruments Incorporated
6
3
2.5
TPS2023
2
TPS2022
1.5
TPS2021
1
TPS2020
0.5
0
−50
−25
0
50
75
25
TJ − Junction Temperature − °C
100
Figure 29.
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15
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
www.ti.com
− Static Drain-Source On-State Resistance − m Ω
IO = 0.18 A
50
TJ = 125°C
40
TJ = 25°C
30
TJ = −40°C
3
4
4.5
5
3.5
VI − Input Voltage − V
5.5
6
60
IO = 0.18 A
50
VI = 2.7 V
40
VI = 3.3 V
30
VI = 5.5 V
20
−50 −25
r
20
2.5
DS(on)
60
50
75 100
0
25
TJ − Junction Temperature − °C
125
150
Figure 31.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
60
IO = 1.8 A
50
TJ = 125°C
40
TJ = 25°C
TJ = −40°C
30
20
3
3.5
4
4.5
5
VI − Input Voltage − V
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5.5
6
DS(on)
− Static Drain-Source On-State Resistance − m Ω
Figure 30.
Figure 32.
16
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
r
r
DS(on)
− Static Drain-Source On-State Resistance − m Ω
r DS(on) − Static Drain-Source On-State Resistance − m Ω
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
60
IO = 1.8 A
50
VI = 3.3 V
VI = 4 V
VI = 5.5 V
40
30
20
−50 −25
25
0
50
75 100
TJ − Junction Temperature − °C
125
150
Figure 33.
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TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
UNDERVOLTAGE LOCKOUT
2.5
VI − Input Voltage − V
2.4
Start Threshold
2.3
2.2
Stop Threshold
2.1
2
−50
Copyright © 2004–2010, Texas Instruments Incorporated
0
50
100
TJ − Temperature − °C
Figure 34.
150
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TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
www.ti.com
APPLICATION INFORMATION
TPS2024
2,3
Power Supply
2.7 V to 5.5 V
10 kΩ
IN
0.1 µF
OUT
6,7,8
Load
0.1 µF
5
4
22 µF
OC
EN
GND
1
Figure 35. Typical Application
Power Supply Considerations
A 0.01-mF to 0.1-mF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load is
heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,
bypassing the output with a 0.01-mF to 0.1-mF ceramic capacitor improves the immunity of the device to
short-circuit transients.
Overcurrent
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant
output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present
long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied, see Figure 6. The TPS202x senses the short and
immediately switches into a constant-current output.
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figures 13–22).
After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figures 7–11). The TPS202x is capable of delivering current up to the current-limit threshold
without damaging the device. Once the threshold has been reached, the device switches into its constant-current
mode.
OC Response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter can be connected
to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers
the inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.
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TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
TPS202x
TPS202x
GND
OUT
IN
OUT
IN
EN
V+
V+
GND
OUT
IN
OUT
OUT
IN
OUT
OC
EN
OC
Rpullup
Rpullup
Rfilter
Cfilter
Figure 36. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses
Power Dissipation and Junction Temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it is
good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at the
input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of
interest and read rDS(on) from Figures 33–36. Next, calculate the power dissipation using:
PD = rDS(on) × I2
(1)
Finally, calculate the junction temperature:
TJ = PD × RqJA + TA
(2)
where:
TA = Ambient temperature °C
RqJA = Thermal resistance—SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get an acceptable answer.
Thermal Protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS202x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to
the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection
circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense
circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues
to cycle in this manner until the load fault or input power is removed.
Undervoltage Lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage
falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion
systems where it is not possible to turn off the power switch before input power is removed. The UVLO also
keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is
enabled. Upon reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage
overshoots.
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TPS2022-Q1, TPS2024-Q1
SGLS260G – SEPTEMBER 2004 – REVISED JUNE 2010
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Generic Hot-Plug Applications
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications (see Figure 37). Such implementations require the control of current
surges seen by the main power supply and the card being inserted. The most effective way to control these
surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a
power supply normally turns on. Because of the controlled rise times and fall times of the TPS202x series, these
devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO
feature of the TPS202x also ensures the switch is off after the card has been removed, and the switch remains
off during the next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion
of the card or module.
PC Board
TPS2024
GND
OUT
Power
Supply
2.7 V to 5.5 V
1000 µF
Optimum
0.1 µF
IN
OUT
IN
OUT
EN
OC
Block of
Circuitry
Overcurrent Response
Figure 37. Typical Hot-Plug Implementation
By placing the TPS202x between the VCC input and the rest of the circuitry, the input power reaches this device
first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage ramp at the
output of the device. This implementation controls system surge currents and provides a hot-plugging
mechanism for any device.
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS2020IDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2020I
TPS2021IDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T2021Q
TPS2022DRG4Q1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2022Q1
TPS2022DRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2022Q1
TPS2024IDRG4Q1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2024Q1
TPS2024IDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2024Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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