TPS2030D

TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 POWER-DISTRIBUTION SWITCHES FEATURES 1 • • • • • • • • • • 33-mΩ (5-V Input) High-Side MOSFET Switch Short-Circuit and Thermal Protection Overcurrent Logic Output Operating Range: 2.7 V to 5.5 V Logic-Level Enable Input Typical Rise Time: 6.1 ms Undervoltage Lockout Maximum Standby Supply Current: 10 μA No Drain-Source Back-Gate Diode Available in 8-pin SOIC and PDIP Packages • • • Ambient Temperature Range, –40°C to 85°C 2-kV Human-Body-Model, 200-V Machine-Model ESD Protection UL Listed– File No. E169910 D OR P PACKAGE (TOP VIEW) GND IN IN EN 1 8 2 7 3 6 4 5 OUT OUT OUT OC DESCRIPTION The TPS203x family of power distribution switches is intended for applications where heavy capacitive loads and short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the TPS203x limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is present. The TPS203x devices differ only in short-circuit current threshold. The TPS2030 limits at 0.3-A load, the TPS2031 at 0.9-A load, the TPS2032 at 1.5-A load, the TPS2033 at 2.2-A load, and the TPS2034 at 3-A load (see Available Options). The TPS203x is available in an 8-pin small-outline integrated-circuit (SOIC) package and in an 8-pin dual-in-line (DIP) package and operates over a junction temperature range of –40°C to 125°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2007, Texas Instruments Incorporated TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS TA ENABLE –40°C to 85°C (1) (2) PACKAGED DEVICES (1) RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT (A) TYPICAL SHORT-CIRCUIT CURRENT LIMIT AT 25°C (A) SMALL OUTLINE (D) (2) PLASTIC DIP (P) 0.2 0.3 TPS2030D TPS2030P 0.6 0.9 TPS2031D TPS2031P 1 1.5 TPS2032D TPS2032P 1.5 2.2 TPS2033D TPS2033P 2 3 TPS2034D TPS2034P Active high For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2030DR) TPS2030 FUNCTIONAL BLOCK DIAGRAM Power Switch † CS IN OUT Charge Pump EN Current Limit Driver OC UVLO Thermal Sense GND †Current Sense TERMINAL FUNCTIONS TERMINAL NO. D OR P I/O EN 4 I Enable input. Logic high turns on power switch. GND 1 I Ground 2, 3 I Input voltage 5 O Overcurrent. Logic output active low 6, 7, 8 O Power-switch output NAME IN OC OUT 2 DESCRIPTION Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 DETAILED DESCRIPTION POWER SWITCH The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (VI(IN) = 5 V). Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. CHARGE PUMP An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current. DRIVER The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range. ENABLE (EN) The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce the supply current to less than 10 μA when a logic low is present on EN . A logic high input on EN restores bias to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS logic levels. OVERCURRENT (OC) The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed. CURRENT SENSE A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant current mode and holds the current constant while varying the voltage on the load. THERMAL SENSE An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately 140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20°C, the switch turns back on. The switch continues to cycle off and on until the fault is removed. UNDERVOLTAGE LOCKOUT A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch. Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 3 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VI(IN) (2) Input voltage range VO(OUT) (2) Output voltage range VI(EN) Input voltage range IO(OUT) Continuous output current VALUE UNIT –0.3 to 6 V –0.3 to VI(IN) + 0.3 V –0.3 to 6 V Internally limited Continuous total power dissipation See Dissipation Rating Table °C TJ Operating virtual junction temperature range –40 to 125 Tstg Storage temperature range –65 to 150 °C 2 kV Machine model 200 V Charged device model (CDM) 750 V Human body model ESD (1) (2) Electrostatic discharge protection: Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. DISSIPATION RATING TABLE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 725 mW 5.8 mW°C 464 mW 377 mW P 1175 mW 9.4 mW°C 752 mW 611 mW PACKAGE RECOMMENDED OPERATING CONDITIONS Input voltage IO TJ 4 Continuous output current MIN MAX VI(IN) 2.7 5.5 V VI(EN) 0 5.5 V TPS2030 0 0.2 TPS2031 0 0.6 TPS2032 0 1 TPS2033 0 1.5 TPS2034 0 2 –40 125 Operating virtual junction temperature Submit Documentation Feedback UNIT A °C Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 5 V (unless otherwise noted) POWER SWITCH TEST CONDITIONS (1) PARAMETER rDS(on) tr tf (1) Static drain-source on-state resistance Rise time, output Fall time, output TYP MAX VI(IN) = 5 V, TJ = 25°C, IO = 1.8 A MIN 33 36 VI(IN) = 5 V, TJ = 85°C, IO = 1.8 A 38 46 VI(IN) = 5 V, TJ = 125°C, IO = 1.8 A 44 50 VI(IN) = 3.3 V, TJ = 25°C, IO = 1.8 A 37 41 VI(IN) = 3.3 V, TJ = 85°C, IO = 1.8 A 43 52 VI(IN) = 3.3 V, TJ = 125°C, IO = 1.8 A 51 61 VI(IN) = 5 V, TJ = 25°C, IO = 0.18 A 30 34 VI(IN) = 5 V, TJ = 85°C, IO = 0.18 A 35 41 VI(IN) = 5 V, TJ = 125°C, IO = 0.18 A 39 47 VI(IN) = 3.3 V, TJ = 25°C, IO = 0.18 A 33 37 VI(IN) = 3.3 V, TJ = 85°C, IO = 0.18 A 39 46 VI(IN) = 3.3 V, TJ = 125°C, IO = 0.18 A 44 56 VI(IN) = 5.5 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω 6.1 VI(IN) = 2.7 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω 8.6 VI(IN) = 5.5 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω 3.4 VI(IN) = 2.7 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω 3 UNIT mΩ ms ms Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. ENABLE INPUT (EN) PARAMETER VIH TEST CONDITIONS MIN 2.7 V ≤ VI(IN) ≤ 5.5 V high-level input voltage TYP MAX UNIT 2 V 4.5 V ≤ VI(IN) ≤ 5.5 V 0.8 2.7 V ≤ VI(IN) ≤ 4.5 V 0.5 VIL Low-level input voltage II Input current EN = 0 V or EN = VI(IN) ton Turnon time CL = 100 μF, RL = 10 Ω 20 toff Turnoff time CL = 100 μF, RL = 10 Ω 40 –0.5 V μA 0.5 ms CURRENT LIMIT TEST CONDITIONS (1) PARAMETER IOS (1) Short-circuit output current TJ = 25°C, VI = 5.5 V, OUT connected to GND, Device enable into short circuit MIN TYP MAX TPS2030 0.22 0.3 0.4 TPS2031 0.66 0.9 1.1 TPS2032 1.1 1.5 1.8 TPS2033 1.65 2.2 2.7 TPS2034 2.2 3 3.8 UNIT A Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 5 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (Continued) over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 5 V (unless otherwise noted) SUPPLY CURRENT PARAMETER TEST CONDITIONS Supply current, low-level output No Load on OUT EN = 0 Supply current, high-level output No Load on OUT EN = VI(IN) Leakage current OUT connected to ground EN = 0 MIN TJ = 25°C TYP MAX 0.3 1 40°C ≤ TJ ≤ 125°C 10 TJ = 25°C 58 75 40°C ≤ TJ ≤ 125°C 75 100 40°C ≤ TJ ≤ 125°C 10 UNIT μA μA μA UNDERVOLTAGE LOCKOUT PARAMETER TEST CONDITIONS Low-level input voltage MIN TYP 2 Hysteresis TJ = 25°C MAX 2.5 100 UNIT V mV OVERCURRENT (OC) Output low voltage IO = 10 mA, VOL(OC) Off-state current (1) VO = 5 V, VO = 3.3 V (1) 6 0.4 V 1 μA Specified by design, not production tested. Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION OUT RL tf tr CL VO(OUT) 90% 10% 90% 10% TEST CIRCUIT 50% VI(EN) 50% toff ton 90% VO(OUT) 10% VOLTAGE WAVEFORMS Figure 1. Test Circuit and Voltage Waveforms TABLE OF TIMING DIAGRAMS FIGURE Turnon Delay and Rise Time 2 Turnoff Delay and Fall Time 3 Turnon Delay and Rise Time with 1-μF Load 4 Turnoff Delay and Rise TIME with 1-μF Load 5 Device Enabled Into Short 6 TPS2030, TPS2031, TPS2032, TPS2033, and TPS2034, Ramped Load on Enabled Device 7, 8, 9, 10, 11 TPS2034, Inrush Current 12 7.9-Ω Load Connected to an Enabled TPS2030 Device 13 3.7-Ω Load Connected to an Enabled TPS2030 Device 14 3.7-Ω Load Connected to an Enabled TPS2031 Device 15 2.6-Ω Load Connected to an Enabled TPS2031 Device 16 2.6-Ω Load Connected to an Enabled TPS2032 Device 17 1.2-Ω Load Connected to an Enabled TPS2032 Device 18 1.2-Ω Load Connected to an Enabled TPS2033 Device 19 0.9-Ω Load Connected to an Enabled TPS2033 Device 20 0.9-Ω Load Connected to an Enabled TPS2034 Device 21 0.5-Ω Load Connected to an Enabled TPS2034 Device 22 Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 7 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 VI(EN) (5 V/div) VI(EN) (5 V/div) VI(EN) VI(EN) VI(IN) = 5 V RL = 27 Ω TA = 25°C VO(OUT) (2 V/div) VO(OUT) (2 V/div) VIN = 5 V RL = 27 Ω TA = 25°C VO(OUT) 0 2 4 6 8 10 12 14 16 18 VO(OUT) 0 20 2 4 6 10 12 14 16 18 t − Time − ms Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Fall Time VI(EN) (5 V/div) 20 VI(EN) (5 V/div) VI(EN) VI(EN) VO(OUT) (2 V/div) VO(OUT) (2 V/div) VI(IN) = 5 V CL = 1 µF RL = 27 Ω TA = 25°C VO(OUT) 0 8 8 t − Time − ms 2 4 6 8 10 12 14 16 18 VI(IN) = 5 V CL = 1 µF RL = 27 Ω TA = 25°C VO(OUT) 20 0 2 4 6 8 10 12 14 16 18 20 t − Time − ms t − Time − ms Figure 4. Turnon Delay and Rise Time With 1-µF Load Figure 5. Turnoff Delay and Fall Time With 1-μF Load Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 VO(OC) (5 V/div) VI(EN) VI(EN) (5 V/div) VO(OC) VI(IN) = 5 V TA = 25°C VI(IN) = 5 V TA = 25°C TPS2034 TPS2033 IO(OUT) (500 mA/div) TPS2032 TPS2031 TPS2030 IO(OUT) IO(OUT) IO(OUT) (1 A/div) 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 t − Time − ms 80 100 120 140 160 180 200 t − Time − ms Figure 6. Device Enabled Into Short Figure 7. TPS2030, Ramped Load on Enabled Device VO(OC) (5 V/div) VO(OC) VO(OC) (5 V/div) VO(OC) VI(IN) = 5 V TA = 25°C VI(IN) = 5 V TA = 25°C IO(OUT) (1 A/div) IO(OUT) (1 A/div) IO(OUT) IO(OUT) 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 t − Time − ms t − Time − ms Figure 8. TPS2031, Ramped Load on Enabled Device Figure 9. TPS2032, Ramped Load on Enabled Device Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 9 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 VO(OC) (5 V/div) VO(OC) (5 V/div) VO(OC) VO(OC) VI(IN) = 5 V TA = 25°C VI(IN) = 5 V TA = 25°C IO(OUT) (1 A/div) IO(OUT) (1 A/div) IO(OUT) IO(OUT) 0 20 40 60 0 80 100 120 140 160 180 200 20 40 60 80 100 120 140 160 180 200 t − Time − ms t − Time − ms Figure 10. TPS2033, Ramped Load on Enabled Device Figure 11. TPS2034, Ramped Load on Enabled Device VI(EN) VO(OC) (5 V/div) VI(EN) (5 V/div) VO(OC) IO(OUT) (200 mA/div) 470 µF 150 µF II(IN) (500 mA/div) II(IN) RL = 10 Ω TA = 25°C 47 µF 0 1 2 3 4 5 6 7 8 t − Time − ms Figure 12. TPS2034, Inrush Current 10 Submit Documentation Feedback 9 VI(IN) = 5 V RL = 7.9 Ω TA = 25°C IO(OUT) 10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 t − Time − µs Figure 13. 7.9-Ω Load Connected to an Enabled TPS2030 Device Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 VO(OC) (5 V/div) VO(OC) (5 V/div) VO(OC) VO(OC) VI(IN) = 5 V RL = 3.7 Ω TA = 25°C VI(IN) = 5 V RL = 3.7 Ω TA = 25°C IO(OUT) (500 mA/div) IO(OUT) IO(OUT) (1 A/div) IO(OUT) 0 50 100 150 200 250 300 350 400 450 500 0 t − Time − µs 200 400 600 800 1000 1200 1400 1600 1800 2000 t − Time − µs Figure 14. 3.7-Ω Load Connected to an Enabled TPS2030 Device Figure 15. 3.7-Ω Load Connected to an Enabled TPS2031 Device VO(OC) VO(OC) (5 V/div) VO(OC) (5 V/div) VO(OC) VI(IN) = 5 V RL = 2.6 Ω TA = 25°C VI(IN) = 5 V RL = 2.6 Ω TA = 25°C IO(OUT) (1 A/div) IO(OUT) IO(OUT) (1 A/div) IO(OUT) 0 50 100 150 200 250 300 350 400 450 500 t − Time − µs Figure 16. 2.6-Ω Load Connected to an Enabled TPS2031 Device Copyright © 1998–2007, Texas Instruments Incorporated 0 200 400 600 800 1000 1200 1400 1600 1800 2000 t − Time − µs Figure 17. 2.6-Ω Load Connected to an Enabled TPS2032 Device Submit Documentation Feedback Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 11 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 VO(OC) (5 V/div) VO(OC) (5 V/div) VO(OC) VO(OC) VI(IN) = 5 V RL = 1.2 Ω TA = 25°C IO(OUT) (1 A/div) IO(OUT) (2 A/div) IO(OUT) VI(IN) = 5 V RL = 1.2 Ω TA = 25°C IO(OUT) 0 100 200 300 400 500 600 700 800 900 1000 0 t − Time − µs 100 200 300 400 500 600 700 800 900 1000 t − Time − µs Figure 18. 1.2-Ω Load Connected to an Enabled TPS2032 Device Figure 19. 1.2-Ω Load Connected to an Enabled TPS2033 Device VO(OC) (5 V/div) VO(OC) (5 V/div) VO(OC) VO(OC) VI(IN) = 5 V RL = 0.9 Ω TA = 25°C VI(IN) = 5 V RL = 0.9 Ω TA = 25°C IO(OUT) (2 A/div) IO(OUT) (5 A/div) IO(OUT) IO(OUT) 0 100 200 300 400 500 600 700 800 900 1000 t − Time − µs Figure 20. 0.9-Ω Load Connected to an Enabled TPS2033 Device 12 Submit Documentation Feedback 0 100 200 300 400 500 600 700 800 900 1000 t − Time − µs Figure 21. 0.9-Ω Load Connected to an Enabled TPS2034 Device Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 VO(OC) (5 V/div) VO(OC) VI(IN) = 5 V RL = 0.5 Ω TA = 25°C IO(OUT) (5 A/div) IO(OUT) 50 100 150 200 250 300 350 400 450 0 500 t − Time − µs Figure 22. 0.5-Ω Load Connected to an Enabled TPS2034 Device TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE td(on) Turnon delay time vs Output voltage 23 td(off) Turnoff delay time vs Input voltage 24 tr Rise time vs Load current 25 tf Fall time vs Load current 26 Supply current (enabled) vs Junction temperature 27 Supply current (disabled) vs Junction temperature 28 Supply current (enabled) vs Input voltage 29 Supply current (disabled) vs Input voltage 30 vs Input voltage 31 vs Junction temperature 32 vs Input voltage 33 vs Junction temperature 34 vs Input voltage 35 vs Junction temperature 36 Undervoltage lockout 37 IOS Short-circuit current limit rDS(on) Static drain-source on-state resistance VI Input voltage Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 13 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 TURNON DELAY TIME vs OUTPUT VOLTAGE TURNOFF DELAY TIME vs INPUT VOLTAGE 18 7.5 6.5 6 5.5 5 t d(off) t d(on) − Turn-on Delay Time − ms 7 − Turn-off Delay Time − ms TA = 25°C CL = 1 µF 4.5 TA = 25°C CL = 1 µF 17.5 17 16.5 4 3.5 2.5 3 3.5 4 4.5 5 VI − Input Voltage − V 5.5 16 2.5 6 3 3.5 4 4.5 5 VI − Input Voltage − V Figure 23. Figure 24. RISE TIME vs LOAD CURRENT FALL TIME vs LOAD CURRENT 6.5 5.5 6 3.5 TA = 25°C CL = 1 µF TA = 25°C CL = 1 µF t f − Fall Time − ms t r − Rise Time − ms 3.25 6 5.5 3 2.75 5 2.5 0 0.5 1 1.5 IL − Load Current − A Figure 25. 14 Submit Documentation Feedback 2 0 0.5 1 1.5 IL − Load Current − A 2 Figure 26. Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 SUPPLY CURRENT (ENABLED) vs JUNCTION TEMPERATURE SUPPLY CURRENT (DISABLED) vs JUNCTION TEMPERATURE 5 VI(IN) = 5.5 V Supply Current (Disabled) − µ A Supply Current (Enabled) − µ A 75 65 VI(IN) = 5 V 55 VI(IN) = 4 V 45 VI(IN) = 3.3 V VI(IN) = 5.5 V VI(IN) = 5 V 4 3 2 1 VI(IN) = 4 V VI(IN) = 3.3 V 0 VI(IN) = 2.7 V VI(IN) = 2.7 V 35 −1 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C 150 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C Figure 27. Figure 28. SUPPLY CURRENT (ENABLED) vs INPUT VOLTAGE SUPPLY CURRENT (DISABLED) vs INPUT VOLTAGE 75 150 5 TJ = 85°C Supply Current (Disabled) − µ A Supply Current (Enabled) − µ A TJ = 125°C 65 55 45 TJ = 25°C TJ = 125°C 4 3 TJ = 85°C 2 1 TJ = 25°C 0 TJ = 0°C TJ = 0°C TJ = −40°C TJ = −40°C 35 −1 2.5 3 3.5 4 4.5 5 VI − Input Voltage − V Figure 29. Copyright © 1998–2007, Texas Instruments Incorporated 5.5 6 2.5 3 3.5 4 4.5 5 VI − Input Voltage − V 5.5 6 Figure 30. Submit Documentation Feedback Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 15 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 SHORT-CIRCUIT CURRENT LIMIT vs INPUT VOLTAGE SHORT-CIRCUIT CURRENT LIMIT vs JUNCTION TEMPERATURE 3.5 3.5 TPS2034 TPS2034 I OS − Short-Circuit Current Limit − A I OS − Short-Circuit Current Limit − A TA = 25°C 3 2.5 TPS2033 2 TPS2032 1.5 1 TPS2031 0.5 TPS2030 0 2 3 5 4 VI − Input Voltage − V 3 2.5 TPS2033 2 TPS2031 1 TPS2030 0.5 0 −50 6 TPS2032 1.5 25 −25 0 50 75 TJ − Junction Temperature − °C Figure 31. Figure 32. 50 TJ = 125°C 40 TJ = 25°C 30 TJ = −40°C 3 3.5 4 4.5 5 VI − Input Voltage − V Figure 33. 16 − Static Drain-Source On-State Resistance − m Ω IO = 0.18 A Submit Documentation Feedback 5.5 6 DS(on) 60 r r DS(on) − Static Drain-Source On-State Resistance − m Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 20 2.5 100 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 60 IO = 0.18 A 50 VI = 2.7 V 40 VI = 3.3 V 30 VI = 5.5 V 20 −50 −25 50 75 100 0 25 TJ − Junction Temperature − °C 125 150 Figure 34. Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 50 TJ = 125°C 40 TJ = 25°C TJ = −40°C 30 20 3 3.5 4.5 5 4 VI − Input Voltage − V 5.5 6 DS(on) − Static Drain-Source On-State Resistance − m Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 60 IO = 1.8 A 60 IO = 1.8 A 50 VI = 3.3 V VI = 4 V 40 VI = 5.5 V 30 20 −50 −25 r r DS(on) − Static Drain-Source On-State Resistance − m Ω www.ti.com 0 25 50 75 100 TJ − Junction Temperature − °C Figure 35. 125 150 Figure 36. UNDERVOLTAGE LOCKOUT 2.5 VI − Input Voltage − V 2.4 Start Threshold 2.3 2.2 Stop Threshold 2.1 2 −50 0 50 100 TJ − Temperature − °C 150 Figure 37. Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 17 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 APPLICATION INFORMATION TPS2034 2,3 Power Supply 2.7 V to 5.5 V IN 0.1 µF 10 kΩ OUT 6,7,8 Load 0.1 µF 5 4 22 µF OC EN GND 1 Figure 38. Typical Application POWER SUPPLY CONSIDERATIONS A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load is heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients. OVERCURRENT A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 6). The TPS203x senses the short and immediately switches into a constant-current output. In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figure 13 through Figure 22). After the current-limit circuit has tripped (reached the overcurrent trip threshold) the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 7 through Figure 11). The TPS203x is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC RESPONSE The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from the inrush current flowing through the device, charging the downstream capacitor. An RC filter can be connected to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing a low impedance energy source, thereby reducing erroneous overcurrent reporting. 18 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 TPS203x TPS203x GND OUT IN OUT IN EN V+ V+ GND OUT IN OUT OUT IN OUT OC EN OC Rpullup Rpullup Rfilter Cfilter Figure 39. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses POWER DISSIPATION AND JUNCTION TEMPERATURE The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 33 through Figure 36. Next, calculate the power dissipation using: P D +r DS(on) I2 (1) Finally, calculate the junction temperature: T +P R )T J D qJA A (2) Where: TA = Ambient Temperature °C RθJA = Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get an acceptable answer. THERMAL PROTECTION Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS203x into constant current mode, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMI and voltage overshoots. Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 19 TPS2030, TPS2031 TPS2032, TPS2033, TPS2034 www.ti.com SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007 GENERIC HOT-PLUG APPLICATIONS (Figure 40) In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Because of the controlled rise times and fall times of the TPS203x series, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS203x also ensures the switch will be off after the card has been removed, and the switch will be off during the next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion of the card or module. PC Board TPS2034 GND OUT Power Supply 2.7 V to 5.5 V 1000 µF Optimum 0.1 µF IN OUT IN OUT EN OC Block of Circuitry Overcurrent Response Figure 40. Typical Hot-Plug Implementation By placing the TPS203x between the VCC input and the rest of the circuitry, the input power will reach this device first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device. 20 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS2030D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2030 TPS2030DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2030 TPS2030DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2030 TPS2030DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2030 TPS2030P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS2031D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2031 TPS2031DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2031 TPS2031DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2031 TPS2031DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2031 TPS2031P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS2032D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2032 TPS2032DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2032 TPS2032DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2032 TPS2032DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2032 TPS2033D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2033 TPS2033DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2033 TPS2033DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2033 Addendum-Page 1 TPS2030P TPS2031P Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS2033DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2033 TPS2034D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2034 TPS2034DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2034 TPS2034DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2034 TPS2034DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2034 TPS2034P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TPS2034P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF TPS2030, TPS2032 : • Automotive: TPS2030-Q1, TPS2032-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2030DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2031DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2032DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2033DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2034DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2030DR SOIC D 8 2500 340.5 338.1 20.6 TPS2031DR SOIC D 8 2500 340.5 338.1 20.6 TPS2032DR SOIC D 8 2500 340.5 338.1 20.6 TPS2033DR SOIC D 8 2500 340.5 338.1 20.6 TPS2034DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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