TPS2041B-Q1, TPS2042B-Q1, TPS2051B-Q1
TPS2041B-Q1,
TPS2042B-Q1,
TPS2051B-Q1
SLVS782D
– NOVEMBER
2007 – REVISED
OCTOBER 2020
SLVS782D – NOVEMBER 2007 – REVISED OCTOBER 2020
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TPS20xxB-Q1 Current-Limited Power-Distribution Switches
1 Features
3 Description
•
•
The TPS20xxB-Q1 power-distribution switches are
intended for applications where heavy capacitive
loads and short circuits are likely to be encountered.
These devices incorporate 105-mΩ N-channel
MOSFET power switches for power-distribution
systems that require multiple power switches in a
single package. Each switch is controlled by a logic
enable input. Gate drive is provided by an internal
charge pump designed to control the power-switch
rise times and fall times to minimize current surges
during switching. The charge pump requires no
external components and allows operation from
supplies as low as 2.7 V.
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C6
– Device MM ESD classification level M0
105-mΩ high-side MOSFET
500-mA continuous current
Thermal and short-circuit protection
Accurate current limit: 0.75 A (minimum), 1.25 A
(maximum)
Operating range: 2.7 V to 5.5 V
0.6-ms typical rise time
Undervoltage lockout
Deglitched fault report (OC)
No OC glitch during power up
Maximum standby supply current: 1 µA (single,
dual) or 2 µA (triple, quad)
Bidirectional switch
UL recognized under file number E169910
When the output load exceeds the current-limit
threshold or a short is present, the device limits the
output current to a safe level by switching into a
constant-current mode, pulling the overcurrent ( OCx)
logic output low. When continuous heavy overloads
and short circuits increase the power dissipation in the
switch, causing the junction temperature to rise, a
thermal protection circuit shuts off the switch to
prevent damage. Recovery from a thermal shutdown
is automatic once the device has cooled sufficiently.
Internal circuitry ensures that the switch remains off
until valid input voltage is present. This powerdistribution switch is designed to set current limit at
1 A (typical).
2 Applications
•
•
Heavy Capacitive Loads
Short-Circuit Protection
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS2041B-Q1
SOT-23 (5)
2.80 mm × 2.90 mm
TPS2042B-Q1,
TPS2051B-Q1
SOIC (8)
4.90 mm × 6.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
TPS2042B-Q1
2
Power Supply
2.7 V to 5.5 V
IN
OUT1
0.1 µF
8
3
Load
0.1 µF
22 µF
0.1 µF
22 µF
OC1
EN1
OUT2
5
OC2
4
7
6
Load
EN2
GND
1
Copyright © 2016, Texas Instruments Incorporated
Typical Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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© 2020 Texas
Instruments
Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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SLVS782D – NOVEMBER 2007 – REVISED OCTOBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagrams....................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................12
9 Application and Implementation.................................. 13
9.1 Application Information............................................. 13
9.2 Typical Applications.................................................. 13
10 Power Supply Recommendations..............................20
11 Layout........................................................................... 21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
11.3 Thermal Considerations.......................................... 21
12 Device and Documentation Support..........................22
12.1 Related Links.......................................................... 22
12.2 Receiving Notification of Documentation Updates..22
12.3 Support Resources................................................. 22
12.4 Trademarks............................................................. 22
12.5 Electrostatic Discharge Caution..............................22
12.6 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2016) to Revision D (October 2020)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
• Changed "70-mΩ High-Side MOSFET" to "105-mΩ High-Side MOSFET" in the Features list.......................... 1
• Changed "70-mΩ High-Side MOSFET" to "105-mΩ High-Side MOSFET" in the Description section................1
• Updated rDS(ON) TYP and MAX values in the Electrical Characteristics table.................................................... 5
• Updated Figure 6-9 ............................................................................................................................................7
• Changed "70-mΩ High-Side MOSFET" to "105-mΩ High-Side MOSFET" in the Overview section.................10
Changes from Revision B (October 2011) to Revision C (September 2016)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table; see POA at the end of the data sheet....................................................... 1
• Deleted General Switch Catalog image..............................................................................................................1
• Added AEC-Q100 Qualified bullets.................................................................................................................... 1
• Added Thermal Information table....................................................................................................................... 5
• Deleted Dissipation Ratings section .................................................................................................................. 7
• Combined Functional Block Diagrams for TPS2041B-Q1 and TPS2051B-Q1 as they are the same.............. 10
Changes from Revision A (June 2010) to Revision B (October 2011)
Page
• Changed orderable part number From: TPS2041QDBVRQ1 To: TPS2041BQDBVRQ1...................................1
Changes from Revision * (November 2007) to Revision A (June 2010)
Page
• Added the TPS2041B-Q1 device information.....................................................................................................1
2
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SLVS782D – NOVEMBER 2007 – REVISED OCTOBER 2020
5 Pin Configuration and Functions
OUT
1
GND
2
OC
5
3
GND
1
8
OC1
IN
2
7
OUT1
EN1
3
6
OUT2
EN2
4
5
OC2
IN
4
EN
Not to scale
Not to scale
Figure 5-1. TPS2041B-Q1 DBV Package 5-Pin
SOT-23 Top View
Figure 5-2. TPS2042B-Q1 D Package 8-Pin SOIC
Top View
GND
1
8
OUT
IN
2
7
OUT
IN
3
6
OUT
EN
4
5
OC
Not to scale
Figure 5-3. TPS2051B-Q1 D Package 8-Pin SOIC Top View
Table 5-1. Pin Functions: TPS2041B-Q1
PIN
NAME
NO.
TYPE
I
DESCRIPTION
EN
4
Enable input, logic low turns on power switch
GND
2
GND
Ground
IN
5
PWR
Supply input voltage
OC
3
O
Overcurrent, open-drain output, active low
OUT
1
O
Power-switch output
Table 5-2. Pin Functions: TPS2042B-Q1
PIN
NAME
NO.
TYPE
DESCRIPTION
EN1
3
I
Enable input, logic low turns on power switch IN-OUT1
EN2
4
I
Enable input, logic low turns on power switch IN-OUT2
GND
1
GND
Ground
IN
2
PWR
Supply input voltage
OC1
8
O
Overcurrent, open-drain output, active low, IN-OUT1
OC2
5
O
Overcurrent, open-drain output, active low, IN-OUT2
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Table 5-2. Pin Functions: TPS2042B-Q1 (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
OUT1
7
O
Power-switch output, IN-OUT1
OUT2
6
O
Power-switch output, IN-OUT2
Table 5-3. Pin Functions: TPS2051B-Q1
PIN
NAME
NO.
EN
4
GND
IN
OC
OUT
TYPE
I
DESCRIPTION
Enable input, logic high turns on power switch
1
GND
Ground
2, 3
PWR
Supply input voltage
5
O
Overcurrent open-drain output, active low
6, 7, 8
O
Power-switch output
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1)
Input
voltage(2)
MIN
MAX
UNIT
IN
–0.3
6
V
Output voltage(2)
OUT, OUTx
–0.3
6
V
Input voltage
ENx, EN
–0.3
6
V
Voltage, VI( OC), VI( OCx)
OC, OCx
–0.3
6
V
Continuous output current
Internally limited
Continuous total power dissipation
See ESD Ratings
Operating virtual-junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
6.2 ESD Ratings
VALUE
UNIT
TPS2041B-Q1 in DBV Package and TPS2042B-Q1 in D package
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2500
Charged-device model (CDM), per AEC Q100-011
±1500
Machine model (MM), per AEC Q100-003
V
±50
TPS2051B-Q1 in D package
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1500
Machine model (MM), per AEC Q100-003
(1)
4
V
±50
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SLVS782D – NOVEMBER 2007 – REVISED OCTOBER 2020
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
2.7
5.5
V
VI(IN)
Input voltage (IN)
VI( ENx),
VI(EN)
Input voltage ( ENx, EN)
0
5.5
V
IO(OUT),
IO(OUTx)
Continuous output current (OUT, OUTx)
0
500
mA
TJ
Operating virtual-junction temperature
–40
125
°C
6.4 Thermal Information
THERMAL METRIC(1)
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
DBV (SOT-23)
D (SOIC)
D (SOIC)
5 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
224.1
117.2
124.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
131.2
63.3
72.7
°C/W
RθJB
Junction-to-board thermal resistance
55.4
57.5
64.9
°C/W
ψJT
Junction-to-top characterization parameter
19.2
15.3
24.7
°C/W
ψJB
Junction-to-board characterization parameter
54.3
37
64.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI( ENx) = 0 V (unless
otherwise noted)
TEST CONDITIONS(1)
PARAMETER
MIN
TYP
MAX
UNIT
POWER SWITCH
rDS(ON)
Static drain-source on-state resistance,
5‑V or 3.3-V operation
VI(IN) = 5 V or 3.3 V,
IO = 0.5 A
–40°C ≤ TJ ≤ 125°C
105
160
Static drain-source on-state resistance,
2.7-V operation(2)
VI(IN) = 2.7 V, IO = 0.5 A
–40°C ≤ TJ ≤ 125°C
110
175
VI(IN) = 5.5 V
CL = 1 µF,
RL = 10 Ω
TJ = 25°C
0.6
1.5
0.4
1
CL = 1 µF,
RL = 10 Ω
TJ = 25°C
tr
Rise time, output(2)
tf
Fall time, output(2)
VI(IN) = 2.7 V
VI(IN) = 5.5 V
VI(IN) = 2.7 V
mΩ
0.05
0.5
0.05
0.5
ms
ms
ENABLE INPUT ( EN, ENx)
VIH
High-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
VIL
Low-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
2
0.8
II
Input current
VI( ENx) = 0 V or 5.5 V
ton
Turnon time(2)
CL = 100 µF, RL = 10 Ω
–0.5
0.5
3
toff
Turnoff time(2)
CL = 100 µF, RL = 10 Ω
10
V
µA
ms
CURRENT LIMIT
IOS
VI(IN) = 5 V, OUT connected to GND,
device enabled into short-circuit
Short-circuit output current
TJ = 25°C
–40°C ≤ TJ ≤ 125°C
0.65
1
1.25
0.6
1
1.3
A
SUPPLY CURRENT (TPS2041B-Q1, TPS2051B-Q1)
Supply current, low-level output
No load on OUT,
VI( EN) = 5.5 V or VI(EN) = 0 V
TJ = 25°C
0.5
1
–40°C ≤ TJ ≤ 125°C
0.5
5
Supply current, high-level output
No load on OUT,
VI( EN) = 0 V or VI(EN) = 5.5 V
TJ = 25°C
43
60
–40°C ≤ TJ ≤ 125°C
43
70
Leakage current
OUT connected to ground,
VI( EN) = 5.5 V or VI(EN) = 0 V
–40°C ≤ TJ ≤ 125°C
1
µA
Reverse leakage current
VI(OUTx) = 5.5 V, IN = ground(2)
TJ = 25°C
0
µA
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µA
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SLVS782D – NOVEMBER 2007 – REVISED OCTOBER 2020
6.5 Electrical Characteristics (continued)
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI( ENx) = 0 V (unless
otherwise noted)
TEST CONDITIONS(1)
PARAMETER
MIN
TYP
MAX
TJ = 25°C
0.5
1
–40°C ≤ TJ ≤ 125°C
0.5
5
TJ = 25°C
UNIT
SUPPLY CURRENT (TPS2042B-Q1)
Supply current, low-level output
No load on OUT, VI( ENx) = 5.5 V
Supply current, high-level output
No load on OUT, VI( ENx) = 0 V
50
70
–40°C ≤ TJ ≤ 125°C
50
90
Leakage current
OUT connected to ground, VI( ENx) = 5.5 V –40°C ≤ TJ ≤ 125°C
1
µA
0.2
µA
Reverse leakage current
VI(OUTx) = 5.5 V, IN =
ground(2)
TJ = 25°C
µA
µA
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN, INx
2
Hysteresis, IN, INx
TJ = 25°C
2.5
75
V
mV
OVERCURRENT ( OC, OCx)
Output low voltage, VOL( OCx)
IO( OCx) = 5 mA
OFF-state current(2)
VO( OCx) = 5 V or 3.3 V
OC deglitch(2)
OCx assertion or deassertion
4
8
0.4
V
1
µA
15
ms
THERMAL SHUTDOWN(3)
Thermal shutdown threshold(2)
Recovery from thermal
135
shutdown(2)
125
Hysteresis(2)
(1)
(2)
(3)
6
°C
°C
10
°C
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be accounted for
separately.
Specified by design.
The thermal shutdown only reacts under overcurrent conditions.
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6.6 Typical Characteristics
1.0
3.3
CL = 100 µF,
RL = 10 Ω,
TA = 25°C
0.9
3.2
0.7
Turnoff Time − ms
Turnon Time − ms
0.8
CL = 100 mF,
RL = 10 W,
TA = 255C
0.6
0.5
0.4
3.1
3
0.3
2.9
0.2
0.1
2.8
0
2
3
4
5
VI − Input Voltage − V
6
3
4
5
6
VI − Input Voltage − V
Figure 6-1. Turnon Time vs Input voltage
Figure 6-2. Turnoff Time vs Input Voltage
0.25
0.6
CL = 1 µF,
RL = 10 Ω,
TA = 25°C
CL = 1 µF,
RL = 10 Ω,
TA = 25°C
0.5
0.2
0.4
Fall Time − ms
Rise Time − ms
2
0.3
0.15
0.1
0.2
0.05
0.1
0
0
2
3
4
5
VI − Input Voltage − V
6
Figure 6-3. Rise Time vs Input Voltage
2
6
70
I I (IN) − Supply Current, Output Enabled − µ A
I I (IN) − Supply Current, Output Enabled − µA
4
5
VI − Input Voltage − V
Figure 6-4. Fall Time vs Input Voltage
60
VI = 5.5 V
50
VI = 5 V
40
30
VI = 2.7 V
20
VI = 3.3 V
10
0
−50
3
0
50
100
150
TJ − Junction Temperature − °C
Figure 6-5. TPS2041B-Q1 and TPS2051B-Q1
Supply Current, Output Enabled vs Junction
Temperature
VI = 5.5 V
60
50
VI = 5 V
VI = 3.3 V
40
30
VI = 2.7 V
20
10
0
−50
0
50
100
150
TJ − Junction Temperature − °C
Figure 6-6. TPS2042B-Q1 Supply Current, Output
Enabled vs Junction Temperature
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I I (IN) − Supply Current, Output Disabled − µ A
I I (IN) − Supply Current, Output Disabled − µ A
0.5
VI = 5.5 V
0.45
VI = 5 V
0.4
0.35
0.3
VI = 3.3 V
VI = 2.7 V
0.25
0.2
0.15
0.1
0.05
0
−50
0
50
100
0.5
VI = 5.5 V
0.45
VI = 5 V
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
−50
150
VI = 3.3 V
VI = 2.7 V
0
50
100
150
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 6-7. TPS2041B-Q1 and TPS2051B-Q1
Supply Current, Output Disabled vs Junction
Temperature
Figure 6-8. TPS2042B-Q1 Supply Current, Output
Disabled vs Junction Temperature
I OS − Short-Circuit Output Current − A
1.08
VI = 2.7 V
1.06
VI = 3.3 V
1.04
1.02
1.0
0.98
VI = 5 V
0.96
VI = 5.5 V
0.94
0.92
0.9
−50
Figure 6-9. Static Drain-Source ON-state
Resistance vs Junction Temperature
0
50
100
TJ − Junction Temperature − °C
Figure 6-10. Short-Circuit Output Current vs
Junction Temperature
100
2
VI = 5 V,
TA = 25°C
TA = 25°C
Load Ramp = 1A/10 ms
Current-Limit Response − µs
Threshold Trip Current − A
1.8
1.6
1.4
1.2
1
2.5
80
60
40
20
0
3
3.5
4
4.5
5
5.5
6
VI − Input Voltage − V
Figure 6-11. Threshold Trip Current vs Input
Voltage
8
150
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2.5
5
7.5
Peak Current − A
10
12.5
Figure 6-12. Current-Limit Response vs Peak
Current
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UVLO − Undervoltage Lockout − V
2.3
UVLO Rising
2.26
2.22
UVLO Falling
2.18
2.14
2.1
−50
0
50
100
TJ − Junction Temperature − °C
150
Figure 6-13. Undervoltage Lockout vs Junction Temperature
7 Parameter Measurement Information
OUT
RL
tf
tr
CL
VO(OUT)
90%
10%
90%
10%
TEST CIRCUIT
50%
VI(EN)
50%
t off
t on
VO(OUT)
50%
VI(EN)
90%
50%
t off
t on
VO(OUT)
10%
90%
10%
VOLTAGE WAVEFORMS
Figure 7-1. Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TPS20xxB-Q1 devices are current-limited, power-distribution switches providing 0.5-A continuous-load
current. These devices incorporate 105-mΩ N-channel MOSFET power switches for power-distribution systems
that require multiple power switches in a single package. A gate driver is provided by an internal charge pump
designed to minimize current surges during switching. The charge pump requires no external components and
allows operation supplies as low as 2.7 V.
8.2 Functional Block Diagrams
(See Note A)
CS
IN
OUT
Charge
Pump
EN
(See Note B)
Driver
Current
Limit
OC
UVLO
Thermal
Sense
GND
Deglitch
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A. CS = Current sense
B. EN = Active low ( EN) for TPS2041B-Q1; Active high (EN) for TPS2051B-Q1
Figure 8-1. Functional Block Diagram (TPS2041B-Q1 and TPS2051B-Q1)
10
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OC1
Thermal
Sense
GND
Deglitch
EN1
Driver
Current
Limit
Charge
Pump
(See Note A)
CS
OUT1
UVLO
(See Note A)
IN
OUT2
CS
Charge
Pump
Driver
Current
Limit
OC2
EN2
Thermal
Sense
Deglitch
Copyright © 2016, Texas Instruments Incorporated
A. CS = Current sense
Figure 8-2. Functional Block Diagram (TPS2042B-Q1)
8.3 Feature Description
8.3.1 Power Switch
The power switch is an N-channel MOSFET with a low ON-state resistance. Configured as a high-side switch,
the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies
a minimum current of 500 mA.
8.3.2 Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
little supply current.
8.3.3 Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage.
8.3.4 Enable ( ENx)
The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to
reduce the supply current. The supply current is reduced to less than 1 µA or 2 µA when a logic high is present
on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The
enable input is compatible with both TTL and CMOS logic levels.
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8.3.5 Enable (EN)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to
reduce the supply current. The supply current is reduced to less than 1 µA or 2 µA when a logic low is present
on EN. A logic high input on EN restores bias to the drive and control circuits and turns the switch on. The
enable input is compatible with both TTL and CMOS logic levels.
8.3.6 Overcurrent ( OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A
10‑ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature
shutdown occurs, the OCx is asserted instantaneously.
8.3.7 Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
8.3.8 Thermal Sense
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS204xB-Q1 and TPS205xB-Q1 implement a thermal sensing to monitor the
operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the
junction temperature rises due to excessive power dissipation. Once the die temperature rises to approximately
140°C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus
preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device
has cooled approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the
load fault or input power is removed. The OCx open-drain output is asserted (active low) when an
overtemperature shutdown or overcurrent occurs.
8.3.9 Undervoltage Lockout (UVLO)
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
8.4 Device Functional Modes
Table 8-1 lists OUT pin state as determined by the EN pin.
Table 8-1. OUT Pin State
EN
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
Low
IN
Open
Open
High
Open
IN
IN
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Universal Serial Bus (USB) Applications
The universal serial bus (USB) interface is a 12-Mbps, or 1.5-Mbps, multiplexed serial bus designed for low-tomedium bandwidth PC peripherals (for example, keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
•
•
•
•
•
Hosts and self-powered hubs (SPHs)
Bus-powered hubs (BPHs)
Low-power bus-powered functions
High-power bus-powered functions
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS204xB-Q1
and TPS205xB-Q1 can provide power-distribution solutions to many of these classes of devices.
9.2 Typical Applications
9.2.1 TPS2042B-Q1 Typical Application
TPS2042B-Q1
2
Power Supply
2.7 V to 5.5 V
IN
OUT1
0.1 µF
8
3
Load
0.1 µF
22 µF
0.1 µF
22 µF
OC1
EN1
OUT2
5
OC2
4
7
6
Load
EN2
GND
1
Copyright © 2016, Texas Instruments Incorporated
Figure 9-1. Typical Application Schematic Using the TPS2042B-Q1
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9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
PARAMETER
VALUE
Input voltage
5V
Output1 voltage
5V
Output2 voltage
5V
Output1 current
0.5 A
Output2 current
0.5 A
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 9-7 through Figure 9-10). The TPS20xxB-Q1
senses the short and immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 6-7 through Figure 6-8). The TPS20xxB-Q1 is capable of delivering current up to the
current-limit threshold without damaging the device. Once the threshold has been reached, the device switches
into its constant-current mode.
9.2.1.2.2 OC Response
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS20xxB-Q1 is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch
eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch
is turned off due to an overtemperature shutdown.
V+
TPS2042B-Q1
GND
R pullup
OC1
IN
OUT1
EN1
OUT2
EN2
OC2
Copyright © 2016, Texas Instruments Incorporated
Figure 9-2. Typical Circuit for the OC Pin (TPS2042B-Q1)
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9.2.1.3 Application Curves
RL = 10 Ω,
CL = 1 µF
TA = 25°C
VI(EN)
VI(EN)
5 V/div
VI(EN)
VI(EN)
5 V/div
RL = 10 Ω,
CL = 1 µF
TA = 25°C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 µs/div
t − Time − 500 µs/div
Figure 9-3. Turnon Delay and Rise Time With 1-µF
Load
RL = 10 Ω,
CL = 100 µF
TA = 25°C
VI(EN)
VI(EN)
5 V/div
Figure 9-4. Turnoff Delay and Fall Time With 1-µF
Load
VI(EN)
VI(EN)
5 V/div
RL = 10 Ω,
CL = 100 µF
TA = 25°C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 µs/div
t − Time − 500 µs/div
Figure 9-5. Turnon Delay and Rise Time With 100µF Load
Figure 9-6. Turnoff Delay and Fall Time With 100-µF
Load
VI = 5 V,
RL = 10 Ω,
TA = 25°C
VI(EN)
VI(EN)
5 V/div
VI(EN)
VI(EN)
5 V/div
220 µF
470 µF
IO(OUT)
500 mA/div
IO(OUT)
500 mA/div
100 µF
t − Time − 500 µs/div
Figure 9-7. Short-Circuit Current, Device Enabled
Into Short
t − Time − 500 µs/div
Figure 9-8. Inrush Current With Different Load
Capacitance
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VO(OC)
2 V/div
VO(OC)
2 V/div
IO(OUT)
500 mA/div
IO(OUT)
500 mA/div
t − Time − 2 ms/div
t − Time − 2 ms/div
Figure 9-10. 2-Ω Load Connected to Enabled
Device
Figure 9-9. 3-Ω Load Connected to Enabled Device
9.2.2 Hosts and Self-Powered Hubs and Bus-Powered Hubs
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figure 9-11). This power supply must provide from 5.25 V to 4.75 V to the board side of
the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have
current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop
PCs, monitors, printers, and stand-alone hubs.
Power Supply
3.3 V
Downstream
USB Ports
5V
TPS2051B-Q1
2, 3
IN
D+
D−
6, 7, 8
0.1 µF
V B US
OUT
0.1 µF
5
USB
Control
4
120 µF
GND
OC
EN
GND
1
Copyright © 2016, Texas Instruments Incorporated
Figure 9-11. Typical One-Port USB Host or Self-Powered Hub
9.2.2.1 Design Requirements
9.2.2.1.1 USB Power-Distribution Requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
•
•
•
16
Hosts and self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
Bus-powered hubs must:
– Enable and disable power to downstream ports
– Power up at < 100 mA
– Limit inrush current (< 44 Ω and 10 µF)
Functions must:
– Limit inrush currents
– Power up at < 100 mA
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The feature set of the TPS204xB-Q1 and TPS205xB-Q1 allows them to meet each of these requirements. The
integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level
enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as
the input ports for bus-powered functions (see Figure 9-12 and Figure 9-13).
TUSB2046
Hub Controller
Upstream
Port
SN75240
BUSPWR
A C
B D
GANGED
D+
D−
DP0
DP1
DM0
DM1
Tie to TPS2051B-Q1 EN Input
D+
A C
B D
GND
OC
5V
DM2
5-V Power
Supply
EN
A C
B D
TPS76333-Q1
5V
SN75240
D+
D−
Ferrite Beads
GND
DP4
0.1 µF
4.7 µF
GND
DM3
1 µF
IN
3.3 V
4.7 µF
VCC
D−
33 µF
(see Note A)
DP3
OUT
IN
Ferrite Beads
SN75240
DP2
TPS2051B-Q1
Downstream
Ports
DM4
5V
TPS2051B-Q1
GND
GND
PWRON1
EN
OVRCUR1
OC
IN
0.1 µF
33 µF
(see Note A)
OUT
D+
TPS2051B-Q1
48-MHz
Crystal
XTAL1
Tuning
Circuit
XTAL2
PWRON2
OVRCUR2
EN
D−
IN
Ferrite Beads
0.1 µF
OC
GND
OUT
OCSOFF
5V
TPS2051B-Q1
PWRON3
EN
OVRCUR3
OC
IN
0.1 µF
33 µF
(see Note A)
OUT
GND
D+
TPS2051B-Q1
PWRON4
EN
OVRCUR4
OC
Ferrite Beads
IN
D−
GND
0.1 µF
OUT
5V
33 µF
(see Note A)
Copyright © 2016, Texas Instruments Incorporated
A. USB rev 1.1 requires 120 µF per hub.
Figure 9-12. Hybrid Self-Powered or Bus-Powered Hub Implementation (TPS2051B-Q1)
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TUSB2046
Hub Controller
Upstream
Port
SN75240
BUSPWR
A C
B D
GANGED
D+
D−
DP0
DP1
DM0
DM1
Tie to TPS2051B-Q1 EN Input
D+
5V
IN
5V
DM2
5-V Power
Supply
EN
33 µF
(see Note A)
DP3
OUT
DM3
D+
A C
B D
TPS76333-q1
D−
Ferrite Beads
SN75240
GND
DP4
IN
0.1 µF
4.7 µF
3.3 V
4.7 µF
VCC
DM4
5V
TPS2042B-Q1
GND
GND
48-MHz
Crystal
XTAL1
PWRON1
EN1 OUT1
OVRCUR1
OC1 OUT2
PWRON2
EN2
OVRCUR2
OC2
33 µF
(see Note A)
D+
IN
D−
0.1 µF
Tuning
Circuit
D−
GND
SN75240
DP2
OC
Ferrite Beads
A C
B D
GND
TPS2051B-Q1
Downstream
Ports
XTAL2
OCSOFF
GND
Ferrite Beads
GND
TPS2042B-Q1
PWRON3
EN1 OUT1
OVRCUR3
OC1 OUT2
PWRON4
EN2
OVRCUR4
OC2
5V
33 µF
(see Note A)
IN
D+
0.1 µF
Ferrite Beads
D−
GND
5V
33 µF
(see Note A)
Copyright © 2016, Texas Instruments Incorporated
A. USB rev 1.1 requires 120 µF per hub.
Figure 9-13. Hybrid Self-Powered or Bus-Powered Hub Implementation (TPS2042B-Q1)
9.2.2.2 Detailed Design Procedure
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are
required to power up with less than one unit load. The BPH usually has one embedded function, and power is
always available to the controller of the hub. If the embedded function and hub require more than 100 mA on
power up, the power to the embedded function may need to be kept off until enumeration is completed. This can
be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
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9.2.2.2.1 Low-Power Bus-Powered and High-Power Bus-Powered Functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 µF at power up, the device must implement inrush current limiting (see Figure 9-14).
Power Supply
3.3 V
D+
D−
V B US
TPS2042B-Q1
2
10 µF
IN
7
0.1 µF
8
3
USB
Control
0.1 µF
10 µF
Internal
Function
0.1 µF
10 µF
Internal
Function
OUT1
GND
OC1
EN1
5
OC2
4
6
EN2
OUT2
GND
1
Copyright © 2016, Texas Instruments Incorporated
Figure 9-14. High-Power Bus-Powered Function (TPS2042B-Q1)
9.2.3 Generic Hot-Plug Applications
In many applications, it may be necessary to remove modules or PC boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise and fall times of the TPS204xB-Q1 and TPS205xB-Q1, these
devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO
feature of the TPS204xB-Q1 and TPS205xB-Q1 also ensures that the switch is off after the card has been
removed, and that the switch is off during the next insertion. The UVLO feature ensures a soft start with a
controlled rise time for every insertion of the card or module.
PC Board
TPS2042B-Q1
Power
Supply
GND
2.7 V to 5.5 V
1000 µF
Optimum
0.1 µF
Block of
Circuitry
OC1
IN
OUT1
EN1
OUT2
EN2
OC2
Block of
Circuitry
Overcurrent Response
Copyright © 2016, Texas Instruments Incorporated
Figure 9-15. Example Hot-Plug Implementation (TPS2042B-Q1)
By placing the TPS204xB-Q1 or TPS205xB-Q1 between the VCC input and the rest of the circuitry, the input
power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms,
providing a slow voltage ramp at the output of the device. This implementation controls system surge currents
and provides a hot-plugging mechanism for any device.
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9.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 9-2 as the input parameters.
Table 9-2. Design Parameters
PARAMETER
VALUE
Input voltage
5V
Output1 voltage
5V
Output2 voltage
5V
Output1 current
0.5 A
Output2 current
0.5 A
9.2.3.2 Detailed Design Procedure
To begin the design process a few parameters must be decided upon. The designer must know the following:
• Normal input operation voltage
• Current limit
Input and output capacitance improves the performance of the device; the actual capacitance must be optimized
for the particular application. For all applications, TI recommends a 0.1 µF or greater ceramic bypass capacitor
between IN and GND, as close to the device as possible for local noise decoupling. This precaution reduces
ringing on the input due to power-supply transients. Additional input capacitance may be required on the input to
reduce voltage undershoot from exceeding the UVLO of other load share one power rail with TPS2042B‑Q1
device or overshoot from exceeding the absolute-maximum voltage of the device during heavy transient
conditions. This is especially important during bench testing when long, inductive cables are used to connect the
evaluation board to the bench power supply. Output capacitance is not required, but TI recommends placing a
high-value electrolytic capacitor on the output pin when large transient currents are expected on the output to
reduce the undershoot, which is caused by the inductance of the output power bus just after a short has
occurred and the TPS2042B-Q1 device has abruptly reduced OUT current. Energy stored in the inductance
drives the OUT voltage down and potentially negative as it discharges.
10 Power Supply Recommendations
TI recommends a 0.01-µF to 0.1-µF ceramic bypass capacitor close to the device between IN and GND. TI
recommends placing a high-value electrolytic capacitor on the output pins when the output load is heavy. This
precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients.
See Figure 9-1.
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11 Layout
11.1 Layout Guidelines
•
•
Place the 100-nF bypass capacitor near the IN and GND pins and make the connections using a lowinductance trace.
TI recommends placing a high-value electrolytic capacitor and a 100-nF bypass capacitor on the output pin
when large transient currents are expected on the output.
11.2 Layout Example
GROUND PLANE
TPS2041B-Q1
OUT
IN
VIA TO
GROUND
PLANE
GND
OC
EN
Figure 11-1. Layout Recommendation
11.3 Thermal Considerations
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistances of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the rDS(ON) of the Nchannel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest
operating ambient temperature of interest and read rDS(ON) from Figure 6-9. Using this value, the power
dissipation per switch can be calculated by Equation 1:
PD = rDS(ON) × I2
(1)
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
Finally, calculate the junction temperature with Equation 2:
TJ = PD × RθJA + TA
(2)
where
•
•
•
TA = Ambient temperature °C
RθJA = Thermal resistance
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS2041B-Q1
Click here
Click here
Click here
Click here
Click here
TPS2042B-Q1
Click here
Click here
Click here
Click here
Click here
TPS2051B-Q1
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS2041BQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PLIQ
TPS2042BQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2042B
TPS2051BQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2051BQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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