TPS2046BDG4

DBV-5 D-8 TPS2045B, TPS2055B TPS2046B, TPS2047B D-16 www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES FEATURES APPLICATIONS • • • • • • • • • • • • 1 • • • • 70-mΩ High-Side MOSFET 250-mA Continuous Current Thermal and Short-Circuit Protection Accurate Current Limit (0.3 A min, 0.7 A max) Operating Range: 2.7 V to 5.5 V 0.6-ms Typical Rise Time Undervoltage Lockout Deglitched Fault Report (OC) No OC Glitch During Power Up Maximum Standby Supply Current: 1-μA (Single and Dual) or 2-μA (Triple) Bidirectional Switch Ambient Temperature Range: –40°C to 85°C ESD Protection UL Pending Heavy Capacitive Loads Short-Circuit Protections TPS2045B/TPS2055B DBV PACKAGE (TOP VIEW) OUT IN GND OC EN TPS2047B D PACKAGE (TOP VIEW) TPS2046B D PACKAGE (TOP VIEW) † GND IN EN1 EN2 OC1 OUT1 OUT2 OC2 TPS2045B/TPS2055B D PACKAGE (TOP VIEW) GND IN IN † EN OUT OUT OUT GND OC1 IN1 OUT1 EN1 EN2 GND OUT2 IN2 EN3 NC OC2 OC3 OUT3 NC NC NC - No Connection OC † All enable inputs are active high (EN) for the TPS2055B. DESCRIPTION The TPS204xB/TPS2055B power-distribution switches are intended for applications where heavy capacitive loads and short circuits are likely to be encountered. These devices incorporate 70-mΩ N-channel MOSFET power switches for power-distribution systems that require multiple power switches in a single package. Each switch is controlled by a logic-enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains off until valid input voltage is present. This power-distribution switch is designed to set current limit at 0.5 A typically. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2007, Texas Instruments Incorporated TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS TA –40°C to 85°C ENABLE RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT (A) TYPICAL SHORT-CIRCUIT CURRENT LIMIT AT 25°C (A) NUMBER OF SWITCHES Active low 0.25 0.5 Single Active high 0.25 0.5 Single Active low (1) 0.25 0.5 PACKAGED (1) DEVICES SOIC (D) TPS4045BD SOT-23 (DBV) TPS4045BDBV SOIC (D) TPS4055BD SOT-23 (DBV) TPS4055BDBV Dual SOIC (D) TPS2046BD Triple SOIC (D) TPS2047BD The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2046BDR) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT (2) VI(IN), VI(INx) Input voltage range VO(OUTx) Output voltage range –0.3 V to 6 V VI(/ENx) Input voltage range VI(/OCx) Voltage range IO(OUTx) Continuous output current (2) –0.3 V to 6 V –0.3 V to 6 V –0.3 V to 6 V Internally limited Continuous total power dissipation See Dissipation Rating Table TJ Operating virtual junction temperature range Tstg Storage temperature range ESD (1) (2) Electrostatic discharge protection –40°C to 125°C –65°C to 150°C Human body model MIL-STD-883C 2 kV Charge device model (CDM) 500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. DISSIPATING RATING TABLE 2 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 234.32 mW D-8 585.82 mW 5.8582 mW/°C 322.2 mW D-16 898.47 mW 8.9847 mW/°C 494.15 mW 359.38 mW DBV-5 308.6419 mW 3.086419 mW/°C 169.753 mW 123.4567 mW Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VI(IN), VI(INx) Input voltage 2.7 5.5 VI(/ENx), VI(ENx) Input voltage 0 5.5 V V IO(OUT), IO(OUTx) Continuous output current 0 250 mA TJ Operating virtual junction temperature -40 125 °C ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.25 A, VI(ENx) = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT POWER SWITCH rDS(on) tr (2) tf Static drain-source on-state resistance, 5-V operation and 3.3-V operation VI(IN) = 5 V or 3.3 V, IO = 0.25 A –40°C ≤ TJ≤ 125°C 70 135 mΩ Static drain-source on-state resistance, 2.7-V operation (2) VI(IN) = 2.7 V, –40°C≤ TJ≤ 125°C 75 150 mΩ 0.6 1.5 VI(IN) = 5.5 V Rise time, output (2) IO = 0.25 A VI(IN) = 2.7 V VI(IN) = 5.5 V Fall time, output CL = 1 μF, RL = 20 Ω TJ = 25°C VI(IN) = 2.7 V 0.4 1 0.05 0.5 0.05 0.5 ms ENABLE INPUT ENx VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V VIL Low-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V II 2 0.8 Input current VI(/ENx) = 0 V or 5.5 V (2) Turnon time CL = 100 μF, RL = 20 Ω 3 toff (2) Turnoff time CL = 100 μF, RL = 20 Ω 10 ton -0.5 0.5 V μA ms CURRENT LIMIT IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND, device enabled into short-circuit 0.3 0.5 0.7 A SUPPLY CURRENT (TPS2045B, TPS2055B) Supply current, low-level output No load on OUT, VI(/ENx) = 5.5 V or VI(/ENx) = 0 V TJ = 25°C 0.5 1 –40°C ≤ TJ ≤ 125°C 0.5 5 Supply current, high-level output No load on OUT, VI(/ENx) = 0 V or VI(/ENx) = 5.5 V TJ = 25°C 43 60 –40°C ≤ TJ ≤ 125°C 43 70 Leakage current OUT connected to ground, VI(/ENx) = 5.5 V, or VI(ENx) = 0 V –40°C ≤ TJ ≤ 125°C 1 μA TJ = 25°C 0 μA TJ = 25°C 0.5 1 –40°C ≤ TJ ≤ 125°C 0.5 5 TJ = 25°C 50 70 -40°C ≤ TJ ≤ 125°C 50 90 1 μA 0.2 μA Reverse leakage current VI(OUTx) = 5.5 V, IN = ground (2) μA μA SUPPLY CURRENT (TPS2046B) Supply current, low-level output No load on OUT, VI(/ENx) = 5.5 V Supply current, high-level output No load on OUT, VI(/ENx) = 0 V Leakage current OUT connected to ground, VI(ENx) = 5.5 V -40°C ≤ TJ ≤ 125°C Reverse leakage current VI(OUTx) = 5.5 V, IN = ground (2) TJ = 25°C (1) (2) μA μA Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Not tested in production, specified by design. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B 3 TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.25 A, VI(ENx) = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT SUPPLY CURRENT (TPS2047B) TJ = 25°C 0.5 2 –40°C ≤ TJ ≤ 125°C 0.5 10 TJ = 25°C 65 90 –40°C ≤ TJ ≤ 125°C 65 110 OUT connected to ground, VI(/ENx) = 5.5 V –40°C≤ TJ≤ 125°C 1 μA VI(OUTx) = 5.5 V, INx = ground (3) TJ = 25°C 0.2 μA Supply current, low-level output No load on OUT, VI(/ENx) = 5.5 V Supply current, high-level output No load on OUT, VI(/ENx) = 0 V Leakage current Reverse leakage current μA μA UNDERVOLTAGE LOCKOUT Low-level input voltage, IN, INx 2 Hysteresis, IN, INx TJ = 25°C 2.5 75 V mV OVERCURRENT OC and OCx Output low voltage, VOL(/OCx) Off-state current IO(/OCx) = 5 mA (3) 0.4 VO(/OCx) = 5 V or 3.3 V OC deglitch (3) OCx assertion or deassertion 4 8 V 1 μA 15 ms THERMAL SHUTDOWN (4) Thermal shutdown threshold (3) 135 Recovery from thermal shutdown (3) 125 Hysteresis (3) (3) (4) 4 °C °C 10 °C Not tested in production, specified by design. The thermal shutdown only reacts under overcurrent conditions. Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 DEVICE INFORMATION Terminal Functions (TPS2045B and TPS2055B) TERMINAL D PACKAGE NAME DBV PACKAGE I/O DESCRIPTION TPS2045B TPS2055B TPS2045B EN 4 - 4 - I Enable input, logic low turns on power switch EN - 4 - 4 I Enable input, logic high turns on power switch GND 1 1 2 2 IN 2, 3 2, 3 5 5 I Input voltage OC 5 5 3 3 O Overcurrent open-drain output, active-low 6, 7, 8 6, 7, 8 1 1 O Power-switch output OUT TPS2055B Ground FUNCTIONAL BLOCK DIAGRAM (TPS2045B and TPS2055B) (See Note A) CS IN OUT Charge Pump EN (See Note B) Driver Current Limit OC UVLO Thermal Sense GND A. Current sense B. Active low (EN) for TPS2045B. Active high (EN) for TPS2055B. Copyright © 2004–2007, Texas Instruments Incorporated Deglitch Submit Documentation Feedback Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B 5 TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 Terminal Functions (TPS2046B) TERMINAL NAME NUMBER I/O DESCRIPTION EN1 3 I Enable input, logic low turns on power switch IN-OUT1 EN2 4 I Enable input, logic low turns on power switch IN-OUT2 GND 1 IN 2 I Input voltage OC1 8 O Overcurrent, open-drain output, active low, IN-OUT1 OC2 5 O Overcurrent, open-drain output, active low, IN-OUT2 OUT1 7 O Power-switch output, IN-OUT1 OUT2 6 O Power-switch output, IN-OUT2 Ground FUNCTIONAL BLOCK DIAGRAM (TPS2046B) OC1 Thermal Sense GND Deglitch EN1 Driver Current Limit Charge Pump (See Note A) CS OUT1 UVLO (See Note A) IN CS OUT2 Charge Pump Driver Current Limit OC2 EN2 Thermal Sense A. 6 Deglitch Current sense Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 Terminal Functions (TPS2047B) TERMINAL NAME NUMBER I/O DESCRIPTION EN1 3 I Enable input, logic low turns on power switch IN1-OUT1 EN2 4 I Enable input, logic low turns on power switch IN1-OUT2 EN3 7 I Enable input, logic low turns on power switch IN2-OUT3 GND 1, 5 Ground IN1 2 I Input voltage for OUT1 and OUT2 IN2 6 I Input voltage for OUT3 NC 8, 9, 10 No connection OC1 16 O Overcurrent, open-drain output, active low, IN1-OUT1 OC2 13 O Overcurrent, open-drain output, active low, IN1-OUT2 OC3 12 O Overcurrent, open-drain output, active low, IN2-OUT3 OUT1 15 O Power-switch output, IN1-OUT1 OUT2 14 O Power-switch output, IN1-OUT2 OUT3 11 O Power-switch output, IN2-OUT3 FUNCTIONAL BLOCK DIAGRAM (TPS2047B) OC1 Thermal Sense GND Deglitch EN1 Driver Current Limit (See Note A) CS OUT1 UVLO (See Note A) CS IN1 Driver OUT2 Current Limit OC2 EN2 Thermal Sense VCC Selector Deglitch Charge Pump (See Note A) CS IN2 EN3 Driver OUT3 Current Limit OC3 UVLO Thermal Sense GND A. Deglitch Current sense Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B 7 TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION OUT RL tf tr CL VO(OUT) 90% 10% 90% 10% TEST CIRCUIT 50% VI(EN) 50% toff ton VO(OUT) 50% VI(EN) 90% 50% toff ton 90% VO(OUT) 10% 10% VOLTAGE WAVEFORMS Figure 1. Test Circuit and Voltage Waveforms RL = 20 W, CL = 1 mF TA = 255C VI(EN) VI(EN) 5 V/div VI(EN) 5 V/div RL = 20 W, CL = 1 mF TA = 255C VO(OUT) 2 V/div VO(OUT) 2 V/div t - Time - 500 ms/div Figure 2. Turnon Delay and Rise Time With 1-μF Load 8 Submit Documentation Feedback t - Time - 500 ms/div Figure 3. Turnoff Delay and Fall Time With 1-μF Load Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) VI(EN) 5 V/div VI(EN) 5 V/div VO(OUT) 2 V/div RL = 20 W, CL = 100 mF TA = 255C RL = 20 W, CL = 100 mF TA = 255C VO(OUT) 2 V/div t - Time - 1 ms t - Time - 1 ms Figure 4. Turnon Delay and Rise Time With 100-μF Load Figure 5. Turnoff Delay and Fall Time With 100-μF Load VI = 5 V, RL = 20 W, TA = 255C VI(EN) 5 V/div VI(EN) 5 V/div 150 mF 300 mF IO(OUT) 250 mA/div IO(OUT) 250 mA/div 68 mF t - Time - 500 ms/div Figure 6. Short-Circuit Current, Device Enabled Into Short Copyright © 2004–2007, Texas Instruments Incorporated t - Time - 2 ms Figure 7. Inrush Current With Different Load Capacitance Submit Documentation Feedback Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B 9 TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) VO(OC) 2 V/div VO(OC) 2 V/div IO(OUT) 250 mA/div IO(OUT) 250 mA/div t - Time - 2 ms/div t - Time - 2 ms/div Figure 8. 4-Ω Load Connected to Enabled Device Figure 9. 3-Ω Load Connected to Enabled Device TYPICAL CHARACTERISTICS TURNON TIME vs INPUT VOLTAGE TURNOFF TIME vs INPUT VOLTAGE 1.6 6 CL = 100 mF, RL = 20 W, TA = 255C 1.4 5 Turnoff Time - ms Turnon Time - ms 1.2 1 0.8 0.6 CL = 100 mF, RL = 20 W, TA = 255C 4 3 2 0.4 1 0.2 0 2 3 4 VI - Input Voltage - V Figure 10. 10 Submit Documentation Feedback 5 6 0 2 3 4 5 6 VI - Input Voltage - V Figure 11. Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) RISE TIME vs INPUT VOLTAGE FALL TIME vs INPUT VOLTAGE 160 500 CL = 1 mF, RL = 20 W, TA = 255C 450 400 CL = 1 mF, RL = 20 W, TA = 255C 140 Fall Time - µ s Rise Time - µ s 120 350 300 250 200 100 80 60 150 40 100 20 50 0 2 3 4 VI - Input Voltage - V 5 0 6 2 Figure 13. TPS2046B SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE TPS2047B SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE 6 90 I I (IN) − Supply Current, Output Enabled − µ A I I (IN) − Supply Current, Output Enabled − µ A 4 5 VI - Input Voltage - V Figure 12. 70 VI = 5.5 V 60 50 VI = 5 V VI = 3.3 V 40 30 VI = 2.7 V 20 10 0 3 −50 0 50 100 TJ − Junction Temperature − 5C Figure 14. Copyright © 2004–2007, Texas Instruments Incorporated 150 80 VI = 5.5 V 70 VI = 5 V 60 VI = 3.3 V 50 40 VI = 2.7 V 30 20 10 0 −50 0 50 100 TJ − Junction Temperature − 5C 150 Figure 15. Submit Documentation Feedback Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B 11 TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) 0.5 mΩ r DS(on) - Static Drain-Source On-State Resistance - I I (IN) − Supply Current, Output Disabled − µ A 0.5 VI = 5.5 V 0.45 VI = 5 V 0.4 0.35 0.3 VI = 3.3 V VI = 2.7 V 0.25 0.2 0.15 0.1 0.05 0 −50 12 TPS2047B SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE 0 50 100 TJ − Junction Temperature − 5C 0.45 VI = 5.5 V VI = 5 V 0.4 0.35 0.3 VI = 3.3 V VI = 2.7 V 0.25 0.2 0.15 0.1 0.05 0 −50 150 0 50 100 TJ − Junction Temperature − 5C Figure 16. Figure 17. STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 150 0.54 120 IO = 0.25 A 80 VI = 3.3 V 60 VI = 5 V 40 20 0 -50 VI = 2.7 V 0.53 VI = 2.7 V 100 I OS - Short-Circuit Output Current - A I I (IN) − Supply Current, Output Disabled − µ A TPS2046B SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE VI = 3.3 V 0.52 0.51 0.5 0.49 VI = 5 V 0.48 VI = 5.5 V 0.47 0.46 0.45 -50 TJ - Junction Temperature - 5C 0 50 100 TJ - Junction Temperature - 5C Figure 18. Figure 19. 0 50 Submit Documentation Feedback 100 150 150 Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) THRESHOLD TRIP CURRENT vs INPUT VOLTAGE UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 1.5 2.3 UVLO − Undervoltage Lockout − V TA = 255C Load Ramp = 1A/10 ms Threshold Trip Current - A 1.3 1.1 0.9 0.7 0.5 2.5 3 3.5 4 4.5 5 5.5 6 UVLO Rising 2.26 2.22 UVLO Falling 2.18 2.14 2.1 −50 0 50 100 TJ − Junction Temperature − 5C Figure 21. VI - Input Voltage - V Figure 20. 150 CURRENT-LIMIT RESPONSE vs PEAK CURRENT 200 Current-Limit Response - µ s VI = 5 V, TA = 255C 150 100 50 0 0 Copyright © 2004–2007, Texas Instruments Incorporated 1 2 3 Peak Current - A Figure 22. 4 5 Submit Documentation Feedback Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B 13 TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 APPLICATION INFORMATION POWER-SUPPLY CONSIDERATIONS TPS2046B 2 Power Supply 2.7 V to 5.5 V IN OUT1 0.1 µF 8 3 5 4 7 Load 0.1 µF 22 µF 0.1 µF 22 µF OC1 EN1 OUT2 OC2 6 Load EN2 GND 1 Figure 23. Typical Application (Example, TPS2046B) A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients. OVERCURRENT A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 6). The TPS204xB/TPS2055B senses the short, and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded. The TPS204xB/TPS2055B is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC RESPONSE The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit. The TPS204xB/TPS2055B is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned off due to an overtemperature shutdown. 14 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 V+ TPS2046B GND Rpullup OC1 IN OUT1 EN1 OUT2 EN2 OC2 Figure 24. Typical Circuit for the OC Pin (Example, TPS2046B) POWER DISSIPATION AND JUNCTION TEMPERATURE The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power dissipation per switch can be calculated by: • PD = rDS(on) × I2 Multiply this number by the number of switches being used. This step renders the total power dissipation from the N-channel MOSFETs. Finally, calculate the junction temperature: • TJ = PD × RθJA + TA Where: • TA= Ambient temperature °C • RθJA = Thermal resistance • PD = Total power dissipation based on number of switches being used. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. THERMAL PROTECTION Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS204xB/TPS2055B implements a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs. UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B 15 TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 UNIVERSAL SERIAL BUS (USB) APPLICATIONS The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: • Hosts/self-powered hubs (SPH) • Bus-powered hubs (BPH) • Low-power, bus-powered functions • High-power, bus-powered functions • Self-powered functions Self-powered and bus-powered hubs distribute data and power to downstream functions. TPS204xB/TPS2055B can provide-power distribution solutions to many of these classes of devices. The HOST/SELF-POWERED AND BUS-POWERED HUBS Hosts and self-powered hubs have a local power supply that powers the embedded functions and the downstream ports. This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port. LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 μF at power up, the device must implement inrush current limiting (see Figure 25). 16 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B TPS2045B, TPS2055B TPS2046B, TPS2047B www.ti.com SLVS532C – JULY 2004 – REVISED OCTOBER 2007 Power Supply 3.3 V D+ DVBUS TPS2046B 2 10 µF 0.1 µF IN OUT1 GND 8 3 USB Control 5 4 7 0.1 µF 10 µF Internal Function 0.1 µF 10 µF Internal Function OC1 EN1 OC2 EN2 OUT2 GND 1 6 Figure 25. High-Power Bus-Powered Function (Example, TPS2046B) USB POWER-DISTRIBUTION REQUIREMENTS USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented. • Hosts/self-powered hubs must: – Current-limit downstream ports – Report overcurrent conditions on USB VBUS • Bus-powered hubs must: – Enable/disable power to downstream ports – Power up at