TPS2049DR

TPS2049 www.ti.com......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 SINGLE-CHANNEL 100 mA POWER SWITCH FEATURES 1 • • • • • • • • • 100-mA Continuous Current 600-mΩ High-Side MOSFET Thermal and Short-Circuit Protection Operating Range: 2.7 V to 5.5 V 0.6-ms Typical Rise Time Undervoltage Lockout Deglitched Fault Report (OC) 43 µA Quiescent Supply Current 1-µA Maximum Standby Supply Current • • • SOIC-8 Package Ambient Temperature Range: –40°C to 85°C 2 µS Response Time to Short Circuit GND IN IN EN OUT OUT OUT OC DESCRIPTION The TPS2049 power-distribution switch is intended for applications where heavy capacitive loads and short circuits are likely to be encountered. This device incorporates a 600-mΩ N-channel MOSFET power switch for power-distribution systems that require only one power distribution path. The switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7V. When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is present. This power-distribution switch is designed to set current limit at 150mA typically. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated TPS2049 SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007......................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTION AND ORDERING INFORMATION (1) TA ENABLE RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT (mA) TYPICAL SHORT-CIRCUIT CURRENT LIMIT AT 25°C (mA) NUMBER OF SWITCHES SOIC (D) –40°C to 85°C Active low 100 150 Single TPS2049D (2) (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2042BDR) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) VI(IN) Input voltage range (2) (2) VALUE UNIT –0.3 to 6 V VO(OUT) Output voltage range -0.3 to 6 V VI(EN) Input voltage range –0.3 to 6 V VI(OC) Voltage range –0.3 to 6 V IO(OUT) Continuous output current Internally limited Continuous total power dissipation See Dissipation Rating Table TJ Operating virtual junction temperature range –40 to 125 °C Tstg Storage temperature range –65 to 150 °C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds Electrostatic discharge (ESD) protection (1) (2) Human body model MIL-STD-883C Charge device model (CDM) 260 °C 2 kV 500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. DISSIPATING RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D-8 585.82 mW 5.8582 mW/C 322.20 mW 234.32 mW RECOMMENDED OPERATING CONDITIONS MIN MAX VI(IN) Input voltage 2.7 5.5 V VI(EN) Input voltage 0 5.5 V IO(OUT) Continuous output current 0 100 mA TJ Operating virtual junction temperature –40 125 °C 2 Submit Documentation Feedback UNIT Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2049 TPS2049 www.ti.com......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 90 mA, VI(EN) = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT POWER SWITCH rDS(on) Static drain-source on-state resistance, 5-V operation and 2.7-V operation VI(IN) = 2.7 V or 5.5 V, IO = 90 A, –40°C < TJ < 125°C 400 650 mΩ tr Rise time, output VI(IN) = 2.7 V CL = 1 F, RL = 50 Ω, TJ = 25°C 0.1 0.4 ms tf Fall time, output VI(IN) = 2.7 V CL = 1 F, RL = 50 Ω, TJ = 25°C 0.3 ms 0.03 ENABLE INPUT EN VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V VIL Low-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V II Input current VI(EN) = 0 V or VI(EN) = VI(IN) ton Turnon time toff Turnoff time 2 V 0.8 V 0.5 µA CL = 1 µF, RL = 50 Ω, TJ = 25°C 1 ms CL = 1 F, RL = 50 Ω, TJ = 25°C 1 ms 200 mA 325 mA –0.5 CURRENT LIMIT IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND, Device enabled into short-circuit, 10°C < TJ < 40°C IOC_trip Overcurrent trip threshold 10°C < TJ < 40°C, 100 A/sec current rate increase 100 Short-circuit response time 150 µs 2 SUPPLY CURRENT TJ = 25°C 0.5 1 –40C ≤ TJ ≤ 125°C 0.5 5 TJ = 25°C 43 60 –40C ≤ TJ ≤ 125°C 43 70 VI(EN) = 5.5 V, –40C ≤ TJ ≤ 125°C 1 µA VI(OUT) = 5.5 V, VI(EN) = 0 V TJ = 25°C 0 µA Supply current, low-level output No load on OUT VI(EN) = 5.5 V Supply current, high-level output No load on OUT VI(EN) = 0 V Leakage current OUT connected to ground Reverse leakage current IN = ground µA µA UNDERVOLTAGE LOCKOUT IN Low-level input voltage IN Hysteresis 2 TJ = 25C 2.5 75 V mV OVERCURRENT OC VOL(OC) Output low voltage IO(OC) = 5 mA 0.4 Off-state current VO(OC) = 5 V or 3.3 V OC deglitch OC assertion or de-assertion 4 8 V 1 µA 15 ms THERMAL SHUTDOWN (2) Thermal shutdown threshold 135 Recovery from thermal shutdown 125 Hysteresis (1) (2) °C °C 10 °C Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. The thermal shutdown only reacts under overcurrent conditions. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2049 3 TPS2049 SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007......................................................................................................................................... www.ti.com FUNCTIONAL BLOCK DIAGRAM TERMINAL FUNCTIONS TERMINAL NAME EN1 GND NO. I/O DESCRIPTION 4 I Enable input, logic low turns on power switch 1 I Ground IN 2, 3 I Input voltage OC 5 O Overcurrent, report, active-low, open-drain output 6, 7, 8 O Power-switch output OUT 4 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2049 TPS2049 www.ti.com......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION OUT RL tf tr CL VO(OUT) 90% 10% 90% 10% TEST CIRCUIT 50% VI(EN) 50% toff ton VO(OUT) 50% VI(EN) 90% 50% toff ton 90% VO(OUT) 10% 10% VOLTAGE WAVEFORMS Figure 1. Test Circuit and Voltage Waveforms RL = 50 W VI(EN) 2 V/div CL = 1 m F VO(OUT) 2 V/div VI(EN) 2 V/div RL = 50 W CL = 1 m F VO(OUT1) 2 V/div t - Time - 100 ms/div t - Time - 100 ms/div Figure 2. Turnon Delay and Rise Time With 1-µF Load Figure 3. Turnoff Delay and Fall Time With 1-µF Load Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2049 5 TPS2049 SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007......................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VI(EN) 5 V/div Enable Into a Short Watching OC Flag’s Delay VO(OUT1) 5 V/div Hotshort 5 Ω on Output Watch Current Limit Response Time. OC 200 ms/div IO(OUT1) 200 mA/div VI(OUT) 5 V/div t - Time - 2 ms/div t - Time - 2 ms/div Figure 4. Device Enabled Into a Short 6 Figure 5. 5-Ω Load Connected to Enabled Device Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2049 TPS2049 www.ti.com......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 APPLICATION INFORMATION 2,3 6,7,8 5 4 Figure 6. Typical Application POWER-SUPPLY CONSIDERATIONS A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients. OVERCURRENT A sense FET is employed to check for overcurrent conditions. Unlike current–sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 6). The TPS2049 senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, very high currents may flow for a short period of time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold) the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded. The TPS2049 is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC RESPONSE The OC open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OC occurs due to the 10-ms deglitch circuit. The TPS2049 is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OC is not deglitched when the switch is turned off due to an overtemperature shutdown. Figure 7. Typical Circuit for the OC Pin Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2049 7 TPS2049 SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007......................................................................................................................................... www.ti.com POWER DISSIPATION AND JUNCTION TEMPERATURE The low on-resistance on the n-channel MOSFET allows small surface-mount packages to pass large currents. The thermal resistance of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest. Using this value, the power dissipation per switch can be calculated by: PD = rDS(on)× I2 Finally, calculate the junction temperature: TJ = PD × RΘJA + TA Where: TA = Ambient temperature °C RΘJA = Thermal resistance PD = Total power dissipation based on number of switches being used. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. THERMAL PROTECTION Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS2049 implement a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition the junction temperature will rise due to excessive power dissipation. Once the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OC open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs. UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMI and voltage overshoots. 8 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2049 TPS2049 www.ti.com......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 GENERIC HOT-PLUG APPLICATIONS (see Figure 8) In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS2049, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS2049 also ensures the switch will be off after the card has been removed, and the switch will be off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or module. Figure 8. Typical Hot-Plug Implementation By placing the TPS2049 between the VCC input and the rest of the circuitry, the input power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device. DETAILED DESCRIPTION POWER SWITCH The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a minimum current of 90 mA. CHARGE PUMP An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current. DRIVER The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. ENABLE (EN) The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 µA when a logic high is present on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2049 9 TPS2049 SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007......................................................................................................................................... www.ti.com OVERCURRENT (OC) The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 10-ms deglitch circuit prevents the OC signal from oscillation or false triggering. If an overtemperature shutdown occurs, the OC is asserted instantaneously. CURRENT SENSE A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load. THERMAL SENSE The TPS2049 implements a thermal sensing to monitor the operating temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output (OC) is asserted (active low) when an overtemperature shutdown or overcurrent occurs. UNDERVOLTAGE LOCKOUT A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2V, a control signal turns off the power switch. 10 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2049 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS2049D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2049 Samples TPS2049DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2049 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of