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TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
TPS20xxC and TPS20xxC-2 Current Limited, Power-Distribution Switches
1 Features
3 Description
•
•
•
•
•
•
•
The TPS20xxC and TPS20xxC-2 power-distribution
switch family is intended for applications, such as
USB, where heavy capacitive loads and short circuits
are likely to be encountered. This family offers
multiple devices with fixed current-limit thresholds for
applications from 0.5 A to 2 A.
1
•
•
•
•
Single Power Switch Family
Pin-for-Pin With Existing TI Switch Portfolio
Rated Currents of 0.5 A, 1 A, 1.5 A, 2 A
±20% Accurate, Fixed, Constant Current Limit
Fast Overcurrent Response: 2 µs
Deglitched Fault Reporting
Selected Parts With (TPS20xxC) and Without
(TPS20xxC-2) Output Discharge
Reverse Current Blocking
Built-In Soft Start
Ambient Temperature Range: –40°C to 85°C
UL Listed and CB-File No. E169910
The TPS20xxC and TPS20xxC-2 family limits the
output current to a safe level by operating in a
constant-current mode when the output load exceeds
the current limit threshold. This provides a predictable
fault current under all conditions. The fast overload
response time eases the burden on the main 5-V
supply to provide regulated power when the output is
shorted. The power-switch rise and fall times are
controlled to minimize current surges during turnon
and turnoff.
2 Applications
•
•
•
•
Device Information(1)
USB Ports and Hubs, Laptops, and Desktops
High-Definition Digital TVs
Set-Top Boxes
Short-Circuit Protection
PART NUMBER
TPS20xxC,
TPS20xxC-2
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
MSOP-PowerPAD (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
Fault Signal
Control Signal
IN
OUT
0.1 mF
VIN
RFLT
10 kW
VOUT
150 mF
FLT
EN or
EN
GND
Pad*
* DGN only
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
4
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information: SOT-23 ................................... 6
Thermal Information: MSOP-PowerPAD .................. 6
Electrical Characteristics: TJ = TA = 25°C................. 7
Electrical Characteristics: –40°C ≤ TJ ≤ 125°C......... 8
Timing Requirements: TJ = TA = 25°C...................... 9
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
11.3 Power Dissipation and Junction Temperature ...... 22
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (July 2013) to Revision H
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Devices table (previously Table 1) ........................................................................................................................... 4
Changes from Revision F (August 2012) to Revision G
Page
•
Deleted (See Table 1) from Feature: UL Listed and CB-File No. E169910 ........................................................................... 1
•
Changed From: PXKI To: PYKI in the DEVICE INFORMATION table SOT23-5 (DBV) column (TPS2069C) ...................... 4
•
Deleted Note 2 from : "UL listed and CB complete"............................................................................................................... 4
Changes from Revision E (April 2012) to Revision F
Page
•
Added device TPS20xxC-2 ................................................................................................................................................... 1
•
Changed Feature From: Ouput Discharge When TPS20XXC is Disabled To: Selected parts with (TPS20xxC) and
without (TPS20xxC-2) Output Discharge ............................................................................................................................... 1
•
Added devices TPS2041C, TPS2061C, TPS2065C-2, TPS2068C, and TPS2069C-2 to the Device Information table ....... 4
•
Added the TPS2069C-2 Device ............................................................................................................................................. 4
•
Added PXKI in the DEVICE INFORMATION table SOT23-5 (DBV) column (TPS2069C) .................................................... 4
•
Added devices TPS2041C, TPS2061C, TPS2065C-2, TPS2068C, and TPS2069C-2 to and removed Product Preview.... 4
•
Added Note 1 to the RECOMMENDED OPERATING CONDITIONS table........................................................................... 6
•
Added TPS2041C, TPS2061C, TPS2068C, TPS2065C-2 and TPS2069C-2 devices to IOUT in the RECOMMENDED
OPERATING CONDITIONS table .......................................................................................................................................... 6
•
Added the DBV option to Power Switch RDS(on) 1.5 A rated output, 25°C mΩ ....................................................................... 7
•
Added the DBV option to Power Switch RDS(on) 1.5 A rated output ....................................................................................... 7
•
Changed ISO Current Limit ..................................................................................................................................................... 7
2
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Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
www.ti.com
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
•
Added Leakage Current ......................................................................................................................................................... 7
•
Added the DBV option to Power Switch RDS(on) 1.5 A rated output . ..................................................................................... 8
•
Changed ISO Current Limit ..................................................................................................................................................... 8
•
Added Leakage Current ......................................................................................................................................................... 8
•
Changed the second para graph of the ENABLE section .................................................................................................... 15
•
Added sentence to end of paragraph in the OUTPUT DISCHARGE section ...................................................................... 16
Changes from Revision D (February 2012) to Revision E
•
Page
Changed the POWER DISSIPATION AND JUNCTION TEMPERATURE section. Replaced paragraph " While it is
recommended..."................................................................................................................................................................... 22
Changes from Revision C (October 2011) to Revision D
Page
•
Added Feature UL Listed and CB-File No. E169910 (See ) .................................................................................................. 1
•
Added table Note 2, UL listed and CB complete.................................................................................................................... 4
•
Added VIH and VIL information to the ROC Table................................................................................................................... 6
Changes from Revision B (September 2011) to Revision C
Page
•
Changed From: PXF1 To: PXFI and From: PSG1 To: PXGI in the DEVICE INFORMATION table MOSP-8 (DGK)
column .................................................................................................................................................................................... 4
•
Changed TPS2000C (MSOP-8) status From: Preview To: Active in Table 1 ........................................................................ 4
•
Changed the θJACustom 2 A Rated DGK value from N/A to 110.3 ...................................................................................... 7
•
Added Figure 45 - DGK Package PCB Layout Example ..................................................................................................... 23
Changes from Revision A (July 2011) to Revision B
Page
•
Added the DGK Package Information throughout the data sheet .......................................................................................... 4
•
Changed title of Figure 30 From: NEW FIG To: TPS2065C 50 Ω Short Circuit .................................................................. 19
Changes from Original (June 2011) to Revision A
Page
•
Changed the TPS2051C, TPS2065C, and TPS2069C Devices Status From: Preview To: Active ....................................... 4
•
Corrected pinout numbers for the 5-PIN PACKAGE ............................................................................................................. 5
Copyright © 2011–2016, Texas Instruments Incorporated
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Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
3
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
www.ti.com
5 Device Comparison Table
(1)
(2)
MAXIMUM
OPERATING
CURRENT
OUTPUT
DISCHARGE
ENABLE
BASE PART
NUMBER
0.5
Y
Low
TPS2041C
0.5
Y
High
1
Y
1
PACKAGED DEVICE AND MARKING (1)
MSOP-8 (DGN)
PowerPAD™
SOT23-5
(DBV)
VSSOP-8
(DGK)
— (2)
PYJI
—
TPS2051C
—
VBYQ
—
Low
TPS2061C
PXMI
PXLI
—
Y
High
TPS2065C
VCAQ
VCAQ
—
1
N
High
TPS2065C-2
PYRI
PYQI
—
1.5
Y
Low
TPS2068C
PXNI
—
—
1.5
Y
High
TPS2069C
VBUQ
PYKI
—
1.5
N
High
TPS2069C-2
PYSI
—
—
2
Y
Low
TPS2000C
BCMS
—
PXFI
2
Y
High
TPS2001C
VBWQ
–
PXGI
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
"–" indicates the device is not available in this package.
6 Pin Configuration and Functions
DGN Package
8-Pin MSOP-PowerPAD
Top View
GND
1
IN
2
DGK Package
8-Pin VSSOP
Top View
8
OUT
GND
1
8
OUT
7
OUT
IN
2
7
OUT
IN
3
6
OUT
EN/EN
4
5
FLT
PowerPAD
IN
3
6
OUT
EN/EN
4
5
FLT
Pin Functions - 8 Pins
PIN
NAME
NO.
EN/EN
4
FLT
GND
IN
OUT
PowerPAD
(DGN Only)
4
I/O
DESCRIPTION
I
Enable input, logic high turns on power switch
5
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions
1
—
Ground connection
2, 3
PWR
Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to
GND close to the IC
6, 7, 8
PWR
Power-switch output, connect to load
PowerPAD
—
Submit Documentation Feedback
Internally connected to GND. Connect PAD to GND plane as a heatsink for the best thermal
performance. PAD may be left floating if desired. See Power Dissipation and Junction
Temperature for guidance.
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
www.ti.com
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
DBV Package
5-Pin SOT-23
Top View
OUT
1
GND
2
FLT
3
5
IN
4
EN/EN
Pin Functions - 5 Pins
PIN
NAME
NO.
EN/EN
4
FLT
GND
I/O
DESCRIPTION
I
Enable input, logic high turns on power switch
3
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions
2
—
Ground connection
IN
5
PWR
Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to GND
close to the IC
OUT
1
PWR
Power-switch output, connect to load.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
Voltage on IN, OUT, EN or EN, FLT
(4)
MIN
MAX
UNIT
–0.3
6
V
Voltage from IN to OUT
–6
6
V
Maximum junction temperature, TJ
Internally Limited
Storage temperature, Tstg
–60
(1)
(2)
(3)
(4)
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Absolute maximum ratings apply over recommended junction temperature range.
Voltages are with respect to GND unless otherwise noted.
See Input and Output Capacitance.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
IEC 61000-4-2 contact discharge
±8000
IEC 61000-4-2 air-gap discharge (3)
±15000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
VOUT was surged on a PCB with input and output bypassing per the Typical Application Diagram on the first page (except input
capacitor was 22 µF) with no device failures.
Copyright © 2011–2016, Texas Instruments Incorporated
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TPS2069C TPS2069C-2
5
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
www.ti.com
7.3 Recommended Operating Conditions
MIN
VIN
Input voltage, IN
VEN
NOM
MAX
UNIT
4.5
5.5
V
Input voltage, EN or EN
0
5.5
V
VIH
High-level input voltage, EN or EN
2
VIL
Low-level input voltage, EN or EN
V
0.7
TPS2041C and TPS2051C
IOUT
Continuous output current,
OUT (1)
TJ
Operating junction temperature
IFLT
Sink current into FLT
TPS2061C, TPS2065C and TPS2065C-2
1
TPS2068C, TPS2069C and TPS2069C-2
1.5
TPS2000C and TPS2001C
(1)
V
0.5
A
2
–40
125
°C
0
5
mA
Some package and current rating may request an ambient temperature derating of 85°C.
7.4 Thermal Information: SOT-23
TPS20xxC, TPS20xxC-2
THERMAL METRIC (1)
DBV (SOT-23) (2)
DBV (SOT-23) (3)
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
224.9
220.4
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
95.2
89.7
°C/W
RθJB
Junction-to-board thermal resistance
51.4
46.9
°C/W
ψJT
Junction-to-top characterization parameter
6.6
5.2
°C/W
ψJB
Junction-to-board characterization parameter
50.3
46.2
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
—
—
°C/W
RθJACustom
See Power DIssipation and Junction Temperature
139.3
134.9
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Rated at 0.5 A or 1 A.
Rated at 1.5 A or 2 A.
7.5 Thermal Information: MSOP-PowerPAD
TPS20xxC, TPS20xxC-2
THERMAL METRIC (1)
DGN
(MSOPPowerPAD) (2)
DGN
(MSOPPowerPAD) (3)
DGK
(VSSOP) (4)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
72.1
67.1
205.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
87.3
80.8
94.3
°C/W
RθJB
Junction-to-board thermal resistance
42.2
37.2
126.9
°C/W
ψJT
Junction-to-top characterization parameter
7.3
5.6
24.7
°C/W
ψJB
Junction-to-board characterization parameter
42
36.9
125.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
39.2
32.1
—
°C/W
RθJACustom
See Power DIssipation and Junction Temperature
66.5
61.3
110.3
°C/W
(1)
(2)
(3)
(4)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Rated at 0.5 A or 1 A.
Rated at 1.5 A or 2 A.
Rated at 2 A.
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Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
www.ti.com
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
7.6 Electrical Characteristics: TJ = TA = 25°C
Unless otherwise noted: VIN = 5 V, VEN = VIN or VEN = GND, IOUT = 0 A. See Device Comparison Table for the rated current of
each part number. Parametrics over a wider operational range are shown in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C (1).
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
POWER SWITCH
0.5-A rated output, 25°C
DBV
97
110
mΩ
0.5-A rated output,
–40°C ≤ (TJ , TA) ≤ 85°C
DBV
96
130
mΩ
DBV
96
110
DGN
86
100
DBV
96
130
DGN
86
120
DBV
76
91
mΩ
DGN
69
84
mΩ
1.5-A rated output,
–40°C ≤ (TJ , TA) ≤ 85°C
DBV
76
106
mΩ
DGN
69
98
mΩ
2-A rated output, 25°C
DGN, DGK
72
84
mΩ
2-A rated output, –40°C ≤ (TJ , TA) ≤
85°C
DGN, DGK
72
98
mΩ
0.5-A rated output
TPS20xxC
0.67
0.85
1.01
TPS20xxC
1.3
1.55
1.8
1.18
1.53
1.88
1.7
2.15
2.5
TPS20xxC-2
1.71
2.23
2.75
TPS20xxC
2.35
2.9
3.4
0.01
1
1-A rated output, 25°C
RDS(on)
Input – output resistance
1-A rated output,
–40°C ≤ (TJ , TA) ≤ 85°C
1.5-A rated output, 25°C
mΩ
mΩ
CURRENT LIMIT
1-A rated output
IOS (2)
Current limit,
See Figure 6
1.5-A rated output
2-A rated output
TPS20xxC-2
TPS20xxC
A
SUPPLY CURRENT
ISD
Supply current, switch disabled
ISE
Supply current, switch enabled
Ilkg
Leakage current
IOUT = 0 A
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A
2
IOUT = 0 A
60
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A
VOUT = 0 V, VIN = 5 V, disabled,
measure IVIN
–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 0 V,
VIN = 5 V, disabled, measure IVIN
85
0.05
Reverse leakage current
µA
1
TPS20xxC-2
µA
2
VOUT = 5 V, VIN = 0 V, measure IVOUT
IREV
70
µA
0.1
–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 5 V, VIN = 0 V, measure
IVOUT
1
5
µA
OUTPUT DISCHARGE
RPD
(1)
(2)
(3)
Output pulldown resistance (3)
VIN = VOUT = 5 V, disabled
TPS20xxC
400
470
600
Ω
Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
See Current Limit section for explanation of this parameter.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Copyright © 2011–2016, Texas Instruments Incorporated
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Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
7
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
www.ti.com
7.7 Electrical Characteristics: –40°C ≤ TJ ≤ 125°C
Unless otherwise noted:4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN or VEN = GND, IOUT = 0 A, typical values are at 5 V and 25°C. See
Device Comparison Table for the rated current of each part number.
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
DBV
97
154
mΩ
DBV
96
154
DGN
86
140
DBV
76
121
mΩ
DGN
69
112
mΩ
DGN, DGK
72
112
mΩ
POWER SWITCH
0.5-A rated output
1-A rated output
RDS(ON)
Input – output resistance
1.5-A rated output
2-A rated output
mΩ
ENABLE INPUT (EN or EN)
Threshold
Input rising
1
1.45
2
0.07
0.13
0.2
V
–1
0
1
µA
TPS20xxC
0.65
0.85
1.05
TPS20xxC
1.2
1.55
1.9
TPS20xxC-2
1.1
1.53
1.96
TPS20xxC
1.6
2.15
2.7
TPS20xxC-2
1.6
2.23
2.86
TPS20xxC
2.3
2.9
3.6
Hysteresis
Leakage current
(VEN or VEN) = 0 V or 5.5 V
V
CURRENT LIMIT
0.5-A rated output
1-A rated output
IOS (2)
Current limit,
See Figure 23
1.5-A rated output
2-A rated output
Short-circuit response time (3)
tIOS
VIN = 5 V (see Figure 6),
One-half full load → RSHORT = 50 mΩ,
Measure from application to when current falls below 120% of
final value
2
A
µs
SUPPLY CURRENT
ISD
Supply current, switch disabled
IOUT = 0 A
0.01
10
µA
ISE
Supply current, switch enabled
IOUT = 0 A
65
90
µA
Ilkg
Leakage current
VOUT = 0 V, VIN = 5 V, disabled,
measure IVIN
IREV
Reverse leakage current
VOUT = 5.5 V, VIN = 0 V, measure IVOUT
TPS20XXC-2
0.05
µA
0.2
20
µA
3.75
4
V
UNDERVOLTAGE LOCKOUT
VUVLO
Rising threshold
VIN↑
Hysteresis (3)
VIN↓
Output low voltage, FLT
IFLT = 1 mA
OFF-state leakage
VFLT = 5.5 V
FLT deglitch
FLT assertion or deassertion deglitch
3.5
0.14
V
FLT
tFLT
0.2
V
1
µA
ms
6
9
12
OUTPUT DISCHARGE
RPD
Output pulldown resistance
VIN = 4 V, VOUT = 5 V, disabled
TPS20XXC
350
560
1200
VIN = 5 V, VOUT = 5 V, disabled
TPS20XXC
300
470
800
Ω
THERMAL SHUTDOWN
Rising threshold (TJ)
Hysteresis
(1)
(2)
(3)
8
(3)
In current limit
135
Not in current limit
155
°C
20
Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
See Current Limit for explanation of this parameter.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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7.8 Timing Requirements: TJ = TA = 25°C
MIN
NOM
MAX
UNIT
ENABLE INPUT (EN or EN)
1
1.4
1.8
Turnon time
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↑ or EN
↓.
See Figure 1, Figure 3, and Figure 4
0.5-A and 1-A Rated
tON
1.5-A and 2-A Rated
1.2
1.7
2.2
1.3
1.65
2
Turnoff time
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↓ or EN
↑.
See Figure 1, Figure 3, and Figure 4
0.5-A and 1-A Rated
tOFF
1.5-A and 2-A Rated
1.7
2.1
2.5
tR
Rise time, output
CL = 1 µF, RL = 100 Ω, VIN = 5 V. See
Figure 2
0.5-A and 1-A Rated
0.4
0.55
0.7
1.5-A and 2-A Rated
0.5
0.7
1
tF
Fall time, output
CL = 1 µF, RL = 100 Ω, VIN = 5 V. See
Figure 2
0.5-A and 1-A Rated
0.25
0.35
0.45
1.-5A and 2-A Rated
0.3
0.43
0.55
ms
ms
ms
ms
OUT
RL
CL
Figure 1. Output Rise and Fall Test Load
VOUT
tR
90%
tF
10%
Figure 2. Power-On and Power-Off Timing
VEN
50%
tON
50%
tOFF
90%
VOUT
10%
Figure 3. Enable Timing, Active High Enable
V/EN
50%
50%
tOFF
tON
90%
VOUT
10%
Figure 4. Enable Timing, Active Low Enable
120% x IOS
IOUT
IOS
0A
tIOS
Figure 5. Output Short-Circuit Parameters
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VIN
Decreasing
Load
Resistance
VOUT
Slope = -RDS(ON)
0V
0A
IOUT
IOS
Figure 6. Output Characteristic Showing Current Limit
10
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7.9 Typical Characteristics
9.3
14
VIN = 5 V
All Versions, 5 V
85°C
12
IOUT sinking (mA)
tFLT (ms)
9.2
9.1
9.0
25°C
10
8
−40°C
6
125°C
4
8.9
2
8.8
−40
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
0
0.0
140
0.5
1.0
1.5
G019
Figure 7. Deglitch Period (TFLT) vs Temperature
2.0 2.5 3.0 3.5
Output Voltage (V)
4.0
4.5
5.0
5.5
G020
Figure 8. Output Discharge Current vs Output Voltage
3.5
7
2-A Rated
VIN = 5 V
All Unit Types, 5 V
6
3.0
5
IOS (A)
2.0
IREV (µA)
1.5-A Rated
2.5
1-A Rated
1.5
0.5-A Rated
3
2
1
1.0
0.5
−40
4
0
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
−1
−40
140
Figure 9. Short Circuit Current (IOS) vs Temperature
20
40
60
80
100
Junction Temperature (°C)
120
140
G022
1.0
Input Voltage = 5.5 V
All Unit Types
0.8
0.8
0.6
0.6
ISD (µA)
ISD (µA)
0
Figure 10. Reverse Leakage Current (IREV) vs Temperature
1.0
0.4
125°C
0.4
0.2
0.2
0.0
0.0
−0.2
−40
−20
G021
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
G023
Figure 11. Disabled Supply Current (ISD) vs Temperature
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−0.2
4.00
85°C
−40°C and 25°C
4.25
4.50
4.75
5.00
Input Voltage (V)
5.25
5.50
G024
Figure 12. Disabled Supply Current (ISD) vs Input Voltage
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6.0
All unit types, VIN = 0 V
5.5
5.0
4.5
125°C
4.0
3.5
3.0
2.5
2.0
85°C
1.5
25°C
−40°C
1.0
0.5
0.0
−0.5
4.00
4.25
4.50
4.75
5.00
5.25
Output Voltage (V)
80
All Unit Types, VIN = 5.5 V
75
70
ISE (µA)
IREV (µA)
Typical Characteristics (continued)
60
55
50
−40
5.50
−20
0
G025
Figure 13. Reverse Leakage Current (IREV) vs Output Voltage
0.475
75
125°C
85°C
70
tf (ms)
55
0.400
1.5-A and 2-A Rated, VIN = 4.5 V
1.5-A and 2-A Rated, VIN = 5 V
0.375
1.5-A and 2-A Rated, VIN = 5.5 V
0.350
25°C
45
−40°C
40
4.00
4.25
0.5-A and 1-A Rated, VIN = 5 V
4.50
4.75
5.00
Input Voltage (V)
5.25
5.50
0.325
−40
20
40
60
80
100
Junction Temperature (°C)
120
140
G028
Figure 16. Output Fall Time (TF) vs Temperature
130
1.5 A, 2 A, 5.5 V
VIN = 5 V
120
0.75
0.5-A, 1-A Rated
110
RDSON (mΩ)
tr (ms)
0
140
COUT = 1 µF, RLOAD = 100 Ω
0.80
−20
G027
Figure 15. Enabled Supply Current (ISE) vs Input Voltage
0.70
0.65
0.5 A, 1 A, 5 V
100
90
80
70
1.5 A, 2 A, 5 V
1.5-A, 2-A Rated
60
1.5 A, 2 A, 4.5 V
0.55
50
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
Figure 17. Output Rise Time (TR) vs Temperature
12
G026
COUT = 1 µF, RLOAD = 100 Ω
50
0.50
−40
140
0.425
60
0.60
120
0.450
65
0.85
20
40
60
80
100
Junction Temperature (°C)
Figure 14. Enabled Supply Current (ISE) vs Temperature
80
ISE (µA)
65
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G029
40
−40
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
G030
Figure 18. Input-Output Resistance (RDS(ON)) vs Temperature
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Typical Characteristics (continued)
100
Recovery Time (µs)
VIN = 5 V, CIN = 730 µF, TPS2065C, IEND = 1.68 A
IOS
10
1
0
5
10
15
IPK (Shorted) (A)
20
25
G031
Figure 19. Recovery vs Current Peak
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8 Detailed Description
8.1 Overview
The TPS20xxC and TPS20xxC-2 are current-limited, power-distribution switches providing a range from 0.5 A
and 2 A of continuous load current in 5-V circuits. These parts use N-channel MOSFETs for low resistance,
maintaining voltage regulation to the load. They are designed for applications where short circuits or heavy
capacitive loads are encountered. Device features include enable, reverse blocking when disabled, output
discharge pulldown, overcurrent protection, overtemperature protection, and deglitched fault reporting.
8.2 Functional Block Diagram
Current
Sense
IN
Charge
Pump
CS
OUT
Current
Limit
EN or
EN
(Disabled+
UVLO)
Driver
FLT
UVLO
OTSD
Thermal
Sense
GND
9-ms
Deglitch
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Figure 20. TPS20xxC Block Diagram
Current
Sense
IN
Charge
Pump
EN or
EN
CS
OUT
Current
Limit
Driver
UVLO
GND
FLT
OTSD
Thermal
Sense
9-ms
Deglitch
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Figure 21. TPS20xxC-2 Block Diagram
8.3 Feature Description
8.3.1 Undervoltage Lockout
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turnon threshold. Built-in hysteresis prevents unwanted ON/OFF cycling due to input voltage drop from large
current surges. FLT is high impedance when the TPS20xxC and TPS20xxC-2 are in UVLO.
14
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Feature Description (continued)
8.3.2 Enable
The logic enable input (EN, or EN), controls the power switch, bias for the charge pump, driver, and other
circuits. The supply current is reduced to less than 1 µA when the TPS20xxC and TPS20xxC-2 are disabled.
Disabling the TPS20xxC and TPS20xxC-2 immediately clears an active FLT indication. The enable input is
compatible with both TTL and CMOS logic levels.
The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times
are internally controlled. The rise time is controlled by both the TPS20xxC and TPS20xxC-2 and the external
loading (especially capacitance). TPS20xxC fall time is controlled by the loading (R and C), and the output
discharge (RPD). TPS20xxC-2 does not have the output discharge (RPD), fall time is controlled by the loading (R
and C). An output load consisting of only a resistor experiences a fall time set by the TPS20xxC and TPS20xxC2. An output load with parallel R and C elements experiences a fall time determined by the (R × C) time constant
if it is longer than the tF TPS20xxC and TPS20xxC-2.
The enable must not be left open, and may be tied to VIN or GND depending on the device.
8.3.3 Internal Charge Pump
The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel
MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull
the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of
the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start
functionality. The MOSFET power switch blocks current from OUT to IN when turned off by the UVLO or
disabled.
8.3.4 Current Limit
The TPS20xxC and TPS20xxC-2 responds to overloads by limiting output current to the static IOS levels shown in
Electrical Characteristics: TJ = TA = 25°C. When an overload condition is present, the device maintains a
constant output current, with the output voltage determined by (IOS × RLOAD). Two possible overload conditions
can occur. The first overload condition occurs when either:
1. input voltage is first applied, enable is true, and a short circuit is present (load which draws IOUT > IOS)
2. input voltage is present and the TPS20xxC and TPS20xxC-2 are enabled into a short circuit.
The output voltage is held near zero potential with respect to ground and the TPS20xxC and TPS20xxC-2 ramps
the output current to IOS. The TPS20xxC and TPS20xxC-2 limits the current to IOS until the overload condition is
removed or the device begins to thermal cycle. This is demonstrated in Figure 26 where the device was enabled
into a short, and subsequently cycles current OFF and ON as the thermal protection engages.
The second condition is when an overload occurs while the device is enabled and fully turned on. The device
responds to the overload condition within tIOS (Figure 5 and Figure 6) when the specified overload (see Electrical
Characteristics: –40°C ≤ TJ ≤ 125°C) is applied. The response speed and shape varies with the overload level,
input circuit, and rate of application. The current limit response will vary between simply settling to IOS, or turnoff
and controlled return to IOS. Similar to the previous case, the TPS20xxC and TPS20xxC-2 limits the current to IOS
until the overload condition is removed or the device begins to thermal cycle. This is demonstrated by Figure 27,
Figure 28, and Figure 29.
The TPS20xxC and TPS20xxC-2 thermal cycles if an overload condition is present long enough to activate
thermal limiting in any of the above cases. This is due to the relatively large power dissipation [(VIN – VOUT) × IOS]
driving the junction temperature up. The device turns off when the junction temperature exceeds 135°C
(minimum) while in current limit. The device remains off until the junction temperature cools 20°C and then
restarts.
There are two kinds of current limit profiles typically available in TI switch products that are similar to the
TPS20xxC and TPS20xxC-2. Many older designs have an output I vs V characteristic similar to the plot labeled
Current Limit with Peaking in Figure 22. This type of limiting can be characterized by two parameters, the current
limit corner (IOC), and the short circuit current (IOS). IOC is often specified as a maximum value. The TPS20xxC
and TPS20xxC-2 family of parts does not present noticeable peaking in the current limit, corresponding to the
characteristic labeled Flat Current Limit in Figure 22. This is why the IOC parameter is not present in Electrical
Characteristics: –40°C ≤ TJ ≤ 125°C.
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Feature Description (continued)
Current Limit
with Peaking
Flat Current
Limit
VIN
Decreasing
Load
Resistance
Decreasing
Load
Resistance
Slope = -RDS(ON)
VOUT
VO UT
Slope = -RDS(ON)
VIN
0V
0V
0A
IOUT
IOS IOC
IOUT
0A
I OS
Figure 22. Current Limit Profiles
8.3.5 FLT
The FLT open-drain output is asserted (active low) during an overload or overtemperature condition. A 9-ms
deglitch on both the rising and falling edges avoids false reporting at start-up and during transients. A current
limit condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer does
not integrate multiple short overloads and declare a fault. This is also true for exiting from a faulted state. An
input voltage with excessive ripple and large output capacitance may interfere with operation of FLT around IOS
as the ripple drives the TPS20xxC and TPS20xxC-2 in and out of current limit.
If the TPS20xxC and TPS20xxC-2 are in current limit and the overtemperature circuit goes active, FLT goes true
immediately (see Figure 27); however, the exiting this condition is deglitched (see Figure 29). FLT is tripped just
as the knee of the constant-current limiting is entered. Disabling the TPS20xxC and TPS20xxC-2 clears an active
FLT as soon as the switch turns off (see Figure 26). FLT is high impedance when the TPS20xxC and TPS20xxC2 are disabled or in undervoltage lockout (UVLO).
8.3.6 Output Discharge
A 470-Ω (typical) output discharge dissipates stored charge and leakage current on OUT when the TPS20xxC is
in UVLO or disabled. The pulldown circuit loses bias gradually as VIN decreases, causing a rise in the discharge
resistance as VIN falls towards 0 V. The TPS20xxC-2 does not have this function. The output is be controlled by
an external loadings when the device is in ULVO or disabled.
8.4 Device Functional Modes
There are no other functional modes.
16
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SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS20xxC and TPS20xxC-2 current-limited power switch uses N-channel MOSFETs in applications
requiring continuous load current. The device enters constant-current mode when the load exceeds the current
limit threshold.
9.2 Typical Application
TPS2065CDGN
4.5 V-6.5 V
VOUT
0.1PF
1/2
OUT
IN
6/7/8
COUT
RFAULT
Fault
Signal
Control
Signal
5
FAULT
4
EN
Power
Pad
GND
1
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the following input parameters:
1. The TPS2065CDGN operates from a 5-V to ±0.5-V input rail.
2. What is the normal operation current, for example, the maximum allowable current drawn by portable
equipment for USB 3.0 port is 900 mA, so the normal operation current is 900 mA, and the minimum current
limit of power switch must exceed 900 mA to avoid false trigger during normal operation. For the TPS2065C
device, target 1-A continuous output current application.
3. What is the maximum allowable current provided by up-stream power, the maximum current limit of power
switch that must lower it to ensure power switch can protect the up-stream power when overload is
encountered at the output of power switch. For the TPS2065C device, the maximum IOS is 1.8 A.
9.2.2 Detailed Design Procedure
To
1.
2.
3.
begin the design process a few parameters must be decided upon. The designer must know the following:
Normal input operation voltage
Output continuous current
Maximum up-stream power supply output current
9.2.2.1 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance must be optimized
for the particular application. For all applications, TI recommends placing a 0.1-µF or greater ceramic bypass
capacitor between IN and GND, as close to the device as possible for local noise decoupling.
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Typical Application (continued)
All protection circuits such as the TPS20xxC and TPS20xxC-2 has the potential for input voltage overshoots and
output voltage undershoots.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input
voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high
impedance (before turnon). Theoretically, the peak voltage is 2× the applied. The second cause is due to the
abrupt reduction of output short-circuit current when the TPS20xxC and TPS20xxC-2 turns off and energy stored
in the input inductance drives the input voltage high. Input voltage droops may also occur with large load steps
and as the TPS20xxC and TPS20xxC-2 output is shorted. Applications with large input inductance (for example,
connecting the evaluation board to the bench power-supply through long cables) may require large input
capacitance reduce the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast
current limit speed of the TPS20xxC and TPS20xxC-2 to hard output short circuits isolates the input bus from
faults. However, ceramic input capacitance in the range of 1 µF to 22 µF adjacent to the TPS20xxC and
TPS20xxC-2 input aids in both speeding the response time and limiting the transient seen on the input power
bus. Momentary input transients to 6.5 V are permitted.
Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred
and the TPS20xxC and TPS20xxC-2 has abruptly reduced OUT current. Energy stored in the inductance drives
the OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such
as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When
implementing USB standard applications, a 120-µF minimum output capacitance is required. Typically a 150-µF
electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application does
not require 120 µF of capacitance, and there is potential to drive the output negative, then TI recommends a
minimum of 10-µF ceramic capacitance on the output. The voltage undershoot must be controlled to less than
1.5 V for 10 µs.
9.2.3 Application Curves
Output Current
7
Amplitude (V)
6
FLT
2.00
9
1.75
8
1.50
7
1.25
6
5
1.00
4
0.75
3
0.50
EN
2
1
Output Voltage
0
−1
−2m
0
2m
4m
6m
1.75
1.50
Output Voltage
FLT
1.25
1.00
5
0.75
4
EN
3
0.50
2
0.25
0.00
1
0.00
−0.25
0
−0.25
−0.50
8m 10m 12m 14m 16m 18m 20m
Time (s)
Submit Documentation Feedback
Output Current
2.00
0.25
Figure 24. TPS2065C Output Rise / Fall 5 Ω
18
VIN = 5 V, COUT = 150 µF, RLOAD = 100 Ω, TPS2065C
−1
−2m
G001
0
2m
4m
6m
−0.50
8m 10m 12m 14m 16m 18m 20m
Time (s)
Current (A)
VIN = 5 V, COUT = 150 µF, RLOAD = 5 Ω, TPS2065C
Amplitude (V)
8
Current (A)
9
G002
Figure 25. TPS2065C Output Rise / Fall 100 Ω
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
www.ti.com
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
Typical Application (continued)
8
7
1.50
7
6
1.25
6
1.20
5
1.00
0.75
4
0.50
3
EN
2
Output Voltage
1
0
−1
−2m
0
2m
4m
4
0.50
2
0.25
0.00
1
0.00
−0.25
0
Output Voltage
2.5m
7.5m
G003
12.5m
Time (s)
17.5m
−0.50
22.5m25m
G004
Figure 27. TPS2065C Pulsed Short Applied
30
6
VIN = 5 V, COUT = 0 µF, RLOAD = 50 mΩ, TPS2065C
25
Output Voltage (V)
5
Current (A)
Voltage (V)
26
24
22
20
18
16
14
12
10
8
6
4
2
0
−0.25
−1
−2.5m
4
20
IOUT
15
3
VOUT
2
10
1
5
0
0
−1
−1u
0
1u
2u
3u
4u
G005
G006
Figure 29. TPS2065C Pulsed 1.45-A Load
2.5
6
VIN = 5 V, COUT = 0 µF,
RLOAD = 50 mΩ, TPS2065C
2.00
9
8
2.0
VIN = 5 V, COUT = 150 µF, RLOAD = 7.5Ω, TPS2065C
1.75
1.50
1.0
3
IOUT
0.5
VOUT
1
0.0
6
Amplitude (V)
1.5
4
Output Current (A)
Output Voltage (V)
7
2
−0.5
0
0
100u
200u
300u
Time (s)
400u
500u
Copyright © 2011–2016, Texas Instruments Incorporated
1.25
4
1.00
EN, VIN
0.75
0.50
3
FLT
2
0.25
Output Current
0.00
−0.25
0
−1.0
600u
Figure 30. TPS2065C 50-mΩ Short Circuit
Output Voltage
5
1
−1
−100u
−5
Time (s)
Figure 28. TPS2065C Short Applied
5
0.75
FLT
3
Figure 26. TPS2065C Enable into Output Short
4u
1.50
EN
0.25
−0.50
6m 8m 10m 12m 14m 16m 18m
Time (s)
10
VIN = 5 V, COUT = 0 µF, TPS2065C
9
8
Input Voltage
7
6
5
4
3
Output Voltage
2
1
0
Output Current
−1
−2
−3
−1u
0
1u
2u
3u
Time (s)
1.80
Current (A)
1.00
Output Current
Output Current (A)
FLT
Output Current
5
2.00
VIN = 5 V, COUT = 150 µF, RLOAD = 50 mΩ, TPS2065C
G007
Current (A)
Amplitude (V)
VIN = 5 V, COUT = 150 µF, RLOAD = 0 Ω, TPS2065C
Amplitude (V)
9
1.75
8
Current (A)
2.00
9
−1
−5m −4m −3m −2m −1m 0
1m
Time (s)
2m
3m
4m
−0.50
5m
G008
Figure 31. TPS2065C Power Up – Enabled
Submit Documentation Feedback
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
19
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
www.ti.com
Typical Application (continued)
6
1.25
5
1.00
FLT
EN, VIN
0.75
0.50
3
2
VIN = 5 V, COUT = 150 µF, RLOAD = 2.5 Ω, TPS2001C
Output Current
7
1
0.00
0
−0.25
Output Voltage
−1
−40m −30m −20m −10m
0
10m
Time (s)
20m
30m
FLT
1.2
0.8
3
1
0
EN
FLT
3.6
9
3.2
8
2.8
7
2.4
6
2.0
4
1.6
3
1.2
2
Output Voltage 0.8
1
0.4
0
0.0
−1
−2m
0
2m
4m
−0.4
6m 8m 10m 12m 14m 16m 18m
Time (s)
Amplitude (V)
Amplitude (V)
6
5
Output Voltage
Amplitude (V)
6
FLT
5
Output Current
1.6
Output Voltage
G011
9
1.2
8
1.0
7
0.8
6
1.0
5
0.8
4
0.6
0.6
−0.2
1
−0.4
0
−0.6
6m 8m 10m 12m 14m 16m 18m
Time (s)
Figure 36. TPS2051C Turnon into 10 Ω
20
1.4
2
4m
Submit Documentation Feedback
−0.4
2.5m 5m 7.5m 10m 12.5m 15m 17.5m 20m 22.5m
Time (s)
G012
Figure 35. TPS2001C Pulsed Output Short
0.0
2m
0.4
0.0
0
2
0
1.2
0.8
FLT
−1
−2.5m 0
0.2
−1
−2m
2.8
2.0
3
3
0
3.2
2.4
EN
4
0.4
EN
G010
3.6
5
4
1
−0.8
8m 10m 12m 14m 16m 18m
Time (s)
1
Amplitude (V)
Output Current
7
6m
2
Current (A)
VIN = 5 V, COUT = 150 µF, RLOAD = 10 Ω, TPS2051C
8
4m
VIN = 5 V, COUT = 150 µF, RLOAD = 50mΩ, TPS2001C
Figure 34. TPS2001C Enable into Short
9
2m
Figure 33. TPS2001C Turnon into 2.5 Ω
Current (A)
Output Current
7
0.0
−0.4
−1
−2m
G009
VIN = 5 V, COUT = 150 µF, RLOAD = 50 mΩ, TPS2001C
0.4
Output Voltage
Figure 32. TPS2065C Power Down – Enabled
8
2.0
1.6
EN
−0.50
40m
9
2.8
2.4
5
0.25
Output Current
3.2
Current (A)
1.50
Amplitude (V)
7
4
9
1.75
1.4
1.2
Output Current
0.4
3
−1
−2m
G013
1.6
VIN = 5 V, COUT = 150 µF, RLOAD = 50 mΩ, TPS2051C
EN
Output Voltage
FLT
Current (A)
VIN = 5 V, COUT = 150 µF, RLOAD = 7.5Ω, TPS2065C
Current (A)
Amplitude (V)
8
Current (A)
2.00
9
0.2
0.0
−0.2
0
2m
4m
6m
−0.4
8m 10m 12m 14m 16m 18m
Time (s)
G014
Figure 37. TPS2051C Enable into Short
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
www.ti.com
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
Typical Application (continued)
1.4
0.8
5
0.6
EN
0.4
0.2
3
2
FLT
0.0
1
Output Voltage
−0.2
−1
−2.5m 0
−0.6
2.5m 5m 7.5m 10m 12.5m 15m 17.5m 20m 22.5m
Time (s)
1.5
8
EN
6
0.5
0.0
FLT
Output Voltage
0
−2
−4m −2m
2.5
FLT
0
−2
0
2m
4m
6m
2.5
6
2.0
4
1.5
2
0.5
0
0.0
−2
−0.5
8m 10m 12m 14m 16m 18m
Time (s)
0.5
0.0
Figure 40. TPS2069C Enable into Short
−4
−12.5m
G017
1.0
Output Current
Output Voltage
Output Voltage
−4
−2m
3.0
8
2.0
1.0
2
G016
EN
1.5
4
−1.0
6m 8m 10m 12m 14m 16m
Time (s)
VIN = 5 V, COUT = 150 µF, RLOAD = 50 mΩ, TPS2069C
Amplitude (V)
Amplitude (V)
6
4m
10
Current (A)
Output
Current
2m
−0.5
Figure 39. TPS2069C Turnon into 3.3 Ω
3.0
EN
0
G015
VIN = 5 V, COUT = 150 µF, RLOAD = 50 mΩ, TPS2069C
8
1.0
4
Figure 38. TPS2051C Pulsed Output Short
10
Output Current
2
−0.4
0
2.0
10
1.0
6
4
2.5
Current (A)
Output Current
VIN = 5 V, COUT = 150 µF, RLOAD = 3.3 Ω, TPS2069C
Current (A)
Amplitude (V)
7
12
1.2
Amplitude (V)
VIN = 5 V, COUT = 150 µF, RLOAD = 50mΩ, TPS2051C
8
Current (A)
9
−7.5m
FLT
−2.5m
2.5m
Time (s)
7.5m
−0.5
12.5m
G018
Figure 41. TPS2069C Pulsed Output Short
10 Power Supply Recommendations
Design of the devices is for operation from an input voltage supply range of 4.5 V to 5.5 V. The current capability
of the power supply should exceed the maximum current limit of the power switch.
Copyright © 2011–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
21
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
www.ti.com
11 Layout
11.1 Layout Guidelines
1. Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low
inductance trace.
2. Place at least 10-µF low ESR ceramic capacitor near the OUT and GND pins, and make the connections
using a low inductance trace.
3. The PowerPAD must be directly connected to PCB ground plane using wide and short copper trace.
11.2 Layout Example
Via to Bottom Layer Signal Ground Plane
Via to Bottom Layer Signal
1
8
2
7
3
6
4
5
Figure 42. Recommended Layout
11.3 Power Dissipation and Junction Temperature
It is good design practice to estimate power dissipation and maximum expected junction temperature of the
TPS20xxC and TPS20xxC-2. The system designer can control choices of package, proximity to other power
dissipating devices, and printed-circuit board (PCB) design based on these calculations. These have a direct
influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature,
are often determined by system considerations. It is important to remember that these calculations do not include
the effects of adjacent heat sources, and enhanced or restricted air flow.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and
maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the
pad improve the efficiency and reliability of both TPS20xxC and TPS20xxC-2 parts and the system. The following
examples were used to determine the θJACustom thermal impedances noted in Thermal Information: SOT-23
and Thermal Information: MSOP-PowerPAD. They were based on use of the JEDEC high-k circuit board
construction (2 signal and 2 plane) with 4, 1-oz. copper weight, layers.
While TI recommends that the DGN package PAD be soldered to circuit board copper fill and vias for low thermal
impedance, there may be cases where this is not desired. For example, use of routing area under the IC. Some
devices are available in packages without the PowerPad (DGK) specifically for this purpose. The θJA for the DGN
package with the pad not soldered and no extra copper, is approximately 141°C/W for 0.5-A and 1-A rated parts,
and 139°C/W for the 1.5-A and 2-A rated parts. The θJA for the DGK mounted per Figure 45 is 110.3°C/W. These
values may be used in Equation 1 to determine the maximum junction temperature.
22
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
www.ti.com
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
Power Dissipation and Junction Temperature (continued)
GND: 0.052in2 Total
& 3 x 0.018in vias
COUT
0.050in trace
CIN
4 x 0.01in vias
VIN : 0.00925in2
& 3 x 0.018in vias
VOUT: 0.041in2 total
Figure 43. DBV Package PCB Layout Example
GND: 0.056in2 total area
& 3 x 0.018in vias
COUT
0.050in trace
CIN
VIN: 0.0145in2 area
& 2 x 0.018in vias
VOUT: 0.048in2 total area
5 x 0.01in vias
Figure 44. DGN Package PCB Layout Example
0.100 x 0.175
& 5 18 mil vias
0.185 x 0.045
& 3 18 mil vias
0.08 x 0.250
0.15 x 0.15
50 mil trace
0.100 x 0.060
& 3 18 mil vias to
inner plane 2
0.07 x 0.08
10 mil trace
10 mil trace
Figure 45. DGK Package PCB Layout Example
As shown in Equation 1, the following procedure requires iteration because power loss is due to the internal
MOSFET I2 × RDS(ON), and RDS(ON) is a function of the junction temperature. As an initial estimate, use the
RDS(ON) at 125°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred
board construction from the Thermal Information: SOT-23 table.
Copyright © 2011–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
23
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
www.ti.com
Power Dissipation and Junction Temperature (continued)
TJ = TA + ((IOUT2 × RDS(ON)) × θJA)
where
•
•
•
•
•
IOUT = rated OUT pin current (A)
RDS(ON) = Power switch ON-resistance at an assumed TJ (Ω)
TA = Maximum ambient temperature (°C)
TJ = Maximum junction temperature (°C)
θJA = Thermal resistance (°C/W)
(1)
If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using
the typical characteristic plot and recalculate.
If the resulting TJ is not less than 125°C, try a PCB construction or a package with lower θJA.
24
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C
TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2
www.ti.com
SLVSAU6H – JUNE 2011 – REVISED APRIL 2016
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS2000C
Click here
Click here
Click here
Click here
Click here
TPS2001C
Click here
Click here
Click here
Click here
Click here
TPS2041C
Click here
Click here
Click here
Click here
Click here
TPS2051C
Click here
Click here
Click here
Click here
Click here
TPS2061C
Click here
Click here
Click here
Click here
Click here
TPS2065C
Click here
Click here
Click here
Click here
Click here
TPS2065C-2
Click here
Click here
Click here
Click here
Click here
TPS2068C
Click here
Click here
Click here
Click here
Click here
TPS2069C
Click here
Click here
Click here
Click here
Click here
TPS2069C-2
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C
TPS2069C TPS2069C-2
25
PACKAGE OPTION ADDENDUM
www.ti.com
26-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
905X0205100
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
VBYQ
TPS2000CDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PXFI
TPS2000CDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PXFI
TPS2000CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BCMS
TPS2000CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BCMS
TPS2001CDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PXGI
TPS2001CDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PXGI
TPS2001CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
VBWQ
TPS2001CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
VBWQ
TPS2041CDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PYJI
TPS2041CDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PYJI
TPS2051CDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
VBYQ
TPS2051CDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
VBYQ
TPS2061CDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PXLI
TPS2061CDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PXLI
TPS2061CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PXMI
TPS2061CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PXMI
TPS2065CDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
VCAQ
TPS2065CDBVR-2
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PYQI
TPS2065CDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
VCAQ
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
26-Feb-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
NIPDAU
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS2065CDBVT-2
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
PYQI
TPS2065CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
VCAQ
TPS2065CDGN-2
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
PYRI
TPS2065CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
VCAQ
TPS2065CDGNR-2
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PYRI
TPS2068CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PXNI
TPS2068CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PXNI
TPS2069CDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PYKI
TPS2069CDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PYKI
TPS2069CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
VBUQ
TPS2069CDGN-2
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
PYSI
TPS2069CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
VBUQ
TPS2069CDGNR-2
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
PYSI
NIPDAUAG
NIPDAUAG
NIPDAUAG
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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