TPS2062CDRBR-2

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 TPS20xxC, TPS20xxC-2 Dual Channel, Current-Limited, Power-Distribution Switches 1 Features 3 Description • • • • • • • • The TPS20xxC and TPS20xxC-2 dual powerdistribution switch family is intended for applications such as USB where heavy capacitive loads and short-circuits may be encountered. This family offers multiple devices with fixed current-limit thresholds for applications between 0.5 A and 2 A. 1 • • • • Dual Power Switch Family Rated Currents of 0.5 A, 1 A, 1.5 A, 2 A Accurate ±20% Current Limit Tolerance Fast Overcurrent Response – 2 µs (Typical) 70-mΩ (Typical) High-Side N-Channel MOSFET Operating Range: 4.5 V to 5.5 V Deglitched Fault Reporting (FLTx) Selected Parts With (TPS20xxC) and Without (TPS20xxC-2) Output Discharge Reverse Current Blocking Built-in Softstart Pin for Pin With Existing TI Switch Portfolio Ambient Temperature Range: –40°C to 85°C The TPS20xxC and TPS20xxC-2 dual family limits the output current to a safe level by operating in a constant-current mode when the output load exceeds the current-limit threshold. This provides a predictable fault current under all conditions. The fast overcurrent response time eases the burden on the main 5 V supply to provide regulated power when the output is shorted. The power-switch rise and fall times are controlled to minimize current surges during turnon and turnoff. Device Information(1) 2 Applications • • • • PART NUMBER USB Ports or Hubs, Laptops, Desktops High-Definition Digital TVs Set Top Boxes Short Circuit Protection PACKAGE BODY SIZE (NOM) TPS2052C TPS2062C TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 MSOP (8) 3.00 mm × 3.00 mm TPS2062C TPS2066C SOIC (8) 3.90 mm × 4.90 mm TPS2062C-2 SON (8) 3.00 mm × 3.00 mm TPS2002C TPS2003C VSON (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application VIN 0.1 mF IN RFLT1 RFLT2 10 kW 10 kW Fault Signals Control Signals FLT1 FLT2 OUT 1 VOUT1 OUT 2 VOUT2 GND Pad 150 mF x 2 EN1 or EN1 EN2 or EN2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6 7.1 7.2 7.3 7.4 7.5 7.6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 7 Electrical Characteristics: TJ = TA = 25°C................. 7 Electrical Characteristics: –40°C ≤ (TJ = TA) ≤ 125°C ......................................................................... 8 7.7 Typical Characteristics ............................................ 10 8 9 Parameter Measurement Information ................ 14 Detailed Description ............................................ 16 9.1 Overview ................................................................. 16 9.2 Functional Block Diagram ....................................... 16 9.3 Feature Description................................................. 17 9.4 Device Functional Modes........................................ 18 10 Application and Implementation........................ 19 10.1 Application Information.......................................... 19 10.2 Typical Application ................................................ 19 11 Power Supply Recommendations ..................... 21 11.1 Self-Powered and Bus-Powered Hubs ................. 21 11.2 Low-Power Bus-Powered and High-Power BusPowered Functions .................................................. 21 12 Layout................................................................... 21 12.1 Layout Guidelines ................................................. 21 12.2 Layout Example .................................................... 21 12.3 Power Dissipation and Junction Temperature ...... 22 13 Device and Documentation Support ................. 23 13.1 13.2 13.3 13.4 13.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 14 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (January 2013) to Revision H • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Changes from Revision F (November 2012) to Revision G Page • Changed device TPS2062C-2 SON-8 packages From: Preview To: Active.......................................................................... 4 • Changed devices TPS2066C-2, and TPS2064C-2 MSOP-8 package From: Preview To: Active ......................................... 4 Changes from Revision E (August 2012) to Revision F Page • Changed Feature from: Rated Currents of 1 A, 1.5 A, 2 A to: Rated Currents of 0.5 A, 1 A, 1.5 A, 2 A .............................. 1 • Changed Feature from: Output Discharge When Disabled to: Selected parts with (TPS20xxC) and without (TPS20xxC-2) Output Discharge ............................................................................................................................................ 1 • Added TPS2052C, TPS2062C-2, TPS2064C-2, and TPS2066C-2 devices to Table 1......................................................... 4 • Added TPS2052C, TPS2062C-2, TPS2064C-2, and TPS2066C-2 devices to Table 2......................................................... 4 • Added TPS2052C, TPS2062C-2, TPS2064C-2, and TPS2066C-2 devices to RECOMMENDED OPERATING CONDITIONS table ................................................................................................................................................................ 6 • Added TPS2052C and TPS2066C-2 devices to rDS(on)........................................................................................................... 8 • Added the TPS2052C and TPS2064C-2 devices to IOS ......................................................................................................... 8 • Added Leakage current to Electrical Characteristics table..................................................................................................... 8 • Added text to the SOFTSTART, REVERSE BLOCKING AND DISCHARGE OUTPUT section.......................................... 18 • Added last paragraph in the DISCHARGE OUTPUT section............................................................................................... 18 2 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 Changes from Revision D (July 2012) to Revision E Page • Changed devices TPS2002C and TPS2003C SON-10 package From: Preview To: Active ................................................. 4 • Changed the IOS current limit values for TPS2002C and 03C (2 A)....................................................................................... 8 • Corrected Note 2 reference in the Electrical Characteristics table......................................................................................... 9 Changes from Revision C (June 2012) to Revision D • Page Changed the Device Information table, Package Devices and Marking columns.................................................................. 4 Changes from Revision B (March 2012) to Revision C Page • Changed devices TPS2062C and TPS2066C SOIC-8 package From: Preview To: Active .................................................. 4 • Changed the TPS2062C and 66C rDS(on) D package TYP value From: 84 to 90 mΩ ............................................................ 8 Changes from Revision A (March 2012) to Revision B • Page Changed device TPS2060C MSOP-8 package From: Preview To: Active ............................................................................ 4 Changes from Original (October 2011) to Revision A Page • Changed devices TPS2062C and TPS2066C MSOP-8 package From: Preview to Active................................................... 4 • Changed the IOS current limit values for TPS2062C/66C (1 A).............................................................................................. 8 Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 3 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com 5 Device Comparison Table Table 1. Devices STATUS DEVICES RATED CURRENT MSOP-8 (PowerPad™) SOIC-8 SON-8 VSON-10 TPS2052C 0.5 A Active — — — TPS2062C TPS2066C 1A Active and Active Active and Active — — TPS2062C-2 TPS2066C-2 1A — and Active — Active and — — TPS2060C TPS2064C 1.5 A Active and Active — — — TPS2064C-2 1.5 A Active — — — TPS2002C TPS2003C 2A — — — Active and Active Table 2. Device Information 4 PART NUMBER MAXIMUM OPERATING CURRENT ENABLE OUTPUT DISCHARGE TPS2052C 0.5 High Y TPS2062C 1 Low Y TPS2062C-2 1 Low N TPS2066C 1 High Y TPS2066C-2 1 High N TPS2060C 1.5 Low Y TPS2064C 1.5 High Y TPS2064C-2 1.5 High N TPS2002C 2 Low Y TPS2003C 2 High Y Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 6 Pin Configuration and Functions DGN Package 8-Pin MSOP Top View GND IN EN1 or EN1 EN2 or EN2 1 2 3 4 PAD DRC Package 10-Pin VSON Top View 8 7 6 5 FLT1 OUT1 OUT2 FLT2 GND IN IN EN1 or EN1 EN2 or EN2 D Package 8-Pin SOIC Top View GND IN EN1 or EN1 EN2 or EN2 8 7 6 5 1 2 3 4 1 2 3 4 5 PAD 10 9 8 7 6 FLT1 OUT1 OUT 2 NC FLT2 DRB Package 8-Pin SON Top View FLT1 OUT1 OUT2 FLT2 GND IN EN1 or EN1 EN2 or EN2 1 2 3 4 PAD 8 7 6 5 FLT1 OUT1 OUT2 FLT2 Pin Functions PIN NAME TYPE (1) DESCRIPTION MSOP SOIC VSON SON GND 1 1 1 1 GND IN 2 2 2, 3 2 I Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to GND close to the IC 3 (2) 3 (3) 4 (4) — (5) (6) (7) — I Enable input channel 1, logic high turns on power switch I Enable input channel 1, logic low turns on power switch I Enable input channel 2, logic high turns on power switch 4 I Enable input channel 2, logic low turns on power switch EN1 – – – Ground connection – (2) – (3) – (4) 3 (5) 3 (6) 4 (7) 4 (2) 4 (3) 5 (4) — (5) (6) – (7) — – (2) – (3) – (4) 4 (5) 4 (6) 5 (7) FLT2 5 5 6 5 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on channel 2 NC — — 7 — O No connect – leave floating OUT2 6 6 8 6 O Power-switch output channel 2, connected to load OUT1 7 7 9 7 O Power-switch output channel 1, connected to load FLT1 8 8 10 8 O Active-low open-drain output, asserted during over-current, or overtemperature conditions on channel 1 PAD — PAD — GND EN1 EN2 EN2 PowerPAD™ (1) (2) (3) (4) (5) (6) (7) – – 3 Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect PAD to GND plane as a heatsink. I = Input, O = Output, GND = Ground Applies to TPS2052C, TPS2066C, TPS2066C-2, TPS2064C, and TPS2064C-2 Applies to TPS2066C Applies to TPS2003C Applies to TPS2062C and TPS2060C Applies to TPS2062C Applies to TPS2002C Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 5 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT –0.3 6 V Voltage range from IN to OUT –6 6 V Maximum junction temperature, TJ Internally limited °C Voltage range on IN, OUTx, ENx or ENx, FLTx (4) Storage temperature, Tstg (1) (2) (3) (4) –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute maximum ratings apply over recommended junction temperature range. All voltages are with respect to GND unless otherwise noted. See Input and Output Capacitance. 7.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V IEC 61000-4-2, contact discharge (3) ±8000 IEC 61000-4-2, air-gap discharge (3) ±15000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. VOUT was surged on a PCB with input and output bypassing per Figure 22 (except input capacitor was 22 µF) with no device failure. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN Input voltage, IN VEnable Input voltage, ENx or ENx NOM MAX 4.5 5.5 0 5.5 TPS2052C IOUTx Continuous output current, OUTx TPS2062C, TPS2062C-2, TPS2066C, and TPS2066C-2 1 Operating junction temperature Sink current into FLTx 6 Submit Documentation Feedback A 1.5 TPS2002C and TPS2003C IFLTx V 0.5 TPS2060C, TPS2064C, and TPS2064C-2 TJ UNIT 2 –40 125 °C 0 5 mA Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 7.4 Thermal Information THERMAL METRIC (1) (2) TPS2052C TPS2062C TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2062C TPS2066C DGN (MSOP) D (SOIC) DRB (SON) DRC (VSON) TPS2062C-2 TPS2002C TPS2003C UNIT 8 PINS 8 PINS 8 PINS 10 PINS RθJA Junction-to-ambient thermal resistance 57.2 129.9 50.8 45.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 110.5 83.5 60.3 58 °C/W RθJB Junction-to-board thermal resistance 60.7 70.4 26.3 21.1 °C/W ψJT Junction-to-top characterization parameter 7.8 36.6 2.1 1.9 °C/W ψJB Junction-to-board characterization parameter 24 66.9 26.5 21.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 14.3 n/a 9.8 9.1 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. 7.5 Electrical Characteristics: TJ = TA = 25°C VIN = 5 V, VENx = VIN or VENx = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT POWER SWITCH rDS(on) On-resistance TPS2052C (0.5 A) DGN 70 84 TPS2052C (0.5 A) –40°C ≤ (TJ, TA) ≤ 85°C DGN 70 95 TPS2062C, 66C, and 66C-2 (1 A) DGN 70 84 TPS2062C, 66C, and 66C-2 (1 A), –40°C ≤ (TJ, TA) ≤ 85°C DGN 70 95 TPS2062C and 66C (1 A) D 90 108 TPS2062C and 66C (1 A) –40°C ≤ (TJ, TA) ≤ 85°C D 90 122 TPS2062C-2 (1 A) DRB 73 87 TPS2062C-2 (1 A) –40°C ≤ (TJ, TA) ≤ 85°C DRB 73 101 TPS2060C, 64C, and 64C-2 (1.5 A) 70 84 TPS2060C, 64C, and 64C-2 (1.5 A) –40°C ≤ (TJ, TA) ≤ 85°C 70 95 TPS2002C and 03C (2 A) 70 84 TPS2002C and 03C (2 A) –40°C ≤ (TJ, TA) ≤ 85°C 70 95 mΩ CURRENT LIMIT IOS Current-limit (see Figure 28) TPS2052C (0.5 A) 0.75 1 1.25 TPS2062C, 62C-2, 66C, and 66C-2 (1 A) 1.28 1.61 1.94 TPS2060C, 64C, and 64C-2 (1.5 A) 1.83 2.29 2.75 TPS2002C and 03C (2 A) 2.55 3.15 3.77 A SUPPLY CURRENT ISD Supply current, switch disabled I(OUTx) = 0 mA 0.01 1 IS1E Supply current, single switch enabled I(OUTx) = 0 mA 60 75 IS2E Supply current, both switches enabled I(OUTx) = 0 mA 100 120 Leakage current VOUT = 0 V, VIN = 5.5 V, disabled, measured IVIN 0.05 1 Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured I(OUTx) 0.15 1 ILKG (1) TPS20xxC-2 µA Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 7 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com Electrical Characteristics: TJ = TA = 25°C (continued) VIN = 5 V, VENx = VIN or VENx = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT 400 470 600 Ω OUTPUT DISCHARGE Output pulldown resistance (2) RPD (2) VIN = VOUTx = 5 V, disabled TPS20xxC These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty. 7.6 Electrical Characteristics: –40°C ≤ (TJ = TA) ≤ 125°C (1) 4.5 V ≤ VIN ≤ 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP (2) MAX UNIT POWER SWITCH rDS(on) On-resistance TPS2052C (0.5 A) DGN 70 112 TPS2062C, 66C, and 66C-2 (1 A) DGN 70 112 TPS2062C and 66C (1 A) D 90 135 TPS2062C-2 (1 A) DRB 73 115 TPS2060C, 64C, and 64C-2 (1.5 A) DGN 70 112 TPS2002C and 03C (2 A) DRC 70 112 mΩ ENABLE INPUT (ENx or ENx) VIH ENx (ENx), High-level input voltage VIL ENx (ENx), Low-level input Voltage 4.5 V ≤ VIN ≤ 5.5 V 2 0.8 V Hysteresis VIN = 5 V Leakage current VENx = 5.5 V or 0 V, VENx = 0 V or 5.5 V –1 0.14 0 1 µA 1.4 1.9 2.4 ms ton Turnon time (3) VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or ENx ↓ (see Figure 25, Figure 26, and Figure 23) 1 A, 1.5 A, 2 A Rated toff Turnoff time (3) VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or EN ↓ (see Figure 25, Figure 26, and Figure 23) 1 A, 1.5 A, 2 A Rated 1.95 2.60 3.25 ms tr Rise time, output CL = 1 µF, RL = 100 Ω (see Figure 24) 1 A, 1.5 A, 2 A Rated 0.58 0.82 1.15 ms tf Fall time, output CL = 1 µF, RL = 100 Ω (see Figure 24) 1 A, 1.5 A, 2 A Rated 0.33 0.47 0.66 ms (3) (3) CURRENT LIMIT TPS2052C (0.5 A) IOS Current-limit (see Figure 28) tIOS Short-circuit response time 0.7 1 1.3 TPS2062C, 62C-2, 66C, and 66C-2 (1 A) 1.12 1.61 2.10 TPS2060C, 64C, and 64C-2 (1.5 A) 1.72 2.29 2.86 TPS2002C and 03C (2 A) 2.35 3.15 3.95 VIN = 5 V (see Figure 27), One-half full load → R(SHORT) = 50 mΩ, Measure from application to when current falls below 120% of final value 2 A µs SUPPLY CURRENT ISD Supply current, switch disabled Standard conditions, I(OUTx) = 0 mA IS1E Supply current, single switch enabled Standard conditions, I(OUTx) = 0 mA 90 IS2E Supply current, both switches enabled Standard conditions, I(OUTx) = 0 mA 150 Leakage current VOUT = 0 V, VIN = 5.5 V, disabled, measured IVIN Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured I(OUTx) ILKG 0.01 TPS20xxC-2 10 µA 0.05 0.20 UNDERVOLTAGE LOCKOUT UVLO Low-level input voltage, IN Hysteresis, IN (1) (2) (3) 8 VIN rising 3.4 4.0 0.14 V V Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature. Typical values are at 5 V and 25°C. These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 Electrical Characteristics: –40°C ≤ (TJ = TA) ≤ 125°C(1) (continued) 4.5 V ≤ VIN ≤ 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP (2) MAX UNIT FLTx Output low voltage, FLTx I(FLTx) = 1 mA Off-state leakage V(FLTx) = 5.5 V FLTx deglitch (3) FLTx overcurrent assertion and deassertion 7 10 0.2 V 1 µA 13 ms OUTPUT DISCHARGE Output pulldown resistance (3) VIN = 5 V, VOUT = 5 V, disabled TPS20xxC 300 470 800 VIN = 4 V, VOUT = 5 V, disabled TPS20xxC 350 560 1200 Ω THERMAL SHUTDOWN Junction thermal shutdown threshold Hysteresis Copyright © 2011–2015, Texas Instruments Incorporated In current limit 135 Not in current limit 155 °C 20 Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C °C 9 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com 7.7 Typical Characteristics 8 8 VIN = 5 V, CLx = 1 µF, RLoadx = 5 Ω, TPS2062C 6 6 4 ENx (V) 4 ENx (V) VIN = 5 V, CLx = 1 µF, RLoadx = 5 Ω, TPS2062C ENx OUTx 2 OUTx 2 ENx 0 0 −2 −3m −2m −1m 0 1m 2m Time (s) 3m 4m −2 −3m 5m Figure 1. TPS2062C Turnon Delay and Rise Time With 1-μF Load 8 −1m 0 1m 2m Time (s) 3m 4m 5m Figure 2. TPS2062C Turnoff Delay and Fall Time With 1-μF Load 8 VIN = 5 V, CLx = 150 µF, RLoadx = 5 Ω, TPS2062C 6 VIN = 5 V, CLx = 150 µF, RLoadx = 5 Ω, TPS2062C 6 ENx 4 ENx (V) 4 ENx (V) −2m OUTx 2 OUTx 2 ENx 0 0 −2m −1m 0 1m 2m Time (s) 3m 4m −2 −3m 5m Figure 3. TPS2062C Turnon Delay and Rise Time With 150-μF Load ENx ,OUTx , FLTx (V) 6 FLTx 4 2 5 2.0 OUTx 1.0 OUTx Current 0.0 0 10m 20m Time (s) 30m 40m −1.0 50m Figure 5. TPS2062C Enable Into Short 10 5.0 3.0 ENx −4 −6 −10m 7 4.0 0 −2 6.0 Submit Documentation Feedback ENx ,OUTx , FLTx (V) VIN = 5 V, CLx = 150 µF, RLoadx = 0 Ω, TPS2062C −1m 0 1m 2m Time (s) 3m 4m 5m Figure 4. TPS2062C Turnoff Delay and Fall Time With 150-μF Load OUTx Current (A) 8 −2m 3.5 VIN = 5 V, RLoadx = 5.0 Ω, TPS2062C 3.0 3 2.5 OUTx 1 −1 FLTx ENx 2.0 1000 µF 220 µF −3 1.0 −5 150 µF −7 −9 −2m 1.5 0 2m 0.5 680 µF 4m Time (s) OUTx Current (A) −2 −3m 0.0 6m 8m −0.5 10m Figure 6. TPS2062C In-rush Current With Different Load Capacitance Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 Typical Characteristics (continued) VIN = 5 V, CLx = 150 µF, RLoadx = 5 Ω, TPS2062C 5.0 6 FLTx 3.0 OUTx 0 2.0 −2 1.0 IOUTx −4 −4m 5.0 0 4m 4.0 2 3.0 FLTx 0 2.0 OUTx −2 1.0 IOUTx −4 0.0 0.0 −6 −4m −1.0 12m 8m 4 OUTx Current (A) 4.0 2 −6 −8m 6.0 VIN = 5 V, CLx = 150 µF, RLoadx = 5 Ω, TPS2062C VIN VIN 4 8 FLTx, OUTx, VIN (V) FLTx, OUTx, VIN (V) 6 6.0 OUTx Current (A) 8 0 4m Time (s) 8m 12m −1.0 16m Time (s) Figure 7. TPS2062C Power Up – Enabled Figure 8. TPS2062C Power Down – Enabled 4.2 8 VIN = 5 V, CLx = 150 μF, RLoadx = 2.0 Ω, TPS2062C 3.6 6 FLTx ENx, OUTx, FLTx (V) ENx 3.0 4 2 2.4 OUTx 1.8 0 1.2 −2 IOUTx −4 0.6 0.0 −6 −8 −4m −2m 0 2m 4m 6m Time (s) 8m 10m 12m −0.6 14m Figure 9. TPS2062C Enable With 2-Ω Load Figure 10. TPS2062C Enable With 1-Ω Load VIN = 5 V, CLx = 150 μF, RLoadx = 10 Ω, TPS2062C VIN = 5 V, CLx = 150 μF, RLoadx = 0 Ω, TPS2062C 6 3.5 8 4.2 8 3.6 6 3.0 4 3.0 4 2 ENx 2.4 1.8 0 −2 OUTx 1.2 IOUTx −4 0.6 0.0 −6 −8 −8m −4m 0 4m 8m −0.6 12m 16m 20m 24m 28m 32m Time (s) Figure 11. TPS2062C Enable and Disable into Output Short Copyright © 2011–2015, Texas Instruments Incorporated ENx, OUTx, FLTx (V) ENx, OUTx, FLTx (V) FLTx 2.5 OUTx FLTx 2 1.5 0 ENx −2 1.0 IOUTx −4 0.5 0.0 −6 −8 −2m 2.0 0 2m 4m 6m −0.5 8m 10m 12m 14m 16m 18m Time (s) Figure 12. TPS2062C Enable and Disable into 10-Ω Load Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 11 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com Typical Characteristics (continued) 12.0 8 10.0 6 VIN = 5 V, CLx = 150 μF, RLoadx = 0 Ω, TPS2064C FLTx ENx 2 6.0 OUTx 4.0 0 2 8m 42 30 OUTx (V) OUTx 24 3 18 12 1 6 1μ 2μ −3m 3μ 0 1m Time (s) 2m 3m 4m −1 5m 10.0 8.0 4 ENx 2 6.0 OUTx 4.0 0 −2 2.0 IOUTx 0.0 0 −4 −6 −6 −6m −4m −2m 0 2m 4m 6m Time (s) 8m −2.0 10m 12m 14m Figure 16. TPS2003C Enable into Short 7 3.4 VIN = 5 V, CLx = 150 μF, RLoadx = 2.5 Ω, TPS2003C 2.0 A rated 3.2 6 6 −1m FLTx Figure 15. TPS2064C Short Applied 8 −2m 12.0 6 ENx, OUTx, FLTx (V) IOUTx 0 Time (s) 0 VIN = 5 V, CLx = 150 μF, RLoadx = 0 Ω, TPS2003C 36 −1μ 1 8 VIN = 5 V, CLx = 0 μF, RLoadx = 50 mΩ, TPS2064C −2μ 2 Figure 14. TPS2064C Enable into 3.3 Ω and 150-μF Laod 7 −1 −3μ −2 −8 −4m −2.0 10m 12m 14m Figure 13. TPS2064C Enable into Short 5 3 −6 0.0 4m 6m Time (s) 0 IOUTx −4 2m 4 ENx −4 IOUTx 0 5 OUTx 2.0 −2 −6 −6m −4m −2m 6 4 8.0 4 OUTx, ENx (V) ENx, OUTx, FLTx (V) 6 7 VIN = 5 V, CLx = 150 µF, RLoadx = 3.3 Ω, TPS2064C OUTx Current (A) 8 VIN = 5.5 V 3 ENx 5 OUTx 2.6 2 4 0 3 −2 2 2 1 1.8 −4 −8 −3m −2m −1m 0 1m 2m 3m Time (s) 0 4m 5m 6m −1 7m Figure 17. TPS2003C Enable into 2.5 Ω and 150-μF Load Submit Documentation Feedback 1.5 A rated 2.4 2.2 1.0 A rated 1.6 IOUTx −6 12 2.8 IOS (A) OUTx, ENx (V) 4 1.4 1.2 −40 −20 0 20 40 60 80 Junction Temperature (°C) 100 120 Figure 18. Current Limit (IOS) vs Temperature Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 Typical Characteristics (continued) 100 2.5 VIN = 5 V VIN = 5 V 2 A rated 2 80 1.5 ISD (μA) RDSON (mΩ) 90 1.0 A rated 1 A rated 70 60 1.5 A rated 2.0 A rated 1 0.5 1.5 A rated 50 0 40 −40 −20 0 20 40 60 80 Junction Temperature (°C) 100 −0.5 −40 120 Figure 19. Input - output Resistance (RDS(ON)) vs Temperature −20 0 20 40 60 80 Junction Temperature (°C) 100 120 Figure 20. Supply Current (Device Disable) - ISD vs Temperature Supply Current − Device Enable (μA) 130 VIN = 5 V 1.0 A rated(IS2E) 120 110 2.0 A rated(IS2E) 100 90 1.5 A rated(IS2E) 2.0 A rated(IS1E) 80 1.5 A rated(IS1E) 70 60 50 −40 1.0 A rated(IS1E) −20 0 20 40 60 80 Junction Temperature (°C) 100 120 Figure 21. Supply Current (Enable) - ISE vs Temperature Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 13 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com 8 Parameter Measurement Information IOUT1 IOUT2 0.1 PF VIN IN 3.01 k: VOUT2 RLoad1 FLT1 FLT2 Fault Signals VOUT1 OUT1 OUT2 3.01 k: GND Pad CL1 RLoad2 CL2 EN1 or EN1 Control Signals EN2 or EN2 Figure 22. Test Circuit for System Operation for the Typical Characteristics OUTx RL CL Figure 23. Output Rise / Fall Test Load 90% tr tf VOUT 10% Figure 24. Power-On and Off Timing VEN 50% 50% ton toff 90% VOUT 10% Figure 25. Enable Timing, Active High Enable VEN 50% 50% toff ton 90% VOUT 10% Figure 26. Enable Timing, Active Low Enable 120% x IOS IOUT IOS 0A tIOS Figure 27. Output Short Circuit Parameters 14 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 VIN Decreasing Load Slope = -rDS(on) VOUT Resistance 0V 0A IOUT IOS Figure 28. Output Characteristic Showing Current Limit Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 15 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com 9 Detailed Description 9.1 Overview The TPS20xxC and TPS20xxC-2 are dual current-limited, power-distribution switches providing between 0.5 A and 2 A of continuous load current in 5-V circuits. These parts use N-channel MOSFETs for low resistance, maintaining output voltage load regulation. They are designed for applications where short circuits or heavy capacitive loads are encountered. Device features include UVLO, ON/OFF control (Enable), reverse blocking when disabled, output discharge when TPS20xxC disabled, overcurrent protection, overtemperature protection, and deglitched fault reporting. They are pin for pin with existing TI Switch Portfolio. 9.2 Functional Block Diagram ! " # $ # % ! " # % $ # % % Figure 29. TPS20xxC Functional Block Diagram 16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 Functional Block Diagram (continued) CS IN OUT1 Current Sense Charge Pump Current Limit EN1 or Driver EN1 FLT1 UVLO OTSD Thermal Sense UVLO 10-ms Deglitch CS OUT2 Current Sense Current Limit EN2 or Driver UVLO EN2 FLT2 OTSD GND Thermal Sense 10-ms Deglitch Figure 30. TPS20xxC-2 Functional Block Diagram 9.3 Feature Description 9.3.1 Undervoltage Lockout (UVLO) The undervoltage lockout (UVLO) circuit disables the power switch when the input voltage is below the UVLO threshold. Built-in hysteresis prevents unwanted ON/OFF cycling due to input voltage drop from large current surges. FLTx is high impedance when the TPS20xxC and TPS20xxC-2 dual are in UVLO. 9.3.2 Enable (ENx or ENx) The logic input of ENx or ENx disables all of the internal circuitry while maintaining the power switch OFF. The supply current of the device can be reduced to less than 1 µA when both switches are disabled. A logic low input on ENx or a logic high input on ENx enables the driver, control circuits, and power switch of corresponding channel. The ENx or ENx input voltage is compatible with both TTL and CMOS logic levels. The FLTx is immediately cleared and the output discharge circuit is enabled when the device is disabled. 9.3.3 Deglitched Fault Reporting FLTx is an open-drain output that asserts (active low) during an overcurrent or overtemperature condition on each corresponding channel. The FLTx output remains asserted until the fault condition is removed or the channel is disabled. The TPS20xxC and TPS20xxC-2 dual eliminates false FLTx reporting by using internal delay circuitry after entering or leaving an overcurrent condition. The deglitch time is typically 10 ms. This ensures that FLTx is not accidentally asserted under overcurrent conditions with a short time, such as starting into a heavy capacitive load. Overtemperature conditions are not deglitched. The FLTx pin is high impedance when the device is disabled and in undervoltage lockout (UVLO). The fault circuits are independent so that another channel continues to operate when one channel is in a fault condition. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 17 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) 9.3.4 Overcurrent Protection The TPS20xxC and TPS20xxC-2 dual responds to overloads by limiting each channel output current to the static IOS levels shown in Electrical Characteristics: TJ = TA = 25°C. When an overload condition is present, the device maintains a constant current (IOS) and reduces the output voltage accordingly, with the output voltage falling to (IOS × RSHORT). Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before voltage is applied to IN. The device senses over-current and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant a short-circuit occurs, high currents may flow for several microseconds (tIOS) before the current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit has responded. In the third condition, the load is increased gradually beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached. The devices are capable of delivering current up to the current-limit threshold without damage. Once the threshold is reached, the device switches into constant-current mode. For all of the above three conditions, the device may begin thermal cycling if the overcurrent condition persists. 9.3.5 Overtemperature Protection The TPS20xxC and TPS20xxC-2 dual includes per channel overtemperature protection circuitry, which activates at 135°C (minimum) junction temperature while in current limit. There is an overall thermal shutdown of 155°C (minimum) junction temperature when the TPS20xxC and TPS20xxC-2 dual are not in current limit. The device remains off until the junction temperature cools 20°C and then restarts. Thermal shutdown may occur during an overload due to the relatively large power dissipation [(VIN – VOUT) × IOS] driving the junction temperature up. The power switch cycles on and off until the fault is removed. This topology allows one channel to continue normal operation even if the other channel is in an overtemperature condition. 9.3.6 Softstart, Reverse Blocking and Discharge Output The power MOSFET driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start functionality. The TPS20xxC and TPS20xxC-2 dual power switch will block current from OUT to IN when turned off by the UVLO or disabled. The TPS20xxC dual includes an output discharge function on each channel. A 470 Ω (typical) discharge resistor will dissipate stored charge and leakage current on OUTx when the device is in UVLO or disabled. However as this circuit is biased from IN, the output discharge will not be active when IN voltage is close to 0 V. The TPS20xxC-2 does not have this function. The output is be controlled by an external loadings when the device is in ULVO or disabled. 9.4 Device Functional Modes There are no other functional modes. 18 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-tomedium bandwidth PC peripherals (for example, keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: • Hosts or self-powered hubs (SPH) • Bus-powered hubs (BPH) • Low-power, bus-powered functions • High-power, bus-powered functions • Self-powered functions Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS20xxC and TPS20xxC-2 can provide power distribution solutions to many of these device classes. 10.2 Typical Application IOUT1 IOUT2 0.1 PF VIN IN 3.01 k: 3.01 k: Fault Signals FLT1 FLT2 VOUT1 OUT1 OUT2 VOUT2 RLoad1 GND Pad CL1 RLoad2 CL2 EN1 or EN1 Control Signals EN2 or EN2 Figure 31. Typical Application Circuit Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 19 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com Typical Application (continued) 10.2.1 Design Requirements Table 3 shows the design requirements for the typical application. Table 3. Design Parameters PARAMETER VALUE Input voltage 5V Output voltage 1 5V Output voltage 2 5V Current limit 1A 10.2.2 Detailed Design Procedure 10.2.2.1 Input and Output Capacitance Input and output capacitance improves the performance of the device. For all applications, TI recommends placing a 0.1-µF or greater ceramic bypass capacitor between IN and GND as close as possible to the device for local noise de-coupling. The actual capacitance should be optimized for the particular application. This precaution reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the input to reduce the overshoot voltage from exceeding the absolute maximum voltage of the device during heavy transients. A 120-µF minimum output capacitance is required when implementing USB standard applications. Typically this uses a 150-µF electrolytic capacitor. If the application does not require 120 µF of output capacitance, a minimum of 10-µF ceramic capacitor on the output is recommended to reduce the transient negative voltage on OUTx pin caused by load inductance during a short circuit. The transient negative voltage should be less than 1.5 V for 10 µs. 10.2.3 Application Curves 8 3.5 8 VIN = 5 V, CLx = 1 µF, RLoadx = 5 Ω, TPS2062C VIN = 5 V, CLx = 150 μF, RLoadx = 10 Ω, TPS2062C 3.0 6 ENx, OUTx, FLTx (V) ENx (V) 6 4 ENx OUTx 2 2.5 4 OUTx FLTx 2 2.0 1.5 0 ENx −2 1.0 IOUTx −4 0.5 0 0.0 −6 −2 −3m −2m −1m 0 1m 2m Time (s) 3m 4m Figure 32. TPS2062C Turnon Delay and Rise Time With 1-μF Load 20 Submit Documentation Feedback 5m −8 −2m 0 2m 4m 6m −0.5 8m 10m 12m 14m 16m 18m Time (s) Figure 33. TPS2062C Enable/Disable into 10-Ω Load Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 11 Power Supply Recommendations 11.1 Self-Powered and Bus-Powered Hubs A Self-Powered Hub (SPH) has a local power supply that powers embedded functions and downstream ports. This power supply must provide between 4.75 V to 5.25 V to downstream facing devices under full-load and noload conditions. SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. A Bus-Powered Hub (BPH) obtains all power from an upstream port and often contains an embedded function. It must power up with less than 100 mA. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This is accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than 100 mA. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and it is limited to 500 mA from an upstream port. 11.2 Low-Power Bus-Powered and High-Power Bus-Powered Functions Both low-power and high-power bus-powered functions obtain all power from upstream ports. Low-power functions always draw less than 100 mA; high-powered functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 µF at power up, the device must implement inrush current limiting. 12 Layout 12.1 Layout Guidelines • • • Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a lowinductance trace. When large transient currents are expected on the output, TI recommends placing a high-value electrolytic capacitor and a 100-nF bypass capacitor on the output pin. The PowerPAD should be directly connected to PCB ground plane using wide and short copper trace. 12.2 Layout Example GND 1 8 FAULT1 IN 2 7 OUT1 EN1 3 6 OUT2 EN2 4 5 FAULT2 Power Ground Figure 34. Layout Recommendation Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 21 TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 www.ti.com 12.3 Power Dissipation and Junction Temperature It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS20xxC and TPS20xxC-2 dual. The system designer can control choices of package, proximity to other power dissipating devices, and printed circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors such as airflow and maximum ambient temperature are often determined by system considerations. Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. The following procedure requires iteration because power loss is due to the two internal MOSFETs 2 × I2 × rDS(on), and rDS(on) is a function of the junction temperature. As an initial estimate, use the rDS(on) at 125°C from the typical characteristics, and the preferred package thermal resistance for the preferred board construction from the thermal parameters section. TJ = TA + [2 × IOUT2 × rDS(on) × θJA] where • • • • • IOUT = rated OUT pin current (A) rDS(on) = Power switch on-resistance at an assumed TJ (Ω) TA = Maximum ambient temperature (°C) TJ = Maximum junction temperature (°C) θJA = Thermal resistance (°C/W) (1) If the calculated TJ is substantially different from the original assumption, look up a new value of rDS(on) and recalculate. If the resulting TJ is not less than 125°C, try a PCB construction and/or package with lower θJA. 22 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2 TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C www.ti.com SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS2052C Click here Click here Click here Click here Click here TPS2062C Click here Click here Click here Click here Click here TPS2062C-2 Click here Click here Click here Click here Click here TPS2066C Click here Click here Click here Click here Click here TPS2066C-2 Click here Click here Click here Click here Click here TPS2060C Click here Click here Click here Click here Click here TPS2064C Click here Click here Click here Click here Click here TPS2064C-2 Click here Click here Click here Click here Click here TPS2002C Click here Click here Click here Click here Click here TPS2003C Click here Click here Click here Click here Click here 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks PowerPad, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C 23 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS2002CDRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ Samples TPS2002CDRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ Samples TPS2003CDRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 VRFQ Samples TPS2003CDRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 VRFQ Samples TPS2052CDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYNI Samples TPS2052CDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYNI Samples TPS2060CDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRAQ Samples TPS2060CDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRAQ Samples TPS2062CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2062C Samples TPS2062CDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRBQ Samples TPS2062CDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRBQ Samples TPS2062CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2062C Samples TPS2062CDRBR-2 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PYVI Samples TPS2062CDRBT-2 ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PYVI Samples TPS2064CDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRCQ Samples TPS2064CDGN-2 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYTI Samples TPS2064CDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRCQ Samples TPS2064CDGNR-2 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYTI Samples TPS2066CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2066C Samples TPS2066CDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 VRDQ Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Aug-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS2066CDGN-2 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYUI Samples TPS2066CDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRDQ Samples TPS2066CDGNR-2 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYUI Samples TPS2066CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2066C Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of