D−8
DGN−8
TPS2062-1
TPS2065-1
TPS2066-1
D−16
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009
CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
The TPS206x-1 power-distribution switches are
intended for applications where heavy capacitive
loads and short-circuits are likely to be encountered.
This device incorporates 70-mΩ N-channel MOSFET
power switches for power-distribution systems that
require multiple power switches in a single package.
Each switch is controlled by a logic enable input.
Gate drive is provided by an internal charge pump
designed to control the power-switch rise times and
fall times to minimize current surges during switching.
The charge pump requires no external components
and allows operation from supplies as low as 2.7 V.
APPLICATIONS
•
•
TPS2062-1/TPS2066-1
DAND DGN PACKAGE
(TOPVIEW)
TPS2065-1
DGN PACKAGE
(TOPVIEW)
Output Discharge Function
70-mΩ High-Side MOSFET
1-A Continuous Current
Thermal and Short-Circuit Protection
Accurate Current Limit
(1.1 A min, 1.9 A max)
Operating Range: 2.7 V to 5.5 V
0.6-ms Typical Rise Time
Undervoltage Lockout
Deglitched Fault Report (OC)
No OC Glitch During Power Up
1-A Maximum Standby Supply Current
Ambient Temperature Range: -40°C to 85°C
ESD Protection
Heavy Capacitive Loads
Short-Circuit Protections
These switches provide a discharge function that
provides a controlled discharge of the output voltage
stored on the output capacitor.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When
continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction
temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains
off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1.5 A
typically.
GENERAL SWITCH CATALOG
33 mΩ, single TPS201xA 0.2 A − 2 A
TPS202x
TPS203x
80 mΩ, single TPS2014
TPS2015
TPS2041B
TPS2051B
TPS2045
TPS2055
TPS2061
TPS2065
TPS2042B
TPS2052B
TPS2046
TPS2056
TPS2062
TPS2066
TPS2060
TPS2064
80 mΩ, dual
0.2 A − 2 A
0.2 A − 2 A
600
1A
500
500
250
250
1A
1A
260 mΩ
mA
mA
mA
mA
mA
IN1
OUT
IN2
1.3 Ω
500 mA
500 mA
250 mA
250 mA
1A
1A
1.5 A
1.5 A
TPS2100/1
IN1 500 mA
IN2 10 mA
TPS2102/3/4/5
IN1
500 mA
IN2
100 mA
80 mΩ, dual
TPS2080
TPS2081
TPS2082
TPS2090
TPS2091
TPS2092
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
80 mΩ, triple
TPS2043B
TPS2053B
TPS2047
TPS2057
500
500
250
250
mA
mA
mA
mA
80 mΩ, quad
TPS2044B
TPS2054B
TPS2048
TPS2058
500
500
250
250
mA
mA
mA
mA
80 mΩ, quad
TPS2085
TPS2086
TPS2087
TPS2095
TPS2096
TPS2097
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTION AND ORDERING INFORMATION (1)
TA
ENABLE
RECOMMENDED
MAXIMUM
CONTINUOUS
LOAD CURRENT
TYPICAL
SHORT-CIRCUIT
CURRENT LIMIT
AT 25°C
1A
1.5 A
NUMBER OF
SWITCHES
Active high
–40°C to 85°C
Single
Active low
Active high
(1)
(2)
Dual
PACKAGED
DEVICES (2)
MSOP (DGN)
SOIC(D)
TPS2065DGN-1
TPS2062D-1
TPS2066DGN-1
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2062-1DR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Input voltage range, VI(IN) (2)
–0.3 V to 6 V
Output voltage range, VO(OUT) (2), VO(OUTx)
-0.3 V to 6 V
Input voltage range, VI(EN), VI(EN), VI(ENx), VI(ENx)
–0.3 V to 6 V
Voltage range, VI(OC), VI(OCx)
–0.3 V to 6 V
Continuous output current, IO(OUT), IO(OUTx)
Internally limited
Continuous total power dissipation
See Dissipation Rating Table
Operating virtual junction temperature range, TJ
-40°C to 125°C
Storage temperature range, Tstg
–65°C to 150°C
Human body model MIL-STD-883C
Electrostatic discharge (ESD) protection
(1)
(2)
2
2 kV
Charge device model (CDM)
500 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1
TPS2062-1
TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009
DISSIPATING RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D-8
585.82 mW
5.8582 mW/°C
322.20 mW
234.32 mW
DGN-8
1712.3 mW
17.123 mW/°C
941.78 mW
684.33 mW
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
2.7
5.5
V
Input voltage, VI(EN), VI(EN), VI(ENx), VI(ENx)
0
5.5
V
Continuous output current, IO(OUT), IO(OUTx)
0
1
A
8
mA
125
°C
Input voltage, VI(IN)
Steady state current through discharge. Device disabled, measured through output pin(s)
Operating virtual junction temperature, TJ
-40
UNIT
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 1 A, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V (unless
otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
POWER SWITCH
rDS(on)
tr (2)
Static drain-source on-state resistance,
5-V operation and 3.3-V operation
VI(IN) = 5 V or 3.3 V, IO = 1 A, –40°C ≤ TJ ≤ 125°C
70
135
mΩ
Static drain-source on-state resistance,
2.7-V operation (2)
VI(IN) = 2.7 V, IO = 1 A, -40°C ≤ TJ ≤ 125°C
75
150
mΩ
VI(IN) = 5.5 V
0.6
1.5
VI(IN) = 2.7 V
0.4
Rise time, output
tf (2)
VI(IN) = 5.5 V
Fall time, output
CL = 1 µF, RL = 5 Ω,
TJ = 25°C
VI(IN) = 2.7 V
1
0.05
0.5
0.05
0.5
ms
ENABLE INPUT EN OR EN
VIH
High-level input voltage
2.7 V ≤ VI(IN) ≤5.5 V
VIL
Low-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
Input current
VI(ENx) = 0 V or 5.5 V, VI(ENx) = 0 V or 5.5 V
Turnon time
CL = 100 µF, RL = 5 Ω
3
Turnoff time
CL = 100 µF, RL = 5 Ω
10
II
ton
(3)
toff (3)
2
0.8
-0.5
0.5
V
µA
ms
CURRENT LIMIT
IOS
Short-circuit output current
VI(IN) = 5 V, OUT connected to GND,
device enabled into short-circuit
IOC_TRIP (3)
Overcurrent trip threshold
VI(IN) = 5 V, current ramp (≤ 100 A/s) on OUT
TJ = 25°C
1.1
1.5
1.9
-40°C ≤ TJ ≤ 125°C
1.1
1.5
2.1
2.4
3
A
A
SUPPLY CURRENT (TPS2065-1)
Supply current, low-level output
No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
TJ = 25°C
0.5
1
-40°C ≤ TJ ≤ 125°C
0.5
10
Supply current, high-level output
No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
TJ = 25°C
43
60
-40°C ≤ TJ ≤ 125°C
43
70
Reverse leakage current
VI(OUTx) = 5.5 V, IN = ground (3)
TJ = 25°C
0
Supply current, low-level output
No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
TJ = 25°C
0.5
1
-40°C ≤ TJ ≤ 125°C
0.5
20
Supply current, high-level output
No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
TJ = 25°C
50
70
-40°C ≤ TJ ≤ 125°C
50
90
Reverse leakage current
VI(OUTx) = 5.5 V, IN = ground (3)
TJ = 25°C
0.2
µA
µA
µA
SUPPLY CURRENT (TPS2062-1, TPS2066-1)
(1)
(2)
(3)
µA
µA
µA
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
Not tested in production, specified by design.
Not tested in production, specified by design.
Copyright © 2007–2009, Texas Instruments Incorporated
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3
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 1 A, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V (unless
otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN
2
Hysteresis, IN
2.5
TJ = 25°C
75
V
mV
OVERCURRENT OC1 and OC2
Output low voltage, VOL(OCx)
IO(OCx) = 5 mA
Off-state current (4)
VO(OCx) = 5 V or 3.3 V
OC deglitch (4)
OCx assertion or deassertion
Discharge resistance
VCC = 5 V, disabled, IO = 1 mA
4
8
0.4
V
1
µA
15
ms
100
Ω
THERMAL SHUTDOWN (5)
Thermal shutdown threshold (4)
135
Recovery from thermal shutdown (4)
125
Hysteresis (4)
(4)
(5)
°C
°C
10
°C
Not tested in production, specified by design.
The thermal shutdown only reacts under overcurrent conditions.
DEVICE INFORMATION
Pin Functions
PIN
NAME
I/O
DESCRIPTION
TPS2065-1
TPS2062-1
TPS2066-1
EN
4
–
–
I
Enable input, logic high turns on power switch
EN1
–
3
–
I
Enable input, logic low turns on channel 1
EN2
–
4
–
I
Enable input, logic high turns on channel 2
EN1
–
–
3
I
Enable input, logic high turns on channel 1
EN2
–
–
4
I
Enable input, logic high turns on channel 2
GND
1
1
1
IN
2, 3
2
2
I
Input voltage; connect a 0.1 µF or greater ceramic capacitor from IN to GND
as close to the IC as possible
OC
5
–
–
O
Active-low open-drain output, asserted during over-current
OC1
–
8
8
O
Active-low open-drain output, asserted during over-current for channel 1
OC2
Ground connection
5
5
O
Active-low open-drain output, asserted during over-current for channel 2
OUT
6, 7, 8
–
–
O
Power-switch output
OUT1
–
7
7
O
Power-switch output for channel 1
OUT2
–
6
6
O
Power-switch output for channel 2
4
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1
TPS2062-1
TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009
FUNCTIONAL BLOCK DIAGRAM (TPS2065-1)
(See Note A)
IN
OUT
CS
Charge
Pump
EN
EN
Driver
Discharge
Control
Current
Limit
OC
UVLO
Deglitch
Thermal
Sense
GND
Note A: Current sense
FUNCTIONAL BLOCK DIAGRAM (TPS2062-1 and TPS2066-1)
FUNCTIONAL BLOCK DIAGRAM (TPS2062-1 and TPS2066-1)
OC1
Thermal
Sense
GND
Deglitch
EN1
(See Note B)
Driver
Current
Limit
Charge
Pump
(See Note A)
CS
OUT1
UVLO
EN
Discharge
Control
(See Note A)
IN
OUT2
CS
Charge
Pump
EN
Driver
Current
Limit
Discharge
Control
OC2
EN2
(See Note B)
Thermal
Sense
Deglitch
Note A: Current sense
Note B: Active low (ENx) for TPS2062. Active high (ENx) for TPS2066
Copyright © 2007–2009, Texas Instruments Incorporated
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5
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com
PARAMETER MEASUREMENT INFORMATION
OUT
RL
tf
tr
CL
VO(OUT)
90%
10%
90%
10%
TEST CIRCUIT
50%
VI(EN)
50%
toff
ton
VO(OUT)
50%
VI(EN)
90%
50%
toff
ton
90%
VO(OUT)
10%
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
RL = 5 W,
CL = 1 mF
TA = 255C
VI(EN)
5 V/div
VI(EN)
5 V/div
RL = 5 W,
CL = 1 mF
TA = 255C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 2. Turnon Delay and Rise Time With 1-µF Load
6
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Figure 3. Turnoff Delay and Fall Time With 1-µF Load
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1
TPS2062-1
TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009
PARAMETER MEASUREMENT INFORMATION (continued)
VI(EN)
5 V/div
RL = 5 W,
CL = 100 mF
TA = 255C
VI(EN)
5 V/div
RL = 5 W,
CL = 100 mF
TA = 255C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 4. Turnon Delay and Rise Time With 100-µF Load
VI(EN)
5 V/div
Figure 5. Turnoff Delay and Fall Time With 100-µF Load
VIN = 5 V
RL = 5 W,
TA = 255C
VI(EN)
5 V/div
220 mF
470 mF
IO(OUT)
500 mA/div
IO(OUT)
500 mA/div
100 mF
t − Time − 500 ms/div
Figure 6. Short-Circuit Current,
Device Enabled Into Short
Copyright © 2007–2009, Texas Instruments Incorporated
t − Time − 1 ms/div
Figure 7. Inrush Current With Different
Load Capacitance
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7
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VO(OC)
2 V/div
VO(OC)
2 V/div
IO(OUT)
1 A/div
IO(OUT)
1 A/div
t − Time − 2 ms/div
Figure 8. 2-Ω Load Connected to Enabled Device
8
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t − Time − 2 ms/div
Figure 9. 1-Ω Load Connected to Enabled Device
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1
TPS2062-1
TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009
TYPICAL CHARACTERISTICS
TURNON TIME
vs
INPUT VOLTAGE
TURNOFF TIME
vs
INPUT VOLTAGE
1.0
2
CL = 100 mF,
RL = 5 W,
TA = 255C
0.9
0.8
CL = 100 mF,
RL = 5 W,
TA = 255C
1.9
Turnoff Time − mS
Turnon Time − ms
0.7
0.6
0.5
0.4
0.3
0.2
1.8
1.7
1.6
0.1
0
2
3
4
5
VI − Input Voltage − V
1.5
6
2
4
5
VI − Input Voltage − V
Figure 10.
Figure 11.
RISE TIME
vs
INPUT VOLTAGE
FALL TIME
vs
INPUT VOLTAGE
6
0.25
0.6
CL = 1 mF,
RL = 5 W,
TA = 255C
CL = 1 mF,
RL = 5 W,
TA = 255C
0.5
0.2
0.4
Fall Time − ms
Rise Time − ms
3
0.3
0.15
0.1
0.2
0.05
0.1
0
2
3
4
5
VI − Input Voltage − V
6
0
2
3
4
5
VI − Input Voltage − V
Figure 12.
Copyright © 2007–2009, Texas Instruments Incorporated
6
Figure 13.
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9
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)
TPS2061, TPS2065-1
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
TPS2062-1, TPS2066-1
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
70
I I (IN) − Supply Current, Output Enabled − µ A
I I (IN) − Supply Current, Output Enabled − µ A
60
VI = 5.5 V
50
VI = 5 V
40
30
VI = 2.7 V
20
VI = 3.3 V
10
0
−50
0
50
100
50
VI = 5 V
VI = 3.3 V
40
30
VI = 2.7 V
20
10
0
150
VI = 5.5 V
60
−50
0
50
100
150
TJ − Junction Temperature − 5C
TJ − Junction Temperature − 5C
Figure 14.
Figure 15.
TPS2065-1
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
TPS2062-1, TPS2066-1
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
1.6
10
9
1.4
I − Off-State Current − mA
I − Off-State Current − mA
8
1.2
1
0.8
0.6
0.4
7
6
5
4
3
2
0.2
0
−50
1
0
50
100
o
10
150
0
−50
0
50
100
TJ − Junction Temperature − C
TJ − Junction Temperature − C
Figure 16.
Figure 17.
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150
o
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1
TPS2062-1
TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
120
IO = 0.5 A
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
1.56
I OS − Short-Circuit Output Current − A
On-State Resistance − mΩ
100
r DS(on) − Static Drain-Source
VI = 2.7 V
1.54
Out1 = 5 V
Out1 = 3.3 V
80
Out1 = 2.7 V
60
40
20
1.52
VI = 3.3 V
1.5
1.48
1.46
1.44
VI = 5 V
1.42
VI = 5.5 V
1.4
1.38
1.36
1.34
0
−50
0
50
100
−50
150
50
100
150
Figure 19.
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
2.3
2.5
UVLO Rising
UVOL − Undervoltage Lockout − V
TA = 255C
Load Ramp = 1A/10 ms
2.3
Threshold Trip Current − A
0
TJ − Junction Temperature − 5C
TJ − Junction Temperature − 5C
Figure 18.
2.1
1.9
1.7
1.5
2.5
3
3.5
4
4.5
5
VI − Input Voltage − V
5.5
6
2.26
2.22
UVLO Falling
2.18
2.14
2.1
−50
0
50
Figure 20.
Copyright © 2007–2009, Texas Instruments Incorporated
100
150
TJ − Junction Temperature − 5C
Figure 21.
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11
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
200
Current-Limit Response − µ s
VI = 5 V,
TA = 255C
150
100
50
0
0
12
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2.5
5
7.5
Peak Current − A
Figure 22.
10
12.5
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1
TPS2062-1
TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009
APPLICATION INFORMATION
POWER-SUPPLY CONSIDERATIONS
TPS2062-1
2
Power Supply
2.7 V to 5.5 V
IN
OUT1
0.1 µF
8
3
5
4
7
Load
0.1 µF
22 µF
0.1 µF
22 µF
OC1
EN1
OUT2
6
OC2
Load
EN2
GND
1
Figure 23. Typical Application
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients.
OVERCURRENT
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 15). The TPS206x-1 senses the short and
immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 17). The TPS206x-1 is capable of delivering current up to the current-limit threshold
without damaging the device. Once the threshold has been reached, the device switches into its constant-current
mode.
OC RESPONSE
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS206x-1 is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates
the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned
off due to an overtemperature shutdown.
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V+
TPS2062-1
GND
Rpullup
OC1
IN
OUT1
EN1
OUT2
EN2
OC2
Figure 24. Typical Circuit for the OC Pin
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistances of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power
dissipation per switch can be calculated by:
PD = rDS(on) × I2
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ = PD ×RθJA + TA
Where:
TA= Ambient temperature °C
RθJA = Thermal resistance
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS206x-1 implements a thermal sensing to monitor the operating junction
temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature
rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C due to
overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power
switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled
approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or
input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown
or overcurrent occurs.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input
voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and
voltage overshoots.
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UNIVERSAL SERIAL BUS (USB) APPLICATIONS
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
• Hosts/self-powered hubs (SPH)
• Bus-powered hubs (BPH)
• Low-power, bus-powered functions
• High-power, bus-powered functions
• Self-powered functions
SPHs and BPHs distribute data and power to downstream functions. The TPS206x-1 has higher current
capability than required by one USB port; so, it can be used on the host side and supplies power to multiple
downstream ports or functions.
HOST/SELF-POWERED AND BUS-POWERED HUBS
Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see
Figure 25). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream
connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection
and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers,
and stand-alone hubs.
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Downstream
USB Ports
D+
D−
VBUS
0.1 µF
33 µF
GND
Power Supply
3.3 V
5V
IN
OUT1
0.1 µF
D−
7
VBUS
0.1 µF
8
3
USB
Controller
D+
TPS2062-1
2
5
4
33 µF
GND
OC1
EN1
D+
OC2
EN2
OUT2
GND
D−
6
VBUS
0.1 µF
33 µF
GND
1
D+
D−
VBUS
0.1 µF
33 µF
GND
Figure 25. Typical Four-Port USB Host / Self-Powered Hub
BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to
power up with less than one unit load. The BPH usually has one embedded function, and power is always
available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up,
the power to the embedded function may need to be kept off until enumeration is completed. This can be
accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 µF at power up, the device must implement inrush current limiting (see Figure 26). With TPS206x-1, the
internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving
circuits.
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Power Supply
3.3 V
D+
D−
VBUS
TPS2062-1
2
10 µF
IN
0.1 µF
OUT1
GND
8
3
USB
Control
5
4
7
0.1 µF
10 µF
Internal
Function
0.1 µF
10 µF
Internal
Function
OC1
EN1
OC2
EN2
OUT2
GND
1
6
Figure 26. High-Power Bus-Powered Function
USB POWER-DISTRIBUTION REQUIREMENTS
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
• Hosts/SPHs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
• BPHs must:
– Enable/disable power to downstream ports
– Power up at
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