TPS2066-Q1
SLVSB37 – SEPTEMBER 2011
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CURRENT-LIMITED, POWER-DISTRIBUTION SWITCH
Check for Samples: TPS2066-Q1
FEATURES
1
•
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2
•
•
•
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Qualified for Automotive Applications
70-mΩ High-Side MOSFET
1-A Continuous Current
Thermal and Short-Circuit Protection
Accurate Current Limit
(1.1 A min, 1.9 A max)
Operating Range: 2.7 V to 5.5 V
0.6-ms Typical Rise Time
Undervoltage Lockout
Deglitched Fault Report (OC)
No OC Glitch During Power Up
1-μA Maximum Standby Supply Current
Bidirectional Switch
Ambient Temperature Range: -40°C to 105°C
•
•
Built-in Soft-Start
UL Listed - File No. E169910
APPLICATIONS
•
•
Heavy Capacitive Loads
Short-Circuit Protections
DGN PACKAGE
(TOP VIEW)
All enable inputs are active high
DESCRIPTION
The TPS2066-Q1 power-distribution switch is intended for applications where heavy capacitive loads and
short-circuits are likely to be encountered. This device incorporates 70-mΩ N-channel MOSFET power switches
for power-distribution systems that require multiple power switches in a single package. Each switch is controlled
by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch
rise times and fall times to minimize current surges during switching. The charge pump requires no external
components and allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When
continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction
temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains
off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1.5 A
typically.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS2066-Q1
SLVSB37 – SEPTEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
spacer
ORDERING INFORMATION (1)
TA
-40°C to 105°C
(1)
2
PACKAGE
8-Pin VSSOP - DGN
ORDERABLE PART
NUMBER
TOP-SIDE MARKING
TPS2066TDGNRQ1
2066Q
Reel of 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Input voltage range, VI(IN)
(2)
Output voltage range, VO(OUT)
-0.3 V to 6 V
(2)
-0.3 V to 6 V
, VO(OUTx)
Input voltage range, VI(EN), VI(EN), VI(ENx), VI(EN)
-0.3 V to 6 V
Voltage range, VI(OC), VI(OCx)
-0.3 V to 6 V
Continuous output current, IO(OUT), IO(OUTx)
Internally limited
Continuous total power dissipation
See Dissipation Rating Table
Operating junction temperature range, TJ
-40°C to 150°C
Human body model (HBM)
Electrostatic discharge (ESD) protection
2 kV
Charge device model (CDM)
1000 V
Machine model (MM)
(1)
(2)
100V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
DISSIPATING RATING TABLE
(1)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 105°C
POWER RATING
DGN-8 (1)
1712.3 mW
17.123 mW/°C
941.78 mW
684.33 mW
341 mW
Power ratings are based on the high-k board (2 signal, 2 plane) with PowerPAD™ vias to the internal ground plane.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
2.7
5.5
V
Input voltage, VI(EN), VI(EN), VI(ENx), VI(EN)
0
5.5
V
Continuous output current, IO(OUT), IO(OUTx)
0
1
A
-40
105
°C
Input voltage, VI(IN)
Operating ambient temperature, TA
UNIT
ELECTRICAL CHARACTERISTICS
over recommended operating ambient temperature range TA = -40°C to 105°C (unless otherwise noted), VI(IN) = 5.5 V, IO = 1
A, VI(ENx) = 0 V, or VI(ENx) = 5.5 V
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
POWER SWITCH
rDS(on)
tr
tf
(1)
Static drain-source on-state
resistance, 5-V operation
and 3.3-V operation
VI(IN) = 5 V or 3.3 V, IO = 1 A, -40°C ≤ TA ≤ 105°C
70
135
mΩ
Static drain-source on-state
resistance, 2.7-V
operation
VI(IN) = 2.7 V, IO = 1 A, -40°C ≤ TA ≤ 105°C
75
150
mΩ
VI(IN) = 5.5 V
0.6
1.5
VI(IN) = 2.7 V
0.4
1
Rise time, output
Fall time, output
VI(IN) = 5.5 V
CL = 1 μF, RL = 5 Ω, TA = 25°C
VI(IN) = 2.7 V
0.05
0.5
0.05
0.5
ms
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating ambient temperature range TA = -40°C to 105°C (unless otherwise noted), VI(IN) = 5.5 V, IO = 1
A, VI(ENx) = 0 V, or VI(ENx) = 5.5 V
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
ENABLE INPUT EN OR EN
VIH
High-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
VIL
Low-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
II
Input current
VI(ENx) = 0 V or 5.5 V, VI(ENx) = 0 V or 5.5 V
ton
Turnon time
CL = 100 μF, RL = 5 Ω
3
toff
Turnoff time
CL = 100 μF, RL = 5 Ω
10
2
0.8
-0.5
0.5
V
μA
ms
CURRENT LIMIT
IOS
Short-circuit output current
VI(IN) = 5 V, OUT connected to GND,
device enabled into short-circuit
IOC_TRIP
Overcurrent trip threshold
VI(IN) = 5 V, current ramp (≤ 100 A/s) on OUT
TA = 25°C
1.1
1.5
1.9
-40°C ≤ TA ≤ 105°C
1.1
1.5
2.1
1.6
2.3
2.9
TA = 25°C
0.5
1
-40°C ≤ TA ≤ 105°C
0.5
5
TA = 25°C
50
70
-40°C ≤ TA ≤ 105°C
50
90
A
A
SUPPLY CURRENT
Supply current, low-level output
No load on OUT, VI(ENx) = 0 V
Supply current, high-level output
No load on OUT, VI(ENx) = 5.5 V
Leakage current
OUT connected to ground, VI(ENx) = 0 V
-40°C ≤ TA ≤ 105°C
Reverse leakage current
VI(OUTx) = 5.5 V, IN = ground
TA = 25°C
μA
μA
1
μA
0.2
μA
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN
2
Hysteresis, IN
TA = 25°C
2.5
75
V
mV
OVERCURRENT OC1 and OC2
Output low voltage, VOL(OCx)
IO(OCx) = 5 mA
Off-state current
VO(OCx) = 5 V or 3.3 V
OC deglitch
OCx assertion or deassertion
4
8
0.4
V
1
μA
15
ms
THERMAL SHUTDOWN (2)
Thermal shutdown threshold
135
Recovery from thermal shutdown
125
Hysteresis
(2)
°C
°C
10
°C
The thermal shutdown only reacts under overcurrent conditions.
PIN FUNCTIONS
PINS
NAME
NO.
I/O
DESCRIPTION
EN1
3
I
Enable input, logic high turns on power switch IN-OUT1
EN2
4
I
Enable input, logic high turns on power switch IN-OUT2
GND
1
IN
2
I
Input voltage
OC1
8
O
Overcurrent, open-drain output, active low, IN-OUT1
OC2
5
O
Overcurrent, open-drain output, active low, IN-OUT2
OUT1
7
O
Power-switch output, IN-OUT1
OUT2
6
O
Power-switch output, IN-OUT2
PowerPAD™
-
4
Ground
Internally connected to GND; used to heat-sink the part to the circuit board traces. Should be
connected to GND pin.
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Functional Block Diagram
PARAMETER MEASUREMENT INFORMATION
Figure 1. Test Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
RL = 5 W,
CL = 1 mF
TA = 255C
VI(EN)
5 V/div
VI(EN)
5 V/div
RL = 5 W,
CL = 1 mF
TA = 255C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 2. Turnon Delay and Rise Time With 1-μF
Load
RL = 5 W,
CL = 100 mF
TA = 255C
VI(EN)
5 V/div
Figure 3. Turnoff Delay and Fall Time With 1-μF
Load
VI(EN)
5 V/div
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 4. Turnon Delay and Rise Time With 100-μF
Load
6
RL = 5 W,
CL = 100 mF
TA = 255C
Figure 5. Turnoff Delay and Fall Time With 100-μF
Load
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PARAMETER MEASUREMENT INFORMATION (continued)
VI(EN)
5 V/div
VIN = 5 V
RL = 5 W,
TA = 255C
VI(EN)
5 V/div
220 mF
470 mF
IO(OUT)
500 mA/div
IO(OUT)
500 mA/div
t − Time − 500 ms/div
Figure 6. Short-Circuit Current,
Device Enabled Into Short
100 mF
t − Time − 1 ms/div
Figure 7. Inrush Current With Different
Load Capacitance
VO(OC)
2 V/div
VO(OC)
2 V/div
IO(OUT)
1 A/div
IO(OUT)
1 A/div
t − Time − 2 ms/div
t − Time − 2 ms/div
Figure 8. 2-Ω Load Connected to Enabled Device
Figure 9. 1-Ω Load Connected to Enabled Device
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TYPICAL CHARACTERISTICS
TURN-ON TIME
vs
INPUT VOLTAGE
TURN-OFF TIME
vs
INPUT VOLTAGE
1.0
2
CL = 100 mF,
RL = 5 W,
TA = 255C
0.9
0.8
CL = 100 mF,
RL = 5 W,
TA = 255C
1.9
Turnoff Time − mS
Turnon Time − ms
0.7
0.6
0.5
0.4
0.3
0.2
1.8
1.7
1.6
0.1
0
2
3
4
5
VI − Input Voltage − V
1.5
6
2
4
5
VI − Input Voltage − V
Figure 10.
Figure 11.
RISE TIME
vs
INPUT VOLTAGE
FALL TIME
vs
INPUT VOLTAGE
6
0.25
0.6
CL = 1 mF,
RL = 5 W,
TA = 255C
CL = 1 mF,
RL = 5 W,
TA = 255C
0.5
0.2
0.4
Fall Time − ms
Rise Time − ms
3
0.3
0.15
0.1
0.2
0.05
0.1
0
2
3
4
5
VI − Input Voltage − V
6
0
2
Figure 12.
8
3
4
5
VI − Input Voltage − V
6
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
I I (IN) − Supply Current, Output Disabled − µ A
I I (IN) − Supply Current, Output Enabled − µ A
70
VI = 5.5 V
60
50
VI = 5 V
VI = 3.3 V
40
30
VI = 2.7 V
20
10
0
−50
0
50
100
0.5
VI = 5.5 V
0.45
VI = 5 V
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
−50
150
TJ − Junction Temperature − 5C
Figure 15.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
150
1.56
VI = 2.7 V
1.54
Out1 = 5 V
I OS − Short-Circuit Output Current − A
IO = 0.5 A
100
On-State Resistance − mΩ
0
50
100
TJ − Junction Temperature − 5C
Figure 14.
120
r DS(on) − Static Drain-Source
VI = 3.3 V
VI = 2.7 V
Out1 = 3.3 V
80
Out1 = 2.7 V
60
40
20
1.52
VI = 3.3 V
1.5
1.48
1.46
1.44
VI = 5 V
1.42
VI = 5.5 V
1.4
1.38
1.36
1.34
0
−50
0
50
100
150
−50
TJ − Junction Temperature − 5C
Figure 16.
0
50
100
150
TJ − Junction Temperature − 5C
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
2.3
2.5
UVLO Rising
UVOL − Undervoltage Lockout − V
TA = 255C
Load Ramp = 1A/10 ms
Threshold Trip Current − A
2.3
2.1
1.9
1.7
1.5
2.5
3
3.5
4
4.5
5
5.5
6
2.26
2.22
UVLO Falling
2.18
2.14
2.1
−50
0
50
100
150
TJ − Junction Temperature − 5C
VI − Input Voltage − V
Figure 18.
Figure 19.
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
200
Current-Limit Response − µ s
VI = 5 V,
TA = 255C
150
100
50
0
0
10
2.5
5
7.5
Peak Current − A
Figure 20.
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APPLICATION INFORMATION
POWER-SUPPLY CONSIDERATIONS
TPS2066-Q1
Figure 21. Typical Application
A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.
OVERCURRENT
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 14). The TPS2066-Q1 senses the short and
immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 15). The TPS2066-Q1 is capable of delivering current up to the current-limit threshold
without damaging the device. Once the threshold has been reached, the device switches into its constant-current
mode.
OC RESPONSE
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS2066-Q1 is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch
eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch
is turned off due to an overtemperature shutdown.
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Figure 22. Typical Circuit for the OC Pin
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistances of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 16. Using this value, the power
dissipation per switch can be calculated by:
• PD = rDS(on)× I2
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
The thermal resistance, RθJA = 1 / (DERATING FACTOR), where DERATING FACTOR is obtained from the
Dissipation Ratings Table. Thermal resistance is a strong function of the printed circuit board construction , and
the copper trace area connecting the integrated circuit.
Finally, calculate the junction temperature:
• TJ = PD x RθJA + TA
Where:
• TA= Ambient temperature °C
• RθJA = Thermal resistance
• PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS2066-Q1 implements a thermal sensing to monitor the operating junction
temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature
rises due to excessive power dissipation. Once the die temperature rises above a minimum of 135°C due to
overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power
switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled
approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or
input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown
or overcurrent occurs.
12
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UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input
voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and
voltage overshoots.
UNIVERSAL SERIAL BUS (USB) APPLICATIONS
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
• Hosts/self-powered hubs (SPH)
• Bus-powered hubs (BPH)
• Low-power, bus-powered functions
• High-power, bus-powered functions
• Self-powered functions
SPHs and BPHs distribute data and power to downstream functions. The TPS2066-Q1 has higher current
capability than required by one USB port; so, it can be used on the host side and supplies power to multiple
downstream ports or functions.
HOST/SELF-POWERED AND BUS-POWERED HUBS
Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see
Figure 23). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream
connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection
and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers,
and stand-alone hubs.
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Figure 23. Typical Four-Port USB Host / Self-Powered Hub
BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to
power up with less than one unit load. The BPH usually has one embedded function, and power is always
available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up,
the power to the embedded function may need to be kept off until enumeration is completed. This can be
accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 μF at power up, the device must implement inrush current limiting (see Figure 24). With TPS2066-Q1, the
internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving
circuits.
14
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Figure 24. High-Power Bus-Powered Function
USB POWER-DISTRIBUTION REQUIREMENTS
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
• Hosts/SPHs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
• BPHs must:
– Enable/disable power to downstream ports
– Power up at
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