TPS2068DGNR

D−8 DGN−8 TPS2060, TPS2064 TPS2068, TPS2069 DRB−8 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES Check for Samples: TPS2060, TPS2064, TPS2068, TPS2069 FEATURES APPLICATIONS • • • • • • • • • • • • • • • 1 2 • • • 70-mΩ High-Side MOSFET 1.5-A Continuous Current Thermal and Short-Circuit Protection Accurate Current Limit (1.6 A min, 2.6 A max) Operating Range: 2.7 V to 5.5 V 0.6-ms Typical Rise Time Undervoltage Lockout Deglitched Fault Report (OC) No OC Glitch During Power Up 1-μA Maximum Standby Supply Current Reverse Current Blocking TPS2060/64 Temperature Range: 0°C to 70°C TPS2068/69 DGN Package Temperature Range: –40°C to 85°C TPS2068 D Package Temperature Range: 0°C to 70°C UL Listed – File No. E169910 TPS2068/69: CB Certified Heavy Capacitive Loads Short-Circuit Protections TPS2060/TPS2064 DRB PACKAGES (TOP VIEW) TPS2060/TPS2064 DGN PACKAGE (TOP VIEW) GND IN EN1 † EN2 † 1 2 3 4 8 7 6 5 OC1 OUT1 OUT2 OC2 GND 1 8 OC1 IN 2 7 OUT1 EN1† 3 6 OUT2 EN2† 4 5 OC2 TPS2068 D PACKAGE (TOP VIEW) GND 1 8 OUT IN 2 7 OUT IN 3 6 OUT EN 4 5 OC TPS2068 DGN PACKAGE (TOP VIEW) GND IN IN EN 1 2 3 4 8 7 6 5 TPS2069 DGN PACKAGE (TOP VIEW) OUT OUT OUT OC GND IN IN EN 1 2 3 4 8 7 6 5 OUT OUT OUT OC † All enable inputs are active high for the TPS2064 devices. DESCRIPTION The TPS206x power-distribution switches are intended for applications where heavy capacitive loads and short-circuits are likely to be encountered. This device incorporates 70-mΩ N-channel MOSFET power switches for power-distribution systems that require single or dual power switches in a single package. Each switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains off until valid input voltage is present. Current limit is typically 2.1 A. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2011, Texas Instruments Incorporated TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTION AND ORDERING INFORMATION TA 0°C to 70°C –40°C to 85°C 0°C to 70°C (1) (2) ENABLE RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT TYPICAL SHORT-CIRCUIT CURRENT LIMIT AT 25°C NUMBER OF SWITCHES Active low Dual Active high Active low 1.5 A 2.1 A Active high Active low Single Single PACKAGED DEVICES (1) (2) MSOP (DGN) SON (DRB) TPS2060DGN TPS2060DRB TPS2064DGN TPS2064DRB TPS2068DGN TPS2069DGN TPS2068D The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2060DGN). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT VI Input voltage range, VI(IN) –0.3 V to 6 V Input voltage range, VI(/ENx), VI(ENx) –0.3 V to 6 V Voltage range, VI(/OC), VI(/OCx) –0.3 V to 6 V –0.3 V to 6 V VO Output voltage range, VO(OUT), VO(OUTx) IO Continuous output current, IO(OUT), IO(OUTx) Internally limited Continuous total power dissipation See Dissipation Rating Table TPS2060/64 TJ Operating virtual junction temperature range Tstg Storage temperature range ESD Electrostatic discharge protection 0°C to 105°C –40°C to 105°C TPS2068/69 (DGN Package) TPS2068 (D Package) (1) 0°C to 105°C –65°C to 150°C Human body model MIL-STD-883C 2 kV Charge device model (CDM) 500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATING RATING TABLE (1) PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DGN-8 (2) 1370 mW 17 mW/°C 600 mW 342 mW D-8 585.82 mW 5.8582 mW/°C 322.20 mW 234.32 mW DRB-8 (Low-K) (3) 270 °CW 370 mW 3.71 mW/°C 203 mW 148 mW DRB-8 (High-K) (4) 60 °CW 1600 mW 16.67 mW/°C 916 mW 866 mW (1) (2) (3) (4) 2 THERMAL RESISTANCE θJA Heatsink the PowerPad™per the recommendations of SLMA002. PCB used for recommendations per appendix A4. See Recommended Operating Conditions Table for PowerPad connection guidelines to meet qualifying conditions for CB Certificate. Soldered PowerPAD on a standard 2-layer PCB without vias for thermal pad. See TI application note SLMA002 for further details. Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad. See TI application note SLMA002 for further details. Copyright © 2005–2011, Texas Instruments Incorporated TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS (1) MIN MAX 2.7 5.5 V Input voltage, VI(ENx), VI(/ENx) 0 5.5 V IO Continuous output current, IO(OUTx) 0 1.5 A TJ Operating virtual junction temperature Input voltage, VI(IN) VI TPS2060/64 TPS2068/69 (DGN Package) 0 105 –40 105 0 105 TPS2068 (D Package) (1) UNIT °C The PowerPad must be connected externally to GND pin to meet qualifying conditions for CB Certificate (DGN package only). ELECTRICAL CHARACTERISTICS 0°C ≤ TJ ≤ 105°C for the TPS2060/64 and TPS2068 (D package), plus –40°C ≤ TJ ≤ 105° for the TPS2068/69 (DGN package), VI(IN) = 5.5 V, IO = 1 A, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V (unless otherwise noted). TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT POWER SWITCH rDS(on) tr Static drain-source on-state resistance, 5-V operation and 3.3-V operation VI(IN) = 5 V or 3.3 V, IO = 1.5 A 70 115 mΩ Static drain-source on-state resistance, 2.7-V operation VI(IN) = 2.7 V, IO = 1.5 A 75 125 mΩ 0.6 1.5 Rise time, output tf Fall time, output VI(IN) = 5.5 V VI(IN) = 2.7 V VI(IN) = 5.5 V CL = 1 μF, RL = 5 Ω TJ = 25°C VI(IN) = 2.7 V 0.4 1 0.05 0.5 0.05 0.5 ms ENABLE INPUT EN OR EN VIH High-level input voltage 2.7 V < VI(IN) < 5.5 V VIL Low-level input voltage 2.7 V < VI(IN) < 5.5 V II Input current VI(/ENx) = 0 V or 5.5 V, VI(ENx) = 0 V or 5.5 V ton Turnon time CL = 100 μF, RL = 5 Ω 3 toff Turnoff time CL = 100 μF, RL = 5 Ω 10 2 0.8 -0.5 0.5 V μA ms CURRENT LIMIT IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND, device enabled into short-circuit IOC_TRIP Overcurrent trip threshold VI(IN) = 5 V, Current ramp (≤ 100 A/s) on OUT Short-circuit output current VI(IN) = 5 V, OUT1 and OUT2 connected to GND, Device enabled into short-circuit, current measured at VI(IN) IOC_TRIP (2) Overcurrent trip threshold TPS2060/64 VI(IN) = 5 V, Current ramp (≤ 100 A/s) on OUT1 and OUT2 tied together, current measured at VI(IN) IOL Supply current, low-level output No load on OUT, VI(/ENx) = 5.5 V, or VI(ENx) = 0 V IOH Supply current, high-level output TPS2060/64 IOH Ilkg IOS (2) 1.6 2.1 2.6 3.2 3.9 2.3 2.85 3.4 3.2 4.2 5.2 A 6.4 7.8 A TJ = 25°C 0.5 1 Over TJ range 0.5 5 No load on OUT, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V TJ = 25°C 50 70 Over TJ range 50 90 Supply current, high-level output TPS2068/69 No load on OUT, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V TJ = 25°C 43 60 Over TJ range 43 70 Leakage current OUT connected to ground, VI(/ENx) = 5.5 V, or VI(ENx) = 0 V Reverse leakage current VI(OUTx) = 5.5 V, IN = ground TPS2060/64 TPS2068/69 TJ = 25°C A A μA μA μA 1 μA 0.2 μA UNDERVOLTAGE LOCKOUT Low-level input voltage, IN Hysteresis, IN (1) (2) 2 TJ = 25°C 2.5 75 V mV Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. This configuration has not been tested for UL certification. Copyright © 2005–2011, Texas Instruments Incorporated 3 TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) 0°C ≤ TJ ≤ 105°C for the TPS2060/64 and TPS2068 (D package), plus –40°C ≤ TJ ≤ 105° for the TPS2068/69 (DGN package), VI(IN) = 5.5 V, IO = 1 A, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V (unless otherwise noted). TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT OVERCURRENT OCx VOL(/OCx) Output low voltage IO(/OCx) = 5 mA Off-state current VO(/OCx) = 5 V or 3.3 V OC deglitch OCx assertion or deassertion 4 8 0.4 V 1 μA 15 ms THERMAL SHUTDOWN (3) Thermal shutdown threshold 135 Recovery from thermal shutdown 125 Hysteresis (3) °C °C 10 °C The thermal shutdown only reacts under overcurrent conditions. DEVICE INFORMATION Pin Functions PINS DGN and DRB PACKAGES NAME I/O DESCRIPTION TPS2060 TPS2064 3 — I Enable input, logic low turns on power switch IN-OUT1 EN2 4 — I Enable input, logic low turns on power switch IN-OUT2 EN1 — 3 I Enable input, logic high turns on power switch IN-OUT1 EN2 — 4 I Enable input, logic high turns on power switch IN-OUT2 GND 1 1 IN 2 2 I Input voltage OC1 8 8 O Overcurrent, open-drain output, active low, IN-OUT1 OC2 5 5 O Overcurrent, open-drain output, active low, IN-OUT2 OUT1 7 7 O Power-switch output, IN-OUT1 OUT2 6 6 O Power-switch output, IN-OUT2 EN1 PowerPad PowerPad 4 Ground Connect to GND Copyright © 2005–2011, Texas Instruments Incorporated TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com Functional Block Diagram (TPS2060 and TPS2064) OC1 Thermal Sense GND Deglitch EN1 (See Note B) Driver Current Limit Charge Pump (See Note A) CS OUT1 UVLO (See Note A) IN CS OUT2 Charge Pump Driver Current Limit OC2 EN2 (See Note B) Thermal Sense A. Current sense. B. Active low (ENx) for TPS2060. Active high (ENx) for TPS2064. Copyright © 2005–2011, Texas Instruments Incorporated Deglitch 5 TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com DEVICE INFORMATION Pin Functions (TPS2068 and TPS2069) PINS NAME I/O DESCRIPTION TPS2068 TPS2069 EN 4 — I Enable input, logic low turns on power switch EN — 4 I Enable input, logic high turns on power switch GND 1 1 IN 2, 3 2, 3 I Input voltage OC 5 5 O Overcurrent, open-drain output, active-low 6, 7, 8 6, 7, 8 O Power-switch output PowerPad PowerPad OUT (1) Ground Connect to GND (DGN Package Only) (1) See the Recommended Operating Conditions Table for PowerPad connection guidelines to meet qualifying conditions for CB Certificate (DGN package only). Functional Block Diagram (TPS2068 and TPS2069) (See Note A) CS IN OUT Charge Pump EN (See Note B) Driver Current Limit OC UVLO GND 6 Thermal Sense A. Current sense. B. Active low (EN) for TPS2068. Active high (EN) for TPS2069. Deglitch Copyright © 2005–2011, Texas Instruments Incorporated TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION OUT RL tf tr CL VO(OUT) 90% 10% 90% 10% TEST CIRCUIT 50% VI(EN) 50% toff ton VO(OUT) 50% VI(EN) 90% 50% toff ton VO(OUT) 10% 90% 10% VOLTAGE WAVEFORMS Figure 1. Test Circuit and Voltage Waveforms RL = 5 W, CL = 1 mF, TA = 25 °C VI(EN) 5 V/div VI(EN) 5 V/div RL = 5 W, CL = 1 mF, TA = 25 °C VO(OUT) 2 V/div VO(OUT) 2 V/div t - Time - 400 ms Figure 2. Turnon Delay and Rise Time With 1-μF Load Copyright © 2005–2011, Texas Instruments Incorporated t - Time - 400 ms Figure 3. Turnoff Delay and Fall Time With 1-μF Load 7 TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) RL = 5 W, CL = 100 mF, TA = 25 °C VI(EN) 5 V/div VO(OUT) 2 V/div VI(EN) 5 V/div RL = 5 W, CL = 100 mF, TA = 25 °C VO(OUT) 2 V/div t - Time - 400 ms Figure 4. Turnon Delay and Rise Time With 100-μF Load t - Time - 400 ms Figure 5. Turnoff Delay and Fall Time With 100-μF Load VIN = 5 V, RL = 3 W, TA = 255C VI(EN) 5 V/div VI(EN) 5 V/div 220 mF 470 mF IO(OUT) 1 A/div 100 mF IO(OUT) 500 mA/div t − Time − 500 ms/div t − Time − 500 ms/div Figure 6. Short-Circuit Current, Device Enabled Into Short 8 Figure 7. Inrush Current With Different Load Capacitance Copyright © 2005–2011, Texas Instruments Incorporated TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VO(OCx) 2 V/div IO(OUT) 1 A/div t - Time - 2 ms/div Figure 8. 0.6-Ω Load Connected to Enabled Device TYPICAL CHARACTERISTICS TURNON TIME vs INPUT VOLTAGE TURNOFF TIME vs INPUT VOLTAGE 1.0 2 CL = 100 mF, RL = 5 W, TA = 255C 0.9 0.8 CL = 100 mF, RL = 5 W, TA = 255C 1.9 Turnoff Time − mS Turnon Time − ms 0.7 0.6 0.5 0.4 0.3 0.2 1.8 1.7 1.6 0.1 0 2 3 4 5 VI − Input Voltage − V Figure 9. Copyright © 2005–2011, Texas Instruments Incorporated 6 1.5 2 3 4 5 VI − Input Voltage − V 6 Figure 10. 9 TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) RISE TIME vs INPUT VOLTAGE FALL TIME vs INPUT VOLTAGE 0.25 0.6 0.5 0.2 0.4 Fall Time − ms Rise Time − ms CL = 1 mF, RL = 5 W, TA = 255C CL = 1 mF, RL = 5 W, TA = 255C 0.3 0.15 0.1 0.2 0.05 0.1 0 2 3 4 5 VI − Input Voltage − V 0 6 2 Figure 12. TPS2060, TPS2064 SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE TPS2068, TPS2069 SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE II(IN) - Supply Current, Output Enabled - mA I I (IN) − Supply Current, Output Enabled − µ A 6 60 VI = 5.5 V 60 50 VI = 5 V VI = 3.3 V 40 30 VI = 2.7 V 20 10 VI = 5.5 V 50 VI = 5 V 40 30 20 VI = 3.3 V VI = 2.7 V 10 0 −50 0 50 100 TJ − Junction Temperature − 5C Figure 13. 10 4 5 VI − Input Voltage − V Figure 11. 70 0 3 150 -50 0 50 100 150 TJ - Junction Temperature - °C Figure 14. Copyright © 2005–2011, Texas Instruments Incorporated TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 120 0.5 0.45 IO = 0.5 A VI = 5.5 V VI = 5 V 0.35 VI = 3.3 V VI = 2.7 V 0.25 0.2 0.15 0.1 Out1 = 3.3 V 80 Out1 = 2.7 V 60 40 20 0.05 0 −50 0 50 100 TJ − Junction Temperature − 5C 0 150 −50 0 50 100 150 TJ − Junction Temperature − 5C Figure 15. Figure 16. SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 2.3 2.6 UVLO Rising UVOL − Undervoltage Lockout − V 2.5 IOS - Short-Circuit Current Limit - A On-State Resistance − mΩ 0.4 0.3 Out1 = 5 V 100 r DS(on) − Static Drain-Source I I (IN) − Supply Current, Output Disabled − µ A SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE 2.4 VI = 2.7 V 2.3 VI = 3.3 V 2.2 2.1 VI = 5.5 V VI = 5 V 2 1.9 1.8 2.26 2.22 UVLO Falling 2.18 2.14 1.7 1.6 -50 0 50 100 TJ - Junction Temperature - °C Figure 17. Copyright © 2005–2011, Texas Instruments Incorporated 150 2.1 −50 0 50 100 150 TJ − Junction Temperature − 5C Figure 18. 11 TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) CURRENT-LIMIT RESPONSE vs PEAK CURRENT 200 Current-Limit Response - ms VI = 5 V, TA = 25 °C 150 100 50 0 0 2.5 5 7.5 10 Peak Current - A Figure 19. 12 Copyright © 2005–2011, Texas Instruments Incorporated TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com APPLICATION INFORMATION POWER-SUPPLY CONSIDERATIONS TPS2060 2 Power Supply 2.7 V to 5.5 V IN OUT1 0.1 µF 8 3 5 4 7 Load 0.1 µF 22 µF 0.1 µF 22 µF OC1 EN1 OUT2 6 OC2 Load EN2 GND 1 Figure 20. Typical Application A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients. OVERCURRENT A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 6). The TPS206x senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents may flow for a short period of time before the current-limit circuit can react (see Figure 8). After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded. The TPS206x is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC RESPONSE The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit. The TPS206x is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned off due to an overtemperature shutdown. Copyright © 2005–2011, Texas Instruments Incorporated 13 TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com V+ TPS2060 GND Rpullup OC1 IN OUT1 EN1 OUT2 EN2 OC2 Figure 21. Typical Circuit for the OC Pin POWER DISSIPATION AND JUNCTION TEMPERATURE The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large currents. The thermal resistance of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 16. Using this value, the power dissipation per switch can be calculated by: PD = rDS(on) × I2 Multiply this number by the number of switches being used. This step renders the total power dissipation from the N-channel MOSFETs. Finally, calculate the junction temperature: TJ = PD × RθJA + TA Where: TA= Ambient temperature °C RθJA = Thermal resistance PD = Total power dissipation based on number of switches being used. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. THERMAL PROTECTION Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS206x implements a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs. UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots. 14 Copyright © 2005–2011, Texas Instruments Incorporated TPS2060, TPS2064 TPS2068, TPS2069 www.ti.com SLVS553K – MARCH 2005 – REVISED MAY 2011 UNIVERSAL SERIAL BUS (USB) APPLICATIONS The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for lowto-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: • Hosts/self-powered hubs (SPH) • Bus-powered hubs (BPH) • Low-power, bus-powered functions • High-power, bus-powered functions • Self-powered functions SPHs and BPHs distribute data and power to downstream functions. The TPS206x has higher current capability than required by one USB port; so, it can be used on the host side and supplies power to multiple downstream ports or functions. HOST/SELF-POWERED AND BUS-POWERED HUBS Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see Figure 22). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. Copyright © 2005–2011, Texas Instruments Incorporated 15 TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com Downstream USB Ports D+ D− VBUS 0.1 µF 22 µF GND D+ D− VBUS 0.1 µF 22 µF GND Power Supply 3.3 V 5V IN OUT1 0.1 µF D− 7 VBUS 0.1 µF 8 3 USB Controller D+ TPS2060 2 5 4 22 µF GND OC1 EN1 D+ OC2 EN2 OUT2 GND D− 6 VBUS 0.1 µF 2 µF GND 1 D+ D− VBUS 0.1 µF 22 µF GND D+ D− VBUS 0.1 µF 22 µF GND Figure 22. Typical Six-Port USB Host/Self-Powered Hub BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port. 16 Copyright © 2005–2011, Texas Instruments Incorporated TPS2060, TPS2064 TPS2068, TPS2069 SLVS553K – MARCH 2005 – REVISED MAY 2011 www.ti.com LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 μF at power up, the device must implement inrush current limiting (see Figure 23). With TPS206x, the internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving circuits. Power Supply 3.3 V D+ D− VBUS TPS2060 2 10 µF 0.1 µF IN OUT1 GND 8 3 USB Control 5 4 7 0.1 µF 10 µF Internal Function 0.1 µF 10 µF Internal Function OC1 EN1 OC2 EN2 OUT2 GND 1 6 Figure 23. High-Power Bus-Powered Function USB POWER-DISTRIBUTION REQUIREMENTS USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented. • Hosts/SPHs must: – Current-limit downstream ports – Report overcurrent conditions on USB VBUS • BPHs must: – Enable/disable power to downstream ports – Power up at