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TPS2069D
SLVSDQ5 – DECEMBER 2016
TPS2069D Current Limited, Power-Distribution Switches
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The TPS2069D power-distribution switch family is
intended for applications such as USB where heavy
capacitive loads and short circuits are likely to be
encountered. The device can continuously deliver up
to 1.5 A output current.
1
Single Power Switch Family
Rated currents of 1.5 A
±20% Accurate, Fixed, Constant Current Limit
Fast Overcurrent Response: 2 µs
Deglitched Fault Reporting
Output Discharge
Reverse Current Blocking
Built-in Soft Start
Ambient Temperature Range: –40°C to 85°C
UL Listed and CB-File No. E169910
The TPS2069D limits the output current to a safe
level by operating in a constant-current mode when
the output load exceeds the current limit threshold.
This provides a predictable fault current under all
conditions. The fast overload response time eases
the burden on the main 5-V supply to provide
regulated power when the output is shorted. The
power-switch rise and fall times are controlled to
minimize current surges during turnon and turnoff.
2 Applications
•
•
•
•
Device Information(1)
USB Ports/Hubs, Laptops, Desktops
High-Definition Digital TVs
Set Top Boxes
Short Circuit Protection
PART NUMBER
TPS2069D
PACKAGE
SOT-23 (5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Spacer
Spacer
Spacer
Typical Application Diagram
IN
OUT
0.1 mF
VIN
RFLT
10 kW
VOUT
150 mF
Fault Signal
FLT
Control Signal
EN
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2069D
SLVSDQ5 – DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: TJ = TA = 25°C.................
Electrical Characteristics: –40°C ≤ TJ ≤ 125°C.........
Timing Requirements: –40°C ≤ TJ ≤ 125°C ..............
Typical Characteristics ..............................................
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
11.3 Power Dissipation and Junction Temperature ...... 17
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Detailed Description ............................................ 11
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
8.1 Overview ................................................................. 11
8.2 Functional Block Diagrams ..................................... 11
4 Revision History
2
DATE
REVISION
NOTES
December 2016
*
Initial release.
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5 Device Comparison Table
MAXIMUM OPERATING
CURRENT
OUTPUT DISCHARGE
ENABLE
1.5 A
Y
High
6 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
OUT
1
GND
2
FLT
3
5
IN
4
EN
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
EN
4
I
GND
2
—
IN
5
PWR
FLT
3
O
OUT
1
PWR
DESCRIPTION
Enable input, logic high turns on power switch
Ground connection
Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to GND
close to the IC
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions
Power-switch output, connect to load.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX
UNIT
–0.3
6
V
Voltage range from IN to OUT
–6
6
V
Maximum junction temperature, TJ
Internally Limited
Storage temperature, Tstg
–60
Voltage range on IN, OUT, EN, FLT
(1)
(2)
(3)
(4)
(4)
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Absolute maximum ratings apply over recommended junction temperature range.
Voltages are with respect to GND unless otherwise noted.
See Input and Output Capacitance .
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
Electrostatic discharge
IEC 61000-4-2 contact discharge
±500
(3)
V
±8000
IEC 61000-4-2 air-gap discharge
(1)
(2)
(3)
UNIT
±2000
±15000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
VOUT was surged on a pcb with input and output bypassing per Input and Output Capacitance (except input capacitor was 22 µF) with
no device failures.
7.3 Recommended Operating Conditions
MIN
VIN
Input voltage, IN
VEN
VIH
VIL
Low-level input voltage, EN
IOUT
Continuous output current, OUT (1)
TJ
Operating junction temperature
IFLT
Sink current into FLT
(1)
NOM
MAX
UNIT
4.5
5.5
V
Input voltage, EN
0
5.5
V
High-level input voltage, EN
2
V
0.7
V
1.5 A
A
–40
125
°C
0
5
mA
Some package and current rating may request an ambient temperature derating of 85°C.
7.4 Thermal Information
TPS2069D
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
220.4
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
89.7
°C/W
RθJB
Junction-to-board thermal resistance
46.9
°C/W
ψJT
Junction-to-top characterization parameter
5.2
°C/W
ψJB
Junction-to-board characterization parameter
46.2
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
°C/W
RθJACustom
See Power DIssipation and Junction Temperature
134.9
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics: TJ = TA = 25°C (1)
Unless otherwise noted: VIN = 5 V, VEN = VIN, IOUT = 0 A. See Device Comparison Table for the rated current of each part
number. Parametrics over a wider operational range are shown in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C.
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
POWER SWITCH
RDS(on)
Input – output resistance
1.5-A rated output, 25°C
DBV
76
91
mΩ
1.5-A rated output,
–40°C ≤ (TJ , TA) ≤ 85°C
DBV
76
106
mΩ
2.15
2.5
A
0.01
1
CURRENT LIMIT
IOS (2)
Current limit, See Figure 6
1.5-A rated output
1.7
SUPPLY CURRENT
ISD
Supply current, switch disabled
ISE
Supply current, switch enabled
IREV
Reverse leakage current
IOUT = 0 A
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A
2
IOUT = 0 A
60
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A
70
85
VOUT = 5 V, VIN = 0 V, measure IVOUT
0.1
–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 5 V, VIN = 0 V, measure
IVOUT
µA
µA
1
5
µA
OUTPUT DISCHARGE
RPD
(1)
(2)
(3)
Output pulldown resistance (3)
VIN = VOUT = 5 V, disabled
400
470
600
Ω
Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
See Current Limit section for explanation of this parameter.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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7.6 Electrical Characteristics: –40°C ≤ TJ ≤ 125°C
Unless otherwise noted:4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, IOUT = 0 A, typical values are at 5 V and 25°C. See Device Comparison
Table for the rated current of each part number.
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
76
121
mΩ
POWER SWITCH
RDS(ON)
Input – output resistance
1.5-A rated output
DBV
ENABLE INPUT (EN)
Threshold
Input rising
1
1.45
2
0.07
0.13
0.20
V
(VEN) = 0 V
–1
0
1
µA
Current limit, See Figure 22
1.5-A rated output
1.6
2.15
2.7
A
Short circuit response time (3)
VIN = 5 V (see Figure 6),
One-half full load → RSHORT = 50 mΩ,
Measure from application to when current falls below 120% of
final value
Hysteresis
Leakage current
V
CURRENT LIMIT
IOS (2)
tIOS
2
µs
SUPPLY CURRENT
ISD
Supply current, switch disabled
IOUT = 0 A
0.01
10
µA
ISE
Supply current, switch enabled
IOUT = 0 A
65
90
µA
IREV
Reverse leakage current
VOUT = 5.5 V, VIN = 0 V, measure IVOUT
0.2
20
µA
3.75
4
V
UNDERVOLTAGE LOCKOUT
VUVLO
Rising threshold
VIN↑
Hysteresis (3)
VIN↓
Output low voltage, FLT
IFLT = 1 mA
Off-state leakage
VFLT = 5.5 V
FLT deglitch
FLT assertion or deassertion deglitch
3.5
0.14
V
FLT
tFLT
0.2
V
1
µA
ms
6
9
12
VIN = 4 V, VOUT = 5 V, disabled
350
560
1200
VIN = 5 V, VOUT = 5 V, disabled
300
470
800
In current limit
135
Not in current limit
155
OUTPUT DISCHARGE
RPD
Output pulldown resistance
Ω
THERMAL SHUTDOWN
Rising threshold (TJ)
Hysteresis
(1)
(2)
(3)
(3)
°C
20
Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
See Current Limit for explanation of this parameter.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
7.7 Timing Requirements: –40°C ≤ TJ ≤ 125°C
MIN
NOM
MAX
UNIT
1.2
1.7
2.2
ms
tON
Turnon time
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↑ or EN ↓.
See Figure 1, Figure 3, and Figure 4
1.5 A Rated
tOFF
Turnoff time
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↓ or EN ↑.
See Figure 1, Figure 3, and Figure 4
1.5 A Rated
1.7
2.1
2.5
ms
tR
Rise time, output
CL = 1 µF, RL = 100 Ω, VIN = 5 V. See Figure 2
1.5 A Rated
0.5
0.7
1
ms
tF
Fall time, output
CL = 1 µF, RL = 100 Ω, VIN = 5 V. See Figure 2
1.5 A Rated
0.3
0.43
0.55
ms
6
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OUT
RL
CL
Figure 1. Output Rise and Fall Test Load
tR
VOUT
90%
tF
10%
Figure 2. Power-On and Power-Off Timing
VEN
50%
tON
50%
tOFF
90%
VOUT
10%
Figure 3. Enable Timing, Active High Enable
V/EN
50%
50%
tOFF
tON
90%
VOUT
10%
Figure 4. Enable Timing, Active Low Enable
120% x IOS
IOUT
IOS
0A
tIOS
Figure 5. Output Short Circuit Parameters
VIN
Decreasing
Load
Resistance
VOUT
Slope = -RDS(ON)
0V
0A
IOUT
IOS
Figure 6. Output Characteristic Showing Current Limit
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7.8 Typical Characteristics
14
9.3
85°C
12
IOUT sinking (mA)
tFLT (ms)
9.2
9.1
9.0
25°C
10
8
−40°C
6
125°C
4
8.9
2
8.8
−40
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
0
0.0
140
0.5
1.0
1.5
G019
All Versions, 5 V
2.0 2.5 3.0 3.5
Output Voltage (V)
4.0
4.5
5.0
5.5
G020
VIN = 5 V
Figure 7. Deglitch Period (TFLT) vs Temperature
Figure 8. Output Discharge Current vs Output Voltage
7
3.5
6
3.0
5
IOS (A)
2.0
IREV (µA)
1.5-A Rated
2.5
1-A Rated
1.5
0.5-A Rated
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
−1
−40
140
0
20
40
60
80
100
Junction Temperature (°C)
120
140
G022
All Unit Types, 5 V
Figure 10. Reverse Leakage Current (IREV) vs Temperature
1.0
0.8
0.8
0.6
0.6
ISD (µA)
1.0
0.4
125°C
0.4
0.2
0.2
0.0
0.0
−0.2
−40
−20
G021
Figure 9. Short Circuit Current (IOS) vs Temperature
ISD (µA)
2
0
VIN = 5 V
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
Figure 11. Disabled Supply Current (ISD) vs Temperature
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−0.2
4.00
G023
Input Voltage = 5.5 V
8
3
1
1.0
0.5
−40
4
85°C
−40°C and 25°C
4.25
4.50
4.75
5.00
Input Voltage (V)
5.25
5.50
G024
All Unit Types
Figure 12. Disabled Supply Current (ISD) vs Input Voltage
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6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−0.5
4.00
80
75
125°C
70
ISE (µA)
IREV (µA)
Typical Characteristics (continued)
85°C
25°C
60
−40°C
55
4.25
4.50
4.75
5.00
Output Voltage (V)
All Unit Types
5.25
50
−40
5.50
VIN = 0 V
0
20
40
60
80
100
Junction Temperature (°C)
All Unit Types
140
G026
VIN = 5.5 V
0.475
75
125°C
85°C
0.450
0.425
tf (ms)
65
60
0.400
55
1.5-A and 2-A Rated, V IN = 4.5 V
1.5-A and 2-A Rated, V IN = 5 V
0.375
1.5-A and 2-A Rated, V IN = 5.5 V
50
0.350
25°C
45
−40°C
40
4.00
4.25
4.50
4.75
5.00
Input Voltage (V)
5.25
0.325
−40
5.50
0.5-A and 1-A Rated, V IN = 5 V
−20
0
G027
COUT = 1 µF
Figure 15. Enabled Supply Current (ISE) vs Input Voltage
20
40
60
80
100
Junction Temperature (°C)
120
140
G028
RLOAD = 100 Ω
Figure 16. Output Fall Time (TF) vs Temperature
0.85
140
130
1.5 A, 2 A, 5.5 V
0.80
120
0.75
0.5-A, 1-A Rated
110
RDSON (mW)
tr (ms)
120
Figure 14. Enabled Supply Current (ISE) vs Temperature
80
ISE (µA)
−20
G025
Figure 13. Reverse Leakage Current (IREV) vs Output Voltage
70
65
0.70
0.65
0.5 A, 1 A, 5 V
0.60
90
80
70
1.5 A, 2 A, 5 V
1.5-A, 2-A Rated
60
1.5 A, 2 A, 4.5 V
0.55
100
50
0.50
−40
COUT = 1 µF
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
G029
RLOAD = 100 Ω
Figure 17. Output Rise Time (TR) vs Temperature
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40
−40
−20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
G030
VIN = 5 V
Figure 18. Input-Output Resistance (RDS(ON)) vs Temperature
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Typical Characteristics (continued)
Recovery Time (µs)
100
IOS
10
1
0
5
VIN = 5 V
10
15
IPK (Shorted) (A)
20
CIN = 730 µF
25
G031
IEND = 1.68 A
Figure 19. Recovery vs Current Peak
10
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8 Detailed Description
8.1 Overview
The TPS2069D are current limited, power-distribution switches providing 1.5 A of continuous load current in 5-V
circuits. These parts use N-channel MOSFETs for low resistance, maintaining voltage regulation to the load.
They are designed for applications where short circuits or heavy capacitive loads are encountered. Device
features include enable, reverse blocking when disabled, output discharge pulldown, overcurrent protection,
overtemperature protection, and deglitched fault reporting.
8.2 Functional Block Diagrams
Current
Sense
IN
Charge
Pump
EN
CS
OUT
Current
Limit
(Disabled+
UVLO)
Driver
UVLO
GND
FLT
OTSD
Thermal
Sense
9-ms
Deglitch
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Figure 20. Block Diagram
8.3 Feature Description
8.3.1 Undervoltage Lockout
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turnon threshold. Built-in hysteresis prevents unwanted ON/OFF cycling due to input voltage drop from large
current surges. FLT is high impedance when the TPS2069D is in UVLO.
8.3.2 Enable
The logic enable input (EN), controls the power switch, bias for the charge pump, driver, and other circuits. The
supply current is reduced to less than 1 µA when the TPS2069D is disabled. Disabling the TPS2069D
immediately clears an active FLT indication. The enable input is compatible with both TTL and CMOS logic
levels.
The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times
are internally controlled. The rise time is controlled by the device and the external loading (especially
capacitance). TPS2069D fall time is controlled by the loading (R and C), and the output discharge (RPD). An
output load consisting of only a resistor will experience a fall time set by the device. An output load with parallel
R and C elements experiences a fall time determined by the (R × C) time constant if it is longer than the device
tF.
The enable should not be left open, and may be tied to VIN or GND depending on the device.
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Feature Description (continued)
8.3.3 Internal Charge Pump
The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel
MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull
the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of
the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start
functionality. The MOSFET power switch will block current from OUT to IN when turned off by the UVLO or
disabled.
8.3.4 Current Limit
The TPS2069D responds to overloads by limiting output current to the static IOS levels shown in Electrical
Characteristics: TJ = TA = 25°C (1). When an overload condition is present, the device maintains a constant output
current, with the output voltage determined by (IOS × RLOAD). Two possible overload conditions can occur.
The first overload condition occurs when either: 1) input voltage is first applied, enable is true, and a short circuit
is present (load which draws IOUT > IOS), or 2) input voltage is present and the device is enabled into a short
circuit. The output voltage is held near zero potential with respect to ground and the TPS2069D ramps the output
current to IOS. The device limits the current to IOS until the overload condition is removed or the device begins to
thermal cycle.
The second condition is when an overload occurs while the device is enabled and fully turned on. The device
responds to the overload condition within tIOS (Figure 5 and Figure 6) when the specified overload (see Electrical
Characteristics: –40°C ≤ TJ ≤ 125°C) is applied. The response speed and shape varies with the overload level,
input circuit, and rate of application. The current limit response will vary between simply settling to IOS, or turnoff
and controlled return to IOS. Similar to the previous case, the device limits the current to IOS until the overload
condition is removed or the device begins to thermal cycle.
The TPS2069D thermal cycles if an overload condition is present long enough to activate thermal limiting in any
of the above cases. This is due to the relatively large power dissipation [(VIN – VOUT) x IOS] driving the junction
temperature up. The device turns off when the junction temperature exceeds 135°C (minimum) while in current
limit. The device remains off until the junction temperature cools 20°C and then restarts.
There are two kinds of current limit profiles typically available in TI switch products similar to the TPS2069D.
Many older designs have an output I vs V characteristic similar to the plot labeled Current Limit with Peaking in
Figure 21. This type of limiting can be characterized by two parameters, the current limit corner (IOC), and the
short circuit current (IOS). IOC is often specified as a maximum value. The TPS2069D does not present noticeable
peaking in the current limit, corresponding to the characteristic labeled Flat Current Limit in Figure 21. This is
why the IOC parameter is not present in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C.
Current Limit
with Peaking
Flat Current
Limit
VIN
Decreasing
Load
Resistance
Decreasing
Load
Resistance
Slope = -RDS(ON)
VOUT
VO UT
Slope = -RDS(ON)
VIN
0V
0V
0A
IOUT
IOS IOC
0A
IOUT
I OS
Figure 21. Current Limit Profiles
(1)
12
Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
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Feature Description (continued)
8.3.5 FLT
The FLT open-drain output is asserted (active low) during an overload or overtemperature condition. A 9-ms
deglitch on both the rising and falling edges avoids false reporting at start-up and during transients. A current
limit condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer will
not integrate multiple short overloads and declare a fault. This is also true for exiting from a faulted state. An
input voltage with excessive ripple and large output capacitance may interfere with operation of FLT around IOS
as the ripple drives the device in and out of current limit.
If the TPS2069D is in current limit and the overtemperature circuit goes active, FLT goes true immediately;
however, the exiting this condition is deglitched. FLT is tripped just as the knee of the constant-current limiting is
entered. Disabling the device clears an active FLT as soon as the switch turns off. FLT is high impedance when
the device is disabled or in undervoltage lockout (UVLO).
8.3.6 Output Discharge
A 470-Ω (typical) output discharge dissipates stored charge and leakage current on OUT when the TPS2069D is
in UVLO or disabled. The pulldown circuit loses bias gradually as VIN decreases, causing a rise in the discharge
resistance as VIN falls towards 0 V. The output is be controlled by an external loadings when the device is in
ULVO or disabled.
8.4 Device Functional Modes
There are no other functional modes.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS2069D current limited power switch uses N-channel MOSFETs in applications requiring continuous load
current. The device enters constant-current mode when the load exceeds the current limit threshold.
9.2 Typical Application
4.5 V~5.5 V
VOUT
0.1 F
5
OUT
IN
RFAULT
1
COUT
Fault
Signal
3 FAULT
Control
Signal
4
EN
GND
2
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the following input parameters:
1. The TPS2069D operates from a 5 V±0.5V rail.
2. What is the normal operation current, for example, the maximum allowable current drawn by portable
equipment for USB 3.0 port is 900 mA, so the normal operation current is 900 mA, and the minimum current
limit of power switch must exceed 900 mA to avoid false trigger during normal operation. For the TPS2069D
device, target 1.5 A continuous output current application.
3. What is the maximum allowable current provided by up-stream power, the maximum current limit of power
switch that must lower it to ensure power switch can protect the up-stream power when overload is
encountered at the output of power switch. For the TPS2069D device, the maximum IOS is 2.5 A.
9.2.2 Detailed Design Procedure
To
1.
2.
3.
14
begin the design process a few parameters must be decided upon. The designer needs to know the following:
Normal input operation voltage
Output continuous current
Maximum up-stream power supply output current
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Typical Application (continued)
9.2.2.1 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. For all applications, TI recommends placing a 0.1-µF or greater ceramic
bypass capacitor between IN and GND, as close to the device as possible for local noise decoupling.
All protection circuits such as the TPS2069D has the potential for input voltage overshoots and output voltage
undershoots.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input
voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high
impedance (before turnon). Theoretically, the peak voltage is 2× the applied. The second cause is due to the
abrupt reduction of output short circuit current when the device turns off and energy stored in the input
inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the
device output is shorted. Applications with large input inductance (for example, connecting the evaluation board
to the bench power-supply through long cables) may require large input capacitance reduce the voltage
overshoot from exceeding the absolute maximum voltage of the device. The fast current limit speed of the device
to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in the range of
1 µF to 22 µF adjacent to the device input aids in both speeding the response time and limiting the transient
seen on the input power bus. Momentary input transients to 6.5 V are permitted.
Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred
and the TPS2069D has abruptly reduced OUT current. Energy stored in the inductance drives the OUT voltage
down and potentially negative as it discharges. Applications with large output inductance (such as from a cable)
benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB
standard applications, a 120 µF minimum output capacitance is required. Typically a 150-µF electrolytic capacitor
is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of
capacitance, and there is potential to drive the output negative, then TI recommends a minimum of 10-µF
ceramic capacitance on the output. The voltage undershoot should be controlled to less than 1.5 V for 10 µs.
9.2.3 Application Curves
2.5
10
10
2.0
8
3.0
Output
Current
EN
Output Current
1.0
0.5
4
2
Amplitude (V)
EN
Current (A)
Amplitude (V)
6
6
1.5
8
2.5
2.0
1.5
4
1.0
2
FLT
0.0
0
−0.5
−2
Current (A)
12
0.5
FLT
Output Voltage
0
−2
−4m −2m
0
2m
VIN = 5 V
4m
−1.0
6m 8m 10m 12m 14m 16m
Time (s)
COUT = 150 µF
Figure 23. Turnon into 3.3 Ω
Copyright © 2016, Texas Instruments Incorporated
−4
−2m
0.0
Output Voltage
0
2m
4m
G001
RLOAD = 3.3 Ω
VIN = 5 V
6m
−0.5
8m 10m 12m 14m 16m 18m
Time (s)
COUT = 150 µF
G002
RLOAD = 50 mΩ
Figure 24. Enable into Short
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Typical Application (continued)
3.0
10
2.5
8
6
2.0
4
1.5
2
Output Current
1.0
Current (A)
Amplitude (V)
EN
0.5
0
0.0
−2
Output Voltage
−4
−12.5m
−7.5m
VIN = 5 V
FLT
−2.5m
2.5m
Time (s)
7.5m
COUT = 150 µF
−0.5
12.5m
G003
RLOAD = 50 mΩ
Figure 25. Pulsed Output Short
16
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10 Power Supply Recommendations
Design of the devices is for operation from an input voltage supply range of 4.5 V to 5.5 V. The current capability
of the power supply should exceed the maximum current limit of the power switch.
11 Layout
11.1 Layout Guidelines
1. Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low
inductance trace.
2. Place at least 10-µF low ESR ceramic capacitor near the OUT and GND pins, and make the connections
using a low inductance trace.
3. The PowerPAD™ should be directly connected to PCB ground plane using wide and short copper trace.
11.2 Layout Example
GND: 0.052in2 Total
& 3 x 0.018in vias
COUT
0.050in trace
CIN
4 x 0.01in vias
VIN : 0.00925in2
& 3 x 0.018in vias
VOUT: 0.041in2 total
Figure 26. DBV Package PCB Layout Example
11.3 Power Dissipation and Junction Temperature
It is good design practice to estimate power dissipation and maximum expected junction temperature of the
TPS2069D. The system designer can control choices of package, proximity to other power dissipating devices,
and printed-circuit-board (PCB) design based on these calculations. These have a direct influence on maximum
junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by
system considerations. It is important to remember that these calculations do not include the effects of adjacent
heat sources, and enhanced or restricted air flow.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and
maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the
pad improve the efficiency and reliability of both device parts and the system. The following examples were used
to determine the θJACustom thermal impedances noted in Thermal Information. They were based on use of the
JEDEC high-k circuit board construction (2 signal and 2 plane) with 4, 1-oz. copper weight, layers.
As shown in Equation 1, the following procedure requires iteration because power loss is due to the internal
MOSFET I2 × RDS(ON), and RDS(ON) is a function of the junction temperature. As an initial estimate, use the
RDS(ON) at 125°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred
board construction from the Thermal Information table.
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Power Dissipation and Junction Temperature (continued)
TJ = TA + ((IOUT2 × RDS(ON)) × θJA)
where
•
•
•
•
•
IOUT = rated OUT pin current (A)
RDS(ON) = Power switch on-resistance at an assumed TJ (Ω)
TA = Maximum ambient temperature (°C)
TJ = Maximum junction temperature (°C)
θJA = Thermal resistance (°C/W)
(1)
If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using
the typical characteristic plot and recalculate.
If the resulting TJ is not less than 125°C, try a PCB construction and/or package with lower θJA.
18
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS2069DDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
18PF
TPS2069DDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
18PF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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