TPS2085D

TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 POWER-DISTRIBUTION SWITCHES FEATURES 1 • • • • • • • • • • • • 80-mΩ High-Side MOSFET Switch 500 mA Continuous Current per Channel Independent Thermal and Short-Circuit Protection With Overcurrent Logic Output Operating Range: 2.7-V to 5.5-V CMOS- and TTL-Compatible Enable Inputs 2.5-ms Typical Rise Time Undervoltage Lockout 10 μA Maximum Standby Supply Current Bidirectional Switch Available in 8-Pin and 16-Pin SOIC Packages Ambient Temperature Range, 0°C to 85°C ESD Protection DESCRIPTION The TPS2080, TPS2081, and TPS2082 dual and the TPS2085, TPS2086 and TPS2087 quad power-distribution switches are intended for applications where heavy capacitive loads and short circuits are likely to be encountered. The TPS208x devices incorporate 80-mΩ N-channel MOSFET high-side power switches for power-distribution systems that require multiple power switches in a single package. Each switch is controlled by an independent logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the TPS208x limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is present. The TPS208x devices are designed to current limit at 1.0-A load. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2007, Texas Instruments Incorporated TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS (1) DUAL POWER DISTRIBUTION SWITCHES ENABLE TA 0°C to 85°C EN1 EN2 Active high Active high Active high Active low Active low RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT (A) TYPICAL SHORT-CIRCUIT CURRENT LIMIT AT 25°C (A) 0.5 1.0 PACKAGED DEVICES SMALL OUTLINE (D) (2) TPS2080D Active low TPS2081D TPS2082D QUAD POWER DISTRIBUTION SWITCHES ENABLE TA 0°C to 85°C (1) (2) 2 EN1 EN2 EN3 DN4 Active high Active high Active high Active high Active high Active low Active high Active low Active low Active low Active low Active low RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT (A) TYPICAL SHORT-CIRCUIT CURRENT LIMIT AT 25°C (A) 0.5 1.0 PACKAGED DEVICES SMALL OUTLINE (D) (2) TPS2085D TPS2086D TPS2087D For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2081DR). Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 TPS2082 FUNCTIONAL BLOCK DIAGRAM Copyright © 2000–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD 3 TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 TPS2087 FUNCTIONAL BLOCK DIAGRAM 4 Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 TERMINAL FUNCTIONS DUAL POWER-DISTRIBUTION SWITCHES TERMINAL NAME NO. TPS2080 TPS2081 EN1 EN2 5 I/O DESCRIPTION TPS2082 4 I Enable input. Active low turns on power switch. 5 I Enable input. Active low turns on power switch. I Enable input. Active high turns on power switch. I Enable input. Active high turns on power switch. EN1 4 4 EN2 5 GND 1 1 1 I Ground IN1 2 2 2 I N-Channel MOSFET Drain IN2 3 3 3 I N-Channel MOSFET Drain OC 8 8 8 O Overcurrent. Open drain output active low OUT1 7 7 7 O Power-switch output OUT2 6 6 6 O Power-switch output QUAD POWER-DISTRIBUTION SWITCHES TERMINAL NAME NO. TPS2085 4 I Enable input. Active low turns on power switch. 13 13 I Enable input. Active low turns on power switch. 8 I Enable input. Active low turns on power switch. 9 I Enable input. Active low turns on power switch. I Enable input. Active high turns on power switch. I Enable input. Active high turns on power switch. I Enable input. Active high turns on power switch. I Enable input. Active high turns on power switch. EN3 EN4 DESCRIPTION TPS2087 EN1 EN2 I/O TPS2086 9 EN1 4 4 EN2 13 EN3 8 EN4 9 GNDA 1 1 1 Ground for IN1 and IN2 switch and circuitry GNDB 5 5 5 Ground for IN3 and IN4 switch and circuitry IN1 2 2 2 I N-channel MOSFET drain IN2 3 3 3 I N-channel MOSFET drain IN3 6 6 6 I N-channel MOSFET drain 8 IN4 7 7 7 I N-channel MOSFET drain OCA 16 16 16 O Overcurrent indicator for switch 1 and switch 2. Active-low open drain output. OCB 12 12 12 O Overcurrent indicator for switch 3 and switch 4. Active low open drain output OUT1 15 15 15 O Power-switch output OUT2 14 14 14 O Power-switch output OUT3 11 11 11 O Power-switch output OUT4 10 10 10 O Power-switch output Copyright © 2000–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD 5 TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 DETAILED DESCRIPTION POWER SWITCH The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5V). Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when disabled. The power switch supplies a minimum of 500 mA per switch. CHARGE PUMP An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7V and requires very little supply current. DRIVER The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range. ENABLE (ENx or ENx) The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current to less than 10 μA when a logic high is present on ENx or a logic low is present on ENx. A logic low input on ENx or logic high on ENx restores bias to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS logic levels. OVERCURRENT (OCx) The OCx open drain output is asserted (active low) when an overcurrent or over temperature condition is encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed. CURRENT SENSE A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant current mode and holds the current constant while varying the voltage on the load. THERMAL SENSE The TPS208x implements a dual thermal trip to allow fully independent operation of the power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The (OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs. UNDERVOLTAGE LOCKOUT A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch. 6 Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VI(IN) Input voltage range (2) VO(OUTx) Output voltage range (2) VI(ENx) or VI(ENx) Input voltage range IO(OUTx) Continuous output current (1) VALUE UNIT –0.3 to 6 V –0.3 to VI(IN) + 0.3 V –0.3 to 6 V Internally Limited Continuous total power dissipation See Dissipation Rating Table TJ Operating virtual junction temperature range Tstg Storage temperature range 0 to 125 °C –65 to 150 °C 260 °C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds Human body model ESD (1) (2) Electrostatic discharge protection 2 kV Machine model 200 V Charged device model (CDM) 750 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. DISSIPATION RATINGS TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING= D-8 725 mW 5.8 mW/°C 464 mW 377 mW D-16 1123 mW 9 mW/°C 719 mW 584 mW RECOMMENDED OPERATING CONDITIONS MIN MAX VI(IN) Input voltage 2.7 5.5 UNIT VI(ENx) or VI(ENx) Input voltage 0 5.5 V IO Continuous output current (per switch) 0 500 mA TJ Operating virtual junction temperature 0 125 °C V ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, VI(ENx) = 0 V, VI(ENx) = VI(INx) (unless otherwise noted) SUPPLY CURRENT PARAMETER TEST CONDITIONS MIN Supply current, low-level output No Load on OUT VI(ENx) = VI(IN), VI(ENx) = 0 V TJ = 25°C Supply current, high-level output No Load on OUT VI(ENx) = 0 V, VI(ENx) = VI(IN) TJ = 25°C Leakage current OUT connected to ground Reverse leakage current INx = high impedance Copyright © 2000–2007, Texas Instruments Incorporated TYP 0.025 –40°C ≤ TJ ≤ 125°C MAX 1 10 85 110 UNIT μA μA –40°C ≤ TJ ≤ 125°C 100 VI(ENx) = VI(IN), VI(ENx) = 0 V –40°C ≤ TJ ≤ 125°C 100 μA VI(ENx) = 0 V, VI(ENx) = VI(IN) TJ = 25°C 0.3 μA Submit Documentation Feedback Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD 7 TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (Continued) over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, VI(ENx) = 0 V, VI(ENx) = VI(INx) (unless otherwise noted) POWER SWITCH TEST CONDITIONS (1) PARAMETER rDS(on) Static drain-source on-state resistance tr Rise time, output tf Fall time, output (1) TYP MAX VI(IN) = 5 V, TJ = 25°C, IO = 0.5 A MIN 80 100 VI(IN) = 5 V, TJ = 85°C, IO = 0.5 A 90 120 VI(IN) = 5 V, TJ = 125°C, IO = 0.5 A 100 135 VI(IN) = 3.3 V, TJ = 25°C, IO = 0.5 A 90 125 VI(IN) = 3.3 V, TJ = 85°C, IO = 0.5 A 110 145 VI(IN) = 3.3 V, TJ = 125°C, IO = 0.5 A 120 165 VI(IN) = 5.5 V, RL = 10Ω, TJ = 125°C, CL = 1 μF 2.5 VI(IN) = 2.7 V, RL = 10Ω, TJ = 125°C, CL = 1 μF 3 VI(IN) = 5.5 V, RL = 10Ω, TJ = 125°C, CL = 1 μF 4.4 VI(IN) = 2.7 V, RL = 10Ω, TJ = 125°C, CL = 1 μF 2.5 UNIT mΩ ms ms Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. ENABLE INPUT VI(ENx) or VI(ENx) PARAMETER VIH TEST CONDITIONS MIN High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V TYP MAX UNIT 2 V 4.5 V ≤ VI(IN) ≤ 5.5 V 0.8 2.7 V ≤ VI(IN) ≤ 4.5 V 0.4 VIL Low-level input voltage II Input current VI(ENx) = 0 V and VI(ENx) = VI(IN), or VI(ENx) = VI(IN) and VI(ENx) = 0 V 0.5 μA ton Turnon time CL = 100 μF, RL = 10 μF 20 ms toff Turnon time CL = 100 μF, RL = 10 μF 40 ms –0.5 V CURRENT LIMIT TEST CONDITIONS (1) PARAMETER IOS (1) Short-circuit output current VI(IN) = 5 V, OUT connected to GND, Device enabled into short circuit MIN TYP MAX 0.7 1 1.3 UNIT A Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. UNDERVOLTAGE LOCKOUT PARAMETER TEST CONDITIONS Low-level input voltage Hysteresis MIN TYP 2 TJ = 25°C MAX 2.5 100 UNIT V mV OVERCURRENT OCx PARAMETER Sink current (1) TEST CONDITIONS MIN TYP MAX UNIT VO = 5 V 10 Output low voltage IO = 5 mA, VOL(OCx) 0.5 V Off-state current (1) VO = 5 V, VO = 3.3 V 1 μA (1) 8 mA Specified by design, not production tested. Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION Figure 1. Test Circuit and Voltage Waveforms Figure 2. Turnon Delay and Rise Time With 0.1-μF Load Copyright © 2000–2007, Texas Instruments Incorporated Figure 3. Turnoff Delay and Fall Time With 0.1-μF Load Submit Documentation Feedback Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD 9 TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) 10 Figure 4. Turnon Delay and Rise Time With 1-μF Load Figure 5. Turnoff Delay and Fall Time With 1-μF Load Figure 6. TPS2080, Short-Circuit Current, Device Enabled Into Short Figure 7. TPS2080, Threshold Trip Current With Ramped Load on Enabled Device Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 8. OC Response With Ramped Load on Enabled Device Figure 9. Inrush Current With 100-μF, 220-μF and 470-μF Load Capacitance Figure 10. 4-Ω Load Connected to Enabled Device Figure 11. 1-Ω Load Connected to Enabled Device Copyright © 2000–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD 11 TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS 12 TURNON DELAY TIME vs INPUT VOLTAGE TURNOFF DELAY TIME vs INPUT VOLTAGE Figure 12. Figure 13. RISE TIME vs INPUT VOLTAGE FALL TIME vs INPUT VOLTAGE Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE Figure 16. Figure 17. STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE INPUT-TO-OUTPUT VOLTAGE vs LOAD CURRENT Figure 18. Figure 19. Copyright © 2000–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD 13 TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) 14 SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE THRESHOLD TRIP CURRENT vs INPUT VOLTAGE Figure 20. Figure 21. UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE CURRENT LIMIT RESPONSE vs PEAK CURRENT Figure 22. Figure 23. Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 APPLICATION INFORMATION Figure 24. Typical Application POWER-SUPPLY CONSIDERATIONS A 0.01-μF to 0.1-μF ceramic bypass capacitor between INx and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients. OVERCURRENT A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 6). The TPS208x senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figure 10 and Figure 11). After the current-limit circuit has tripped (reached the overcurrent trip threshold) the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 8). The TPS208x is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC RESPONSES The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from the inrush current flowing through the device, charging the downstream capacitor. The TPS208x devices are designed to reduce false overcurrent reporting. An internal overcurrent transient filter eliminates the need to use external components to remove unwanted pulses. Using low-ESR electrolytic capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing a low impedance energy source, thereby reducing erroneous overcurrent reporting. Copyright © 2000–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD 15 TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 Figure 25. Typical Circuit for OC Pin POWER DISSIPATION AND JUNCTION TEMPERATURE The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistance of these packages is high compared to that of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power dissipation per switch can be calculated by: PD = rDS(on) × I2 Multiply this number by the total number of switches being used, to get the total power dissipation coming from the N-channel MOSFETs. Finally, calculate the junction temperature: TJ = PD × RθJA + TA Where: TA = Ambient Temperature °C RθJA = Thermal resistance SOIC = 172°C/W (for 8 pin), 111°C/W (for 16 pin) PD = Total power dissipation based on number of switches being used. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. THERMAL PROTECTION Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS208x into constant current mode, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The TPS208x implements a dual thermal trip to allow fully independent operation of the power distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach 160°C, both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or overcurrent occurs. 16 Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD www.ti.com SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007 UNDERVOLTAGE LOCKOUT (UVLO)l An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce EMI and voltage overshoots. GENERIC HOT-PLUG APPLICATIONS (see Figure 26) In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS208x, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS208x also ensures the switch will be off after the card has been removed, and the switch will be off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or module. Figure 26. Typical Hot-Plug Implementation By placing the TPS208x between the VCC input and the rest of the circuitry, the input power will reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device. Copyright © 2000–2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD 17 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS2080D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2080 Samples TPS2080DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2080 Samples TPS2080DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2080 Samples TPS2081D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2081 Samples TPS2082D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2082 Samples TPS2082DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2082 Samples TPS2085D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2085 Samples TPS2085DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2085 Samples TPS2087D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2087 Samples TPS2087DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 2087 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of