TPS2113APWR

TPS2112A TPS2113A www.ti.com SBVS045C – MARCH 2004 – REVISED MAY 2012 AUTOSWITCHING POWER MUX Check for Samples: TPS2112A, TPS2113A FEATURES APPLICATIONS • • • • • • • • 1 2 • • • • • • • • • • Two-Input, One-Output Power Multiplexer with Low rDS(on) Switches: – 84 mΩ Typ (TPS2113A) – 120 mΩ Typ (TPS2112A) Reverse and Cross-Conduction Blocking Wide Operating Voltage: 2.8 V to 5.5 V Low Standby Current: 0.5 μA Typ Low Operating Current: 55 μA Typ Adjustable Current Limit Controlled Output Voltage Transition Time: – Limits Inrush Current – Minimizes Output Voltage Hold-Up Capacitance CMOS- and TTL-Compatible Control Inputs Auto-Switching Operating Mode Thermal Shutdown Available in TSSOP-8 and 3-mm × 3-mm SON-8 Packages PCs PDAs Digital Cameras Modems Cell Phones Digital Radios MP3 Players DESCRIPTION The TPS211xA family of power multiplexers enables seamless transition between two power supplies (such as a battery and a wall adapter), each operating at 2.8 V to 5.5 V and delivering up to 2 A, depending on package. The TPS211xA family includes extensive protection circuitry, including userprogrammable current limiting, thermal protection, inrush current control, seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly simplify designing power multiplexer applications. space TYPICAL APPLICATION Switch Status IN1: 2.8 V to 5.5 V TPS2113A 0.1 mF R1 8 1 STAT IN1 7 2 EN OUT 3 6 VSNS IN2 5 4 ILIM CL RL GND RILIM IN2: 2.8 V to 5.5 V 0.1 mF 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2012, Texas Instruments Incorporated TPS2112A TPS2113A SBVS045C – MARCH 2004 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS FEATURE TPS2110A TPS2111A TPS2112A 0.31 A to 0.75 A 0.63 A to 1.25 A 0.31 A to 0.75 A Manual Yes Yes Automatic Yes Yes No No Yes Current Limit Adjustment Range Switching Modes Switch Status Output TPS2113A TPS2114A TPS2115A 0.63 A to 2 A 0.31 A to 0.75 A 0.63 A to 2 A No No Yes Yes Yes Yes Yes Yes Yes Yes Yes DEVICE INFORMATION (1) TA PACKAGE IOUT (A) ORDERING NUMBER PACKAGE MARKING 0.75 TPS2112APW 2112A 1.25 TPS2113APW 2113A 2 TPS2113ADRB PTOI TSSOP-8 (PW) −40°C to +85°C SON-8 (DRB) (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over recommended junction temperature range, unless otherwise noted. TPS2112A, TPS2113A UNIT −0.3 to 6 V Input voltage range at pins IN1, IN2, EN, VSNS, ILIM (2) (2) −0.3 to 6 V 5 mA TPS2112APW 0.9 A TPS2113APW 1.5 A 2.5 A Output voltage range, VO(OUT), VO(STAT) Output sink current, IO(STAT) Continuous output current, IO TPS2113ADRB, TJ ≤ 105°C Continuous total power dissipation See Dissipation Ratings table Junction temperature ESD (1) (2) Internally Limited Human body model (HBM) Charged device model (CDM) 2 kV 500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. DISSIPATION RATINGS PACKAGE TSSOP-8 (PW) SON-8 (DRB) (1) 2 (1) DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 3.9 mW/°C 387 mW 213 mW 155 mW 25.0 mW/°C 2.50 mW 1.38 mW 1.0 W See TI application note SLMA002 for mounting recommendations. Copyright © 2004–2012, Texas Instruments Incorporated TPS2112A TPS2113A www.ti.com SBVS045C – MARCH 2004 – REVISED MAY 2012 RECOMMENDED OPERATING CONDITIONS TPS2112A, TPS2113A MIN Input voltage at IN1, VI(IN1) Input voltage at IN2, VI(IN2) UNIT 5.5 VI(IN2) < 2.8 V 2.8 5.5 VI(IN1) ≥ 2.8 V 1.5 5.5 VI(IN1) < 2.8 V 2.8 5.5 0 5.5 TPS2112APW 0.31 0.75 TPS2113APW 0.63 1.25 TPS2113ADRB, TJ ≤ 105°C 0.63 2 A –40 125 °C Operating virtual junction temperature, TJ (1) MAX 1.5 Input voltage: VI(EN), VI(VSNS) Nominal current limit adjustment range, IO(OUT) (1) NOM VI(IN2) ≥ 2.8 V V V V A Minimum recommended current limit is based on accuracy considerations. ELECTRICAL CHARACTERISTICS: Power Switch Over recommended operating junction temperature, RILIM = 400 Ω, unless otherwise noted. TPS2112A PARAMETER Drain-source on-state resistance (INx−OUT) (1) TEST CONDITIONS TJ = 25°C, IL = 500 mA rDS(on) (1) TJ = 125°C, IL = 500 mA MIN TPS2113A TYP MAX MIN TYP MAX VI(IN1) = VI(IN2) = 5.0 V 120 140 84 110 VI(IN1) = VI(IN2) = 3.3 V 120 140 84 110 VI(IN1) = VI(IN2) = 2.8 V 120 140 84 110 VI(IN1) = VI(IN2) = 5.0 V 220 150 VI(IN1) = VI(IN2) = 3.3 V 220 150 VI(IN1) = VI(IN2) = 2.8 V 220 150 UNIT mΩ mΩ The TPS211xA can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances. ELECTRICAL CHARACTERISTICS Over recommended operating junction temperature, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise noted. TPS2112A, TPS2113A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUTS (EN) High-level input voltage VIH Low-level input voltage VIL Input current 2 V 0.7 EN = High, sink current EN = Low, source current 1 0.5 1.4 5 VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V 55 90 VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, 1 12 V μA SUPPLY AND LEAKAGE CURRENTS Supply current from IN1 (operating) Supply current from IN2 (operating) μA VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V 75 VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V 1 VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V 1 VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V 75 μA VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V 1 12 VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V 55 90 Copyright © 2004–2012, Texas Instruments Incorporated 3 TPS2112A TPS2113A SBVS045C – MARCH 2004 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise noted. TPS2112A, TPS2113A PARAMETER TEST CONDITIONS MIN TYP MAX 0.5 2 UNIT SUPPLY AND LEAKAGE CURRENTS, Continued Quiescent current from IN1 (standby) Quiescent current from IN2 (standby) EN = High (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V μA EN = High (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V 1 EN = High (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V 1 μA EN = High (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V 0.5 2 Forward leakage current from IN1 (measured from OUT to GND) EN = High (inactive), VI(IN1) = 5.5 V, IN2 open, VO(OUT) = 0 V (shorted), TJ = 25°C 0.1 5 μA Forward leakage current from IN2 (measured from OUT to GND) EN = High (inactive), VI(IN2) = 5.5 V, IN1 open, VO(OUT) = 0 V (shorted), TJ = 25°C 0.1 5 μA Reverse leakage current to INx (measured from INx to GND) EN = High (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, TJ = 25°C 0.3 5 μA μA STAT OUTPUT Leakage current VO(STAT) = 5.5 V 0.01 1 Saturation voltage II(STAT) = 2 mA, IN1 switch is on 0.13 0.4 Deglitch time (falling edge only) V μs 150 CURRENT LIMIT CIRCUIT TPS2112A Current limit accuracy TPS2113A Current limit settling time td Input current at ILIM RILIM = 400 Ω 0.51 0.63 0.80 RILIM = 700 Ω 0.30 0.36 0.50 RILIM = 400 Ω 0.95 1.25 1.56 RILIM = 700 Ω 0.47 0.71 0.99 Time for short-circuit output current to settle within 10% of its steady state value. VI(ILIM) = 0 V 1 –15 A A ms 0 μA VSNS COMPARATOR VSNS threshold voltage VI(VSNS) ↑ 0.78 0.80 0.82 VI(VSNS) ↓ 0.735 0.755 0.775 VSNS comparator hysteresis 30 Deglitch of VSNS comparator (both ↑ ↓ ) Input current 90 0 V ≤ VI(VSNS) ≤ 5.5 V 60 150 –1 V mV 220 μs 1 μA UVLO IN1 and IN2 UVLO Falling edge IN1 and IN2 UVLO hysteresis Internal VDD UVLO (the higher of IN1 and IN2) Falling edge 4 1.35 30 57 65 2.4 2.53 30 Falling edge 1.25 1.30 Rising edge Internal VDD UVLO hysteresis UVLO deglitch for IN1, IN2 1.15 Rising edge 2.58 2.8 50 75 110 V mV V mV μs Copyright © 2004–2012, Texas Instruments Incorporated TPS2112A TPS2113A www.ti.com SBVS045C – MARCH 2004 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise noted. TPS2112A, TPS2113A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 80 100 120 mV REVERSE CONDUCTION BLOCKING Minimum output-to-input voltage difference to block switching ΔVO(I_block) EN = high, VI(IN1) = 3.3 V and VI(IN2) = VI(VSNS) = 0 V. Connect OUT to a 5-V supply through a series 1-kΩ resistor. Let EN = low. Slowly decrease the supply voltage until OUT connects to IN1. THERMAL SHUTDOWN Thermal shutdown threshold TPS211xA is in current limit. 135 Recovery from thermal shutdown TPS211xA is in current limit. 125 °C °C Hysteresis 10 °C IN2−IN1 COMPARATORS Hysteresis of IN2−IN1 comparator 0.1 Deglitch of IN2−IN1 comparator (both ↑ ↓) 10 20 0.2 V 50 μs SWITCHING CHARACTERISTICS Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted. TPS2112A PARAMETER TEST CONDITIONS TPS2113A MIN TYP MAX MIN TYP MAX 0.5 1.0 1.5 1 1.8 3 ms 0.35 0.5 0.7 0.5 1 2 ms 60 40 60 μs tR Output rise time from an enable VI(IN1) = VI(IN2) = 5 V, VI(SNS) = 1.5 V TJ = 25°C, CL = 1 μF, IL = 500 mA; see Figure 1(a). tF Output fall time from a disable VI(IN1) = VI(IN2) = 5 V, VI(SNS) = 1.5 V TJ = 25°C, CL = 1 μF, IL = 500 mA; see Figure 1(a). 40 UNIT tT Transition time IN1 to IN2 transition, VI(IN1) = 3.3 V, VI(IN2) = 5 V, VI(EN) = 0 V TJ = 125°C, CL = 10 μF, IL = 500 mA; measure transition time as 10% to 90% rise time or from 3.4 V to 4.8 V on VO(OUT). See Figure 1(b). tPLH1 Turn-on propagation delay from an enable VI(IN1) = VI(IN2) = 5 V Measured from enable to 10% of VO(OUT), VI(SNS) = 1.5 V TJ = 25°C, CL = 10 μF, IL = 500 mA; see Figure 1(a). 0.5 1 ms tPHL1 Turn-off propagation delay from a disable VI(IN1) = VI(IN2) = 5 V Measured from disable to 90% of VO(OUT), VI(SNS) = 1.5 V TJ = 25°C, CL = 10 μF, IL = 500 mA; see Figure 1(a). 3 5 ms tPLH2 Switch-over rising propagation delay Logic 1 to Logic 0 transition on VSNS, VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(EN) = 0 V, Measured from VSNS to 10% of VO(OUT) TJ = 25°C, CL = 10 μF, IL = 500 mA; see Figure 1(c). 40 100 tPHL2 Switch-over falling propagation delay Logic 0 to Logic 1 transition on VSNS, VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(EN) = 0 V, Measured from VSNS to 90% of VO(OUT) TJ = 25°C, CL = 10 μF, IL = 500 mA; see Figure 1(c). 3 10 Copyright © 2004–2012, Texas Instruments Incorporated 2 2 40 100 μs 5 10 ms 5 TPS2112A TPS2113A SBVS045C – MARCH 2004 – REVISED MAY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION TIMING WAVEFORMS VO(OUT) 90% 90% 10% 0V 10% tR tPLH1 tF tPHL1 EN Switch Off Switch Enabled Switch Off (a) 5V 4.8 V VO(OUT) 3.4 V 3.3 V tT VSNS Switch #1 Enabled Switch #2 Enabled (b) 5V VO(OUT) 1.5 V 4.65 V 1.85 V tPLH2 tPHL2 VSNS Switch #1 Enabled Switch #2 Enabled Switch #1 Enabled (c) Figure 1. Propagation Delays and Transition Timing Waveforms 6 Copyright © 2004–2012, Texas Instruments Incorporated TPS2112A TPS2113A www.ti.com SBVS045C – MARCH 2004 – REVISED MAY 2012 DEVICE INFORMATION TRUTH TABLE (1) (2) EN VI(VSNS) > 0.8 V (1) VI(IN2) > VI(IN1) STAT OUT (2) 0 0 Yes X 0 IN1 No No 0 IN1 0 No Yes Hi-Z IN2 1 X X 0 Hi-Z X = Don’t care. The undervoltage lockout circuit causes the output (OUT) to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or if neither of the supplies exceeds the internal VDD UVLO. PIN CONFIGURATIONS PW PACKAGE TSSOP-8 (TOP VIEW) STAT DRB PACKAGE SON-8 (TOP VIEW) 8 1 IN1 EN 2 7 OUT VSNS 3 6 IN2 ILIM 4 5 GND STAT 1 8 IN1 EN 2 7 OUT GND VSNS 3 6 IN2 ILIM 4 5 GND Table 1. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION TTL- and CMOS-compatible input with a 1-μA pull-up. The Truth Table illustrates the functionality of EN. EN 2 I GND 5 Power IN1 8 I Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. IN2 6 I Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. ILIM 4 I A resistor (RILIM) from ILIM to GND sets the current limit (IL) to 250/RILIM and 500/RILIM for the TPS2112A and TPS2113A, respectively. OUT 7 O Power switch output STAT 1 O STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z (that is, EN is equal to logic '0') VSNS 3 I An internal power FET connects OUT to IN1 if the VSNS voltage is greater than 0.8 V. Otherwise, the FET connects OUT to the higher of IN1 and IN2. The Truth Table illustrates the functionality of VSNS. Pad — Power DRB package only. Connect to GND. Must be connected to large copper area in order to meet stated package dissipation ratings. Ground Copyright © 2004–2012, Texas Instruments Incorporated 7 TPS2112A TPS2113A SBVS045C – MARCH 2004 – REVISED MAY 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM Internal VDD 1 mA Vf = 0 V IN1 IN2 Vf = 0 V IO(OUT) Q1 8 7 OUT Q2 6 Charge Pump k ´ IO(OUT) TPS2112A: k = 0.2% TPS2113A: k = 0.1% VDD UVLO ILIM 0.5 V Q2 is on EN2 EN1 Q1 is on 100 mV UVLO (VDD) VO(OUT) > VI(INx) UVLO (IN2) + IN1 UVLO 0.6 V Cross-Conduction Detector + IN2 UVLO 4 UVLO (IN1) Control Logic EN VSNS 2 EN1 Thermal Sense IN2 3 VI(SNS) > 0.8 V IN1 0.8 V GND 8 5 1 STAT Q2 is on Copyright © 2004–2012, Texas Instruments Incorporated TPS2112A TPS2113A www.ti.com SBVS045C – MARCH 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS OUTPUT SWITCHOVER RESPONSE 3.3 V TPS2113A 1 NC f = 28 Hz 22% Duty Cycle VI(VSNS) 2 V/div 2 3 4 STAT EN VSNS ILIM 0.1 mF 8 IN1 7 OUT 6 IN2 5 GND 1 mF 50 W 400 W VO(OUT) 2 V/div 5V 0.1 mF Output Switchover Response Test Circuit t - Time - 1 ms/div Figure 2. OUTPUT TURN-ON RESPONSE VI(EN) 2 V/div 5V TPS2113A 1 f = 28 Hz 78% Duty Cycle NC 2 3 4 STAT EN VSNS ILIM 0.1 mF IN1 OUT IN2 GND 8 7 6 5 1 mF 50 W 400 W VO(OUT) 2 V/div Output Turn-On Response Test Circuit t - Time - 2 ms/div Figure 3. Copyright © 2004–2012, Texas Instruments Incorporated 9 TPS2112A TPS2113A SBVS045C – MARCH 2004 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT SWITCHOVER VOLTAGE DROOP VI(VSNS) 2 V/div CL = 1 mF VO(OUT) 2 V/div CL = 0 m F t - Time - 40 ms/div 5V TPS2113A SW1 1 NC f = 580 Hz 90% Duty Cycle 2 3 4 0.1 mF STAT EN IN1 OUT VSNS ILIM IN2 GND 1 kW 8 7 6 CL 5 50 W 400 W 0.1 mF Output Switchover Voltage Droop Test Circuit Figure 4. Note: 10 To initialize the TPS2113A for this test, set input VSNS equal to 0 V, turn on the 5-V supply, and then turn on switch SW1. Copyright © 2004–2012, Texas Instruments Incorporated TPS2112A TPS2113A www.ti.com SBVS045C – MARCH 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) OUTPUT SWITCHOVER VOLTAGE DROOP vs LOAD CAPACITANCE 5.0 VI = 5 V DVO(OUT) - Output Voltage Droop - V 4.5 4.0 3.5 3.0 RL= 10 W 2.5 2.0 1.5 RL= 50 W 1.0 0.5 0 0.1 1 10 100 CL - Load Capacitance - mF VI SW1 TPS2113A 1 NC f = 28 Hz 50% Duty Cycle 2 3 4 0.1 mF STAT EN IN1 OUT VSNS ILIM IN2 GND 1 kW 8 7 6 5 400 W 0.1 mF 0.1 mF 1 mF 10 mF 47 mF 100 mF 50 W 10 W Output Switchover Voltage Droop Test Circuit Figure 5. Note: To initialize the TPS2113A for this test, set input VSNS equal to 0 V, turn on the VI supply, and then turn on switch SW1. Copyright © 2004–2012, Texas Instruments Incorporated 11 TPS2112A TPS2113A SBVS045C – MARCH 2004 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) AUTO SWITCHOVER VOLTAGE DROOP VI(IN1) 2 V/div 5V TPS2113A 0.1 mF 1 kW 1 2 f = 220 Hz 20% Duty Cycle 3 4 VO(OUT) 2 V/div 400 W STAT IN1 OUT EN VSNS ILIM IN2 GND 8 7 6 VOUT 3.3 V 10 mF 5 50 W 0.1 mF 75% less output voltage droop compared to TPS2113 Auto Switchover Voltage Droop Test Circuit t - Time - 250 ms/div Figure 6. 12 Copyright © 2004–2012, Texas Instruments Incorporated TPS2112A TPS2113A www.ti.com SBVS045C – MARCH 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) INRUSH CURRENT vs LOAD CAPACITANCE 300 II - Inrush Current - mA 250 200 VI = 5 V 150 VI = 3.3 V 100 50 0 20 0 60 40 80 100 CL - Load Capacitance - mF VI TPS2113A f = 28 Hz 90% Duty Cycle NC 1 2 3 4 0.1 mF STAT EN IN1 OUT VSNS ILIM IN2 GND 8 To Oscilloscope 7 6 5 50 W 400 W 0.1 mF 1 mF 10 mF 47 mF 100 mF Output Capacitor Inrush Current Test Circuit Figure 7. Copyright © 2004–2012, Texas Instruments Incorporated 13 TPS2112A TPS2113A SBVS045C – MARCH 2004 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCH ON-RESISTANCE vs JUNCTION TEMPERATURE SWITCH ON-RESISTANCE vs SUPPLY VOLTAGE 120 180 TPS2112A rDS(on) - Switch-On Resistance - mW rDS(on) - Switch-On Resistance - mW 115 160 140 TPS2112A 120 100 TPS2113A 80 110 105 100 95 90 TPS2113A 85 80 60 -50 0 50 100 2 150 TJ - Junction Temperature - °C 4 5 6 VI(INx) - Supply Voltage - V Figure 8. Figure 9. IN1 SUPPLY CURRENT vs SUPPLY VOLTAGE IN1 SUPPLY CURRENT vs SUPPLY VOLTAGE 60 0.96 Device Disabled VI(IN2) = 0 V IO(OUT) = 0 A IN1 Switch is On VI(IN2) = 0 V IO(OUT) = 0 A 58 II(IN1) - IN1 Supply Current - mA 0.94 II(IN1) - IN1 Supply Current - mA 3 0.92 0.90 0.88 0.86 56 54 52 50 48 46 44 0.84 42 40 0.82 2 3 4 5 VI(IN1) - IN1 Supply Voltage - V Figure 10. 14 6 2 3 4 5 6 VI(IN1) - Supply Voltage - V Figure 11. Copyright © 2004–2012, Texas Instruments Incorporated TPS2112A TPS2113A www.ti.com SBVS045C – MARCH 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs JUNCTION TEMPERATURE SUPPLY CURRENT vs JUNCTION TEMPERATURE 1.2 70 II(INx) - Supply Current - mA II(INx) - Supply Current - mA 1.0 80 Device Disabled VI(IN1) = 5.5 V VI(IN2) = 3.3 V IO(OUT) = 0 A II(IN1) = 5.5 V 0.8 0.6 0.4 60 IN1 Switch is On VI(IN1) = 5.5 V VI(IN2) = 3.3 V IO(OUT) = 0 A II(IN1) 50 40 30 20 0.2 10 II(IN2) = 3.3 V 0 -50 0 50 100 TJ - Junction Temperature - °C Figure 12. Copyright © 2004–2012, Texas Instruments Incorporated 150 0 -50 II(IN2) 0 50 100 150 TJ - Junction Temperature - °C Figure 13. 15 TPS2112A TPS2113A SBVS045C – MARCH 2004 – REVISED MAY 2012 www.ti.com APPLICATION INFORMATION Some applications have two energy sources, one of which should be used in preference to another. Figure 14 shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once the voltage on IN1 falls below this value, the TPS2112A/3A will select the higher of the two supplies. This usually means that the TPS2112A/3A will swap to IN2. Switch Status IN1: 2.8 V to 5.5 V TPS2113A 0.1 mF 8 1 STAT IN1 7 2 R1 EN OUT 3 6 VSNS IN2 ILIM RL CL 5 4 R2 R3 GND RILIM IN2: 2.8 V to 5.5 V 0.1 mF Figure 14. Auto-Selecting for a Dual Power-Supply Application In Figure 15, the multiplexer selects between two power supplies based upon the VSNS logic signal. OUT connects to IN1 if VSNS is logic '1'; otherwise, OUT connects to IN2 if VIN2 is greater than VIN1. The logic thresholds for the VSNS terminal are compatible with both TTL and CMOS logic. Switch Status IN1: 2.8 V to 5.5 V TPS2113A 0.1 mF R1 8 1 STAT IN1 7 2 EN OUT 3 6 VSNS IN2 CL 5 4 ILIM RL GND RILIM IN2: 2.8 V to 5.5 V 0.1 mF Figure 15. Manually Switching Power Sources 16 Copyright © 2004–2012, Texas Instruments Incorporated TPS2112A TPS2113A www.ti.com SBVS045C – MARCH 2004 – REVISED MAY 2012 DETAILED DESCRIPTION AUTO-SWITCHING MODE The TPS2112A/3A only supports the auto-switching mode. In this mode, OUT connects to IN1 if VI(VSNS) is greater than 0.8 V, otherwise OUT connects to the higher of IN1 and IN2. The VSNS terminal includes hysteresis equal to 3.75% to 7.5% of the threshold selected for transition from the primary supply to the higher of the two supplies. This hysteresis helps avoid repeated switching from one supply to the other due to resistive drops. N-CHANNEL MOSFETs Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so output-toinput current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET switch if the output voltage is greater than the input voltage. CROSS-CONDUCTION BLOCKING The switching circuitry ensures that both power switches will never conduct at the same time. A comparator monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source voltage of the other FET is below the turn-on threshold voltage. REVERSE-CONDUCTION BLOCKING When the TPS211xA switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS211xA will not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output voltage. CHARGE PUMP The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages. A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET. CURRENT LIMITING A resistor RILIM from ILIM to GND sets the current limit to 250/RILIM and 500/RILIM for the TPS2112A and TPS2113A, respectively. Setting resistor RILIM equal to zero is not recommended as that disables current limiting. OUTPUT VOLTAGE SLEW-RATE CONTROL The TPS2112A/3A slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state (see the Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the connector power contacts, when hot-plugging a load such as a PCI card. The TPS2112A/3A slews the output voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output voltage droop and reduces the output voltage hold-up capacitance requirement. Copyright © 2004–2012, Texas Instruments Incorporated 17 TPS2112A TPS2113A SBVS045C – MARCH 2004 – REVISED MAY 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2010) to Revision C Page • Changed description of power supplies in Description section ............................................................................................ 1 • Changed Current Limit Adjustment Range parameter TPS2113A and TPS2115A specifications in Available Options table ...................................................................................................................................................................................... 2 • Added IOUT column to Device Information table, changed table name ................................................................................. 2 • Changed Continuous output current parameter in Absolute Maximum Ratings table .......................................................... 2 • Changed Current limit adjustment range parameter in Recommended Operating Conditions table ................................... 3 • Added footnote 1 to Recommended Operating Conditions table ......................................................................................... 3 • Changed second paragraph in Application Information section ......................................................................................... 16 Changes from Revision A (February, 2006) to Revision B Page • Updated document to current format .................................................................................................................................... 1 • Deleted package information from Available Options table .................................................................................................. 2 • Revised Ordering Information table ...................................................................................................................................... 2 • Deleted storage temperature, operating virtual junction temperature range, and lead temperature specifications from, added electrostatic discharge and junction temperature specifications to Absolute Maximum Ratings table; deleted ESD Protection table ................................................................................................................................................ 2 • Added DRB package information and footnote to Dissipation Ratings table ....................................................................... 2 18 Copyright © 2004–2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 14-Nov-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS2112APW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2112A TPS2112APWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2112A TPS2113ADRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PTOI TPS2113ADRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PTOI TPS2113APW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2113A TPS2113APWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2113A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of