TPS2115ADRBTG4

TPS2114A TPS2115A www.ti.com SBVS044F – MARCH 2004 – REVISED MAY 2012 AUTOSWITCHING POWER MUX Check for Samples: TPS2114A, TPS2115A FEATURES APPLICATIONS • • • • • • • • 1 2 • • • • • • • • • • Two-Input, One-Output Power Multiplexer with Low rDS(on) Switches: – 120 mΩ Typ (TPS2114A) – 84 mΩ Typ (TPS2115A) Reverse and Cross-Conduction Blocking Wide Operating Voltage Range: 2.8 V to 5.5 V Low Standby Current: 0.5-μA Typ Low Operating Current: 55-μA Typ Adjustable Current Limit Controlled Output Voltage Transition Times Limit Inrush Current and Minimize Output Voltage Hold-Up Capacitance CMOS- and TTL-Compatible Control Inputs Manual and Auto-Switching Operating Modes Thermal Shutdown Available in TSSOP-8 and 3-mm × 3-mm SON-8 Packages PCs PDAs Digital Cameras Modems Cell Phones Digital Radios MP3 Players DESCRIPTION The TPS211xA family of power multiplexers enables seamless transition between two power supplies (such as a battery and a wall adapter), each operating at 2.8 V to 5.5 V and delivering up to 2 A, depending on package. The TPS211xA family includes extensive protection circuitry, including userprogrammable current limiting, thermal protection, inrush current control, seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly simplify designing power multiplexer applications. TYPICAL APPLICATION Switch Status IN1: 2.8 - 5.5 V TPS2115APW 1 STAT 2 3 4 D0 D1 IN1 OUT 7 IN2 6 CL 5 ILIM R1 0.1 mF 8 RL GND RILIM IN2: 2.8 - 5.5 V 0.1 mF 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2012, Texas Instruments Incorporated TPS2114A TPS2115A SBVS044F – MARCH 2004 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION (1) TA –40°C to 85°C PACKAGE TSSOP-8 (PW) IOUT ORDERING NUMBER MARKING 0.75 TPS2114APW 2114A 1.25 TPS2115APW 2115A 2 TPS2115ADRB CGF SON-8 (DRB) (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over recommended junction temperature range (unless otherwise noted). VALUE IN1, IN2, D0, D1, ILIM (2) Voltage VO(OUT), VO(STAT) (2) MIN MAX –0.3 6 –0.3 6 V 5 mA Output sink, IO(STAT) Current 0.9 A Continuous output, IO (TPS2115APW) 1.5 A Continuous output, IO (TPS2115ADRB), TJ ≤ 105°C 2.5 A Continuous total Temperature Operating virtual junction, TJ (1) (2) V Continuous output, IO (TPS2114APW) Power dissipation See Power Dissipation Ratings table –40 Human body model, HBM ESD ratings UNIT Charge device model, CDM 125 °C 2 kV 500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. AVAILABLE OPTIONS FEATURE TPS2114A TPS2115A 0.31 A to 0.75 A 0.63 A to 2 A Manual Yes Yes Automatic Yes Yes Yes Yes Current limit adjustment range Switching modes Switch status output Package 2 TSSOP-8 TSSOP-8 SON-8 Copyright © 2004–2012, Texas Instruments Incorporated TPS2114A TPS2115A www.ti.com SBVS044F – MARCH 2004 – REVISED MAY 2012 PACKAGE DISSIPATION RATINGS DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING TSSOP-8 (PW) 3.9 mW/°C 387 mW 213 mW 155 mW SON-8 (DRB) 25.0 mW/°C 2.50 W 1.38 W 1.0 W PACKAGE RECOMMENDED OPERATING CONDITIONS MIN Input voltage at IN1, VI(IN1) Input voltage at IN2, VI(IN2) UNIT 1.5 5.5 V VI(IN2) < 2.8 V 2.8 5.5 V VI(IN1) ≥ 2.8 V 1.5 5.5 V VI(IN1) < 2.8 V 2.8 5.5 V 0 5.5 V TPS2114APW 0.31 0.75 A TPS2115APW 0.63 1.25 A TPS2115ADRB, TJ ≤ 105°C 0.63 2 A –40 125 °C Operating virtual junction temperature, TJ (1) MAX VI(IN2) ≥ 2.8 V Input voltage, VI(DO), VI(D1) Nominal current limit adjustment range, IO(OUT) (1) NOM Minimum recommended current is based on accuracy considerations. ELECTRICAL CHARACTERISTICS: POWER SWITCH Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted. TPS2114A PARAMETER rDS(on) (1) (1) Drain-source on-state resistance (INx−OUT) TEST CONDITIONS MIN TPS2115A TYP MAX TJ = 25°C, IL = 500 mA, VI(IN1) = VI(IN2) = 5.0 V 120 TJ = 25°C, IL = 500 mA, VI(IN1) = VI(IN2) = 3.3 V 120 TJ = 25°C, IL = 500 mA, VI(IN1) = VI(IN2) = 2.8 V 120 MIN TYP MAX UNIT 140 84 110 mΩ 140 84 110 mΩ 140 84 110 mΩ TJ = 125°C, IL = 500 mA, VI(IN1) = VI(IN2) = 5.0 V 220 150 mΩ TJ = 125°C, IL = 500 mA, VI(IN1) = VI(IN2) = 3.3 V 220 150 mΩ TJ = 125°C, IL = 500 mA, VI(IN1) = VI(IN2) = 2.8 V 220 150 mΩ The TPS211xA can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances. Copyright © 2004–2012, Texas Instruments Incorporated 3 TPS2114A TPS2115A SBVS044F – MARCH 2004 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted. TPS2114A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUTS (D0 AND D1) VIH High-level input voltage VIL Low-level input voltage Input current at D0 or D1 2 V 0.7 V 1 µA 1.4 5 μA D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 55 90 μA D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 1 12 μA D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 75 μA D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 1 μA D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 1 μA D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 75 μA D0 or D1 = high, sink current D0 or D1 = low, source current 0.5 SUPPLY AND LEAKAGE CURRENTS Supply current from IN1 (operating) Supply current from IN2 (operating) Quiescent current from IN1 (STANDBY) Quiescent current from IN2 (STANDBY) D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 1 12 μA D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 55 90 μA D0 = D1 = high (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 0.5 2 μA D0 = D1 = high (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 1 μA D0 = D1 = high (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 1 μA D0 = D1 = high (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 0.5 2 μA Forward leakage current from IN1 (measured from OUT to GND) D0 = D1 = high (inactive), VI(IN1) = 5.5 V, IN2 open, VO(OUT) = 0 V (shorted), TJ = 25°C 0.1 5 μA Forward leakage current from IN2 (measured from OUT to GND) D0 = D1= high (inactive), VI(IN2) = 5.5 V, IN1 open, VO(OUT) = 0 V (shorted), TJ = 25°C 0.1 5 μA Reverse leakage current to INx (measured from INx to GND) D0 = D1 = high (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, TJ = 25°C 0.3 5 μA CURRENT LIMIT CIRCUIT Current limit accuracy, TPS2114A Current limit accuracy, TPS2115A td RILIM = 400 Ω 0.51 0.63 0.80 A RILIM = 700 Ω 0.30 0.36 0.50 A RILIM = 400 Ω 0.95 1.25 1.56 A RILIM = 700 Ω 0.47 0.71 0.99 A Current limit settling time Time for short-circuit output current to settle within 10% of its steady state value. Input current at ILIM VI(ILIM) = 0 V, IO(OUT) = 0 A –15 Falling edge 1.15 1 ms 0 μA UVLO IN1 and IN2 UVLO Rising edge IN1 and IN2 UVLO hysteresis Internal VDD UVLO (the higher of IN1 and IN2) Falling edge UVLO deglitch for IN1, IN2 4 1.35 30 57 65 2.4 2.53 30 Falling edge V 1.30 Rising edge Internal VDD UVLO hysteresis 1.25 V mV V 2.58 2.8 V 50 75 mV 110 μs Copyright © 2004–2012, Texas Instruments Incorporated TPS2114A TPS2115A www.ti.com SBVS044F – MARCH 2004 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS: GENERAL (continued) Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted. TPS2114A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 80 100 120 mV REVERSE CONDUCTION BLOCKING ΔVO(I_block) Minimum input-to-output voltage difference to block switching D0 = D1 = high, VI(INx) = 3.3 V Connect OUT to a 5-V supply through a series 1-kΩ resistor. Let D0 = low. Slowly decrease the supply voltage until OUT connects to IN1. THERMAL SHUTDOWN Thermal shutdown threshold TPS211xA is in current limit 135 Recovery from thermal shutdown TPS211xA is in current limit 125 °C °C Hysteresis 10 °C IN2−IN1 COMPARATORS Hysteresis of IN2−IN1 comparator 0.1 Deglitch of IN2−IN1 comparator (both ↑↓) 10 20 0.2 V 50 μs μA STAT OUTPUT Leakage current VO(STAT) = 5.5 V 0.01 1 Saturation voltage II(STAT) = 2 mA, IN1 switch is on 0.13 0.4 Deglitch time (falling edge only) V μs 150 SWITCHING CHARACTERISTICS Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted. TPS2114A PARAMETER TEST CONDITIONS TPS2115A MIN TYP MAX MIN TYP MAX UNIT POWER SWITCH tr Output rise time from an enable VI(IN1) = VI(IN2) = 5 V, TJ = 25°C, CL = 1 μF, IL = 500 mA (see Figure 1a) 0.5 1.0 1.5 1 1.8 3 ms tf Output fall time from a disable VI(IN1) = VI(IN2) = 5 V, TJ = 25°C, CL = 1 μF, IL = 500 mA (see Figure 1a) 0.35 0.5 0.7 0.5 1 2 ms IN1 to IN2 transition, VI(IN1) = 3.3 V, VI(IN2) = 5 V, TJ = 125°C, CL = 10 μF, IL = 500 mA Measure transition time as 10−90% rise time or from 3.4 V to 4.8 V on VO(OUT) (see Figure 1b). 40 60 40 60 μs IN2 to IN1 transition, VI(IN1) = 5 V, VI(IN2) = 3.3 V, TJ = 125°C, CL = 10 μF, IL = 500 mA Measure transition time as 10−90% rise time or from 3.4 V to 4.8 V on VO(OUT) (see Figure 1b). 40 60 40 60 μs tt Transition time tPLH1 Turn-on propagation delay from enable VI(IN1) = VI(IN2) = 5 V, measured from enable to 10% of VO(OUT), TJ = 25°C, CL = 10 μF, IL = 500 mA (see Figure 1a) 0.5 1 ms tPHL1 Turn-off propagation delay from a disable VI(IN1) = VI(IN2) = 5 V, measured from disable to 90% of VO(OUT), TJ = 25°C, CL = 10 μF, IL = 500 mA (see Figure 1a) 3 5 ms tPLH2 Switch-over rising propagation delay Logic 1 to Logic 0 transition on D1, VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(D0) = 0 V, measured from D1 to 10% of VO(OUT), TJ = 25°C, CL = 10 μF, IL = 500 mA (see Figure 1c) 40 100 tPHL2 Switch-over falling propagation delay Logic 0 to Logic 1 transition on D1, VI(IN1) = 1.5V, VI(IN2) = 5V, VI(D0) = 0 V, measured from D1 to 90% of VO(OUT), TJ = 25°C, CL = 10 μF, IL = 500 mA (see Figure 1c) 3 10 Copyright © 2004–2012, Texas Instruments Incorporated 2 2 40 100 μs 5 10 ms 5 TPS2114A TPS2115A SBVS044F – MARCH 2004 – REVISED MAY 2012 www.ti.com Table 1. Truth Table D1 (1) (2) D0 VI(IN2) > VI(IN1) X (2) STAT OUT (1) Hi-Z IN2 0 0 0 1 No 0 IN1 0 1 Yes Hi-Z IN2 1 0 X 0 IN1 1 1 X 0 Hi-Z The under-voltage lockout circuit causes the output OUT to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or if neither of the supplies exceeds the internal VDD UVLO. X = Don’t care. PIN CONFIGURATIONS PW PACKAGE TSSOP-8 (TOP VIEW) DRB PACKAGE 3mm × 3mm SON-8 (TOP VIEW) STAT 1 8 IN1 D0 2 7 OUT 3 D1 6 4 ILIM 5 STAT 1 D0 2 D1 3 ILIM 4 8 IN1 7 OUT 6 IN2 5 GND GND IN2 GND TERMINAL FUNCTIONS TERMINAL NAME NO. I/O D0 2 I TTL- and CMOS-compatible input pins. Each pin has a 1-μA pull-up. Table 1 illustrates the functionality of D0 and D1. D1 3 I TTL- and CMOS-compatible input pins. Each pin has a 1-μA pull-up. Table 1 illustrates the functionality of D0 and D1. GND 5 I Ground IN1 8 I Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. IN2 6 I Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. ILIM 4 I A resistor RILIM from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the TPS2114A and TPS2115A, respectively. OUT 7 O Power switch output STAT 1 O STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z (i.e., EN is equal to logic 0). PAD — I Tie to GND. Connect to internal planes for improved heatsinking with multiple vias. 6 DESCRIPTION Copyright © 2004–2012, Texas Instruments Incorporated TPS2114A TPS2115A www.ti.com SBVS044F – MARCH 2004 – REVISED MAY 2012 FUNCTIONAL BLOCK DIAGRAM 1 mA 1 mA IN1 IN2 Internal VDD Vf = 0 V Vf = 0 V IO(OUT) Q1 8 Q2 6 7 Charge Pump VDD ULVO IN2 ULVO IN1 ULVO Cross-Conduction Detector + _ 0.6 V + EN2 k* IO(OUT) _ TPS2114A: k = 0.2% TPS2115A: k = 0.1% + 0.5 V + _ VO(OUT) > VI(INx) UVLO (IN2) UVLO (IN1) D1 GND 3 + _ 100 mV + EN1 D0 D1 ILIM Q1 is ON UVLO (VDD) 2 4 EN1 Q2 is ON D0 OUT Control Logic Thermal Sense IN2 + _ 5 IN1 1 STAT Q2 is ON Copyright © 2004–2012, Texas Instruments Incorporated 7 TPS2114A TPS2115A SBVS044F – MARCH 2004 – REVISED MAY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION 90% 90% VO(OUT) 10% 10% 0V tr tf tPLH1 tPHL1 DO-D 1 Switch Off Switch Enabled Switch Off (a) 5V 4.8 V VO(OUT) 3.4 V 3.3 V tt DO-D 1 Switch #2 Enabled Switch #1 Enabled (b) 5V VO(OUT) 1.5 V 4.65 V 1.85 V tPLH2 tPHL2 DO-D 1 Switch #1 Enabled Switch #2 Enabled Switch #1 Enabled (c) Figure 1. Propagation Delays and Transition Timing Waveforms 8 Copyright © 2004–2012, Texas Instruments Incorporated TPS2114A TPS2115A www.ti.com SBVS044F – MARCH 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS space OUTPUT SWITCHOVER RESPONSE VI(DO) 2V/Div 5V TPS2115APW NC 2 f = 28 Hz 78% Duty Cycle VI(D1) 2V/Div 1 3 4 STAT IN1 7 D0 OUT D1 IN2 ILIM 0.1 mF 8 GND 6 5 50 W 1 mF 400 W 3.3 V VO(OUT) 0.1 mF 2V/Div Output Switchover Response Test Circuit t - Time - 1 ms/div Figure 2. OUTPUT TURN-ON RESPONSE VI(DO) 2V/Div 5V TPS2115APW f = 28 Hz 78% Duty Cycle VI(D1) 2V/Div NC 1 2 3 4 STAT IN1 7 D0 OUT D1 IN2 ILIM 0.1 mF 8 GND 6 5 1 mF 50 W 400 W 3.3 V VO(OUT) 2V/Div 0.1 mF Output Turn-On Response Test Circuit t - Time - 2 ms/div Figure 3. Copyright © 2004–2012, Texas Instruments Incorporated 9 TPS2114A TPS2115A SBVS044F – MARCH 2004 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) space OUTPUT SWITCHOVER VOLTAGE DROOP VI(DO) 2V/Div 5V TPS2115APW NC VI(D1) 2V/Div CL = 1 mF f = 580 Hz 90% Duty Cycle 1 2 3 4 STAT IN1 7 D0 OUT D1 IN2 ILIM 0.1 mF 8 GND 6 5 CL 50 W 400 W VO(OUT) 2V/Div 0.1 mF CL = 0 mF Output Switchover Voltage Droop Test Circuit t - Time - 40 ms/div Figure 4. 10 Copyright © 2004–2012, Texas Instruments Incorporated TPS2114A TPS2115A www.ti.com SBVS044F – MARCH 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) space OUTPUT SWITCHOVER VOLTAGE DROOP vs LOAD CAPACITANCE 5 VI = 5 V VO(OUT) - Output Voltage Droop - V 4.5 4 3.5 RL = 10 W 3 2.5 2 1.5 1 RL = 50 W 0.5 0 0.1 VI 1 10 CL - Load Capacitance -mF 100 TPS2115APW NC 1 2 f = 28 Hz 50% Duty Cycle 3 4 400 W IN1 STAT D0 OUT D1 IN2 ILIM GND 8 0.1 mF 7 6 5 50 W 0.1 mF 0.1 mF 1 mF 10 mF 47 mF 10 W 100 mF Output Switchover Voltage Droop Test Circuit Figure 5. Copyright © 2004–2012, Texas Instruments Incorporated 11 TPS2114A TPS2115A SBVS044F – MARCH 2004 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) space AUTO SWITCHOVER VOLTAGE DROOP VI(IN1) 2V/Div 5V TPS2115A 1kW 1 2 f = 220 Hz 20% Duty Cycle 3 4 400W VO(OUT) 2V/Div STAT D0 D1 ILIM IN1 0.1 mF 8 7 OUT IN2 GND 6 5 VOUT 3.3V 10 mF 50 W 0.1mF 75% less output voltage droop compared to TPS2115 Auto Switchover Voltage Droop Test Circuit t - Time - 250 ms/div Figure 6. 12 Copyright © 2004–2012, Texas Instruments Incorporated TPS2114A TPS2115A www.ti.com SBVS044F – MARCH 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) space INRUSH CURRENT vs LOAD CAPACITANCE 300 200 VI = 5 V 150 VI = 3.3 V 100 I I - Inrush Current - mA 250 50 0 0 VI f = 28 Hz 90% Duty Cycle 20 40 60 80 CL - Load Capacitance -µF 100 TPS2115APW NC 1 2 NC 3 4 400 W STAT IN1 D0 OUT D1 IN2 ILIM GND 8 0.1 mF To Oscilloscope 7 6 5 50 W 0.1 mF 0.1 mF 1 mF 10 mF 47 mF 100 mF Output Capacitor Inrush Current Test Circuit Figure 7. Copyright © 2004–2012, Texas Instruments Incorporated 13 TPS2114A TPS2115A SBVS044F – MARCH 2004 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) space SWITCH ON-RESISTANCE vs JUNCTION TEMPERATURE SWITCH ON-RESISTANCE vs SUPPLY VOLTAGE 120 rDS(on) - Switch On-Resistance - m W rDS(on) - Switch On-Resistance - m W 180 160 TPS2114A 140 120 TPS2115A 100 80 60 -50 150 105 100 95 90 TPS2115A 85 2 3 4 5 VI(INx) - Supply Voltage - V Figure 8. Figure 9. IN1 SUPPLY CURRENT vs SUPPLY VOLTAGE IN1 SUPPLY CURRENT vs SUPPLY VOLTAGE 6 60 Device Disabled VI(IN2) = 0 V IO(OUT) = 0 A IN1 Switch is ON VI(IN2) = 0 V IO(OUT) = 0 A 58 I(IN1) - IN1 Supply Current - mA 0.94 0.92 0.90 0.88 0.86 I IN1 Supply Current- m A 110 80 0 50 100 TJ - Junction Temperature - °C 0.96 I-I(IN1) TPS2114A 115 56 54 52 50 48 46 44 0.84 42 40 0.82 2 3 4 5 VI(IN1) - IN1 Supply Voltage - V Figure 10. 14 6 2 3 4 5 VI(IN1) - Supply Voltage - V 6 Figure 11. Copyright © 2004–2012, Texas Instruments Incorporated TPS2114A TPS2115A www.ti.com SBVS044F – MARCH 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) space SUPPLY CURRENT vs JUNCTION TEMPERATURE SUPPLY CURRENT vs JUNCTION TEMPERATURE 1.2 Device Disabled VI(IN1) = 5.5 V VI(IN2) = 3.3 V IO(OUT) = 0 A I I(INx) - Supply Current - mA 70 II(IN1) = 5.5 V 0.8 0.6 0.4 I I(INx) - Supply Current - mA 1 80 0.2 0 50 100 TJ - Junction Temperature - °C Figure 12. Copyright © 2004–2012, Texas Instruments Incorporated 150 II(IN1) 50 40 30 20 10 II(IN2) = 3.3 V 0 -50 60 IN1 Switch is ON VI(IN1) = 5.5 V VI(IN2) = 3.3 V IO(OUT) = 0 A 0 -50 II(IN2) 0 50 100 TJ - Junction Temperature - °C 150 Figure 13. 15 TPS2114A TPS2115A SBVS044F – MARCH 2004 – REVISED MAY 2012 www.ti.com APPLICATION INFORMATION Some applications have two energy sources, one of which should be used in preference to another. Figure 14 shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once the voltage on IN1 falls below this value, the TPS2114A/5A will select the higher of the two supplies. This usually means that the TPS2114A/5A will swap to IN2. Switch Status IN1: 2.8 - 5.5 V TPS2115APW 1 NC 2 3 4 STAT IN1 D0 OUT D1 IN2 ILIM GND R1 0.1 mF 8 7 6 RL CL 5 RILIM IN2: 2.8 - 5.5 V C2 0.1 mF Figure 14. Auto-Selecting for a Dual Power Supply Application In Figure 15, the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects to IN1 if D1 is logic 1; otherwise, OUT connects to IN2. The logic thresholds for the D1 terminal are compatible with both TTL and CMOS logic. Switch Status IN1: 2.8 - 5.5 V TPS2115APW 1 2 3 4 STAT IN1 D0 OUT D1 IN2 ILIM GND R1 0.1 mF 8 7 6 CL 5 RL RILIM IN2: 2.8 - 5.5 V 0.1 mF Figure 15. Manually Switching Power Sources 16 Copyright © 2004–2012, Texas Instruments Incorporated TPS2114A TPS2115A www.ti.com SBVS044F – MARCH 2004 – REVISED MAY 2012 DETAILED DESCRIPTION AUTO-SWITCHING MODE D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the higher of IN1 and IN2. MANUAL SWITCHING MODE D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic 1, otherwise OUT connects to IN2. N-CHANNEL MOSFETs Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so output-toinput current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET switch if the output voltage is greater than the input voltage. CROSS-CONDUCTION BLOCKING The switching circuitry ensures that both power switches will never conduct at the same time. A comparator monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source voltage of the other FET is below the turn-on threshold voltage. REVERSE-CONDUCTION BLOCKING When the TPS211xA switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS211xA will not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output voltage. CHARGE PUMP The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages. A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET. CURRENT LIMITING A resistor RILIM from ILIM to GND sets the current limit to 250/RILIM and 500/RILIM for the TPS2114A and TPS2115A, respectively. Setting resistor RILIM equal to zero is not recommended as that disables current limiting. OUTPUT VOLTAGE SLEW-RATE CONTROL The TPS2114A/5A slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state (see Table 1). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the connector power contacts, when hot-plugging a load such as a PCI card. The TPS2114A/5A slews the output voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output voltage droop and reduces the output voltage hold-up capacitance requirement. Copyright © 2004–2012, Texas Instruments Incorporated 17 PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2114APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TPS2115ADRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS2115ADRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS2115APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2114APWR TPS2115ADRBR TSSOP PW 8 2000 367.0 367.0 35.0 SON DRB 8 3000 367.0 367.0 35.0 TPS2115ADRBT SON DRB 8 250 210.0 185.0 35.0 TPS2115APWR TSSOP PW 8 2000 367.0 367.0 35.0 Pack Materials-Page 2 TPS2114A TPS2115A SBVS044F – MARCH 2004 – REVISED MAY 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2011) to Revision F Page • Changed description of power supplies in Description section ............................................................................................ 1 • Added IOUT column to Device Information table .................................................................................................................... 2 • Changed conditions of Absolute Maximum Ratings table .................................................................................................... 2 • Added PW to end of device name in first two continuous output rows in Current parameter of Absolute Maximum Ratings table ......................................................................................................................................................................... 2 • Added last continuous output row to Current parameter in Absolute Maximum Ratings table ............................................ 2 • Deleted storage temperature row from Absolute Maximum Ratings table ........................................................................... 2 • Changed Current limit adjustment range parameter, TPS2115A specification in Available Options table .......................... 2 • Changed Nominal current limit adjustment range parameter in Recommended Operating Conditions table ...................... 3 • Added footnote 1 to Recommended Operating Conditions table ......................................................................................... 3 Changes from Revision D (July 2006) to Revision E Page • Updated document to current format .................................................................................................................................... 1 • Changed title, footnote, and CGF marking in Device Information table ............................................................................... 2 • Deleted footnote 1 (not tested in production) from Electrical Characteristics: General table ............................................... 4 • Deleted footnote 1 (not tested in production) from Switching Characteristics table ............................................................. 5 • Added PAD row to Terminal Functions table ........................................................................................................................ 6 18 Copyright © 2004–2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS2114APW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2114A TPS2114APWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2114A TPS2115ADRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CGF TPS2115ADRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CGF TPS2115ADRBTG4 ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CGF TPS2115APW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2115A TPS2115APWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2115A TPS2115APWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2115A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of