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TPS2115A-Q1
SBVS124A – NOVEMBER 2008 – REVISED MAY 2016
TPS2115A-Q1 Auto-Switching Power Multiplexer
1 Features
2 Applications
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 3: –40°C to 85°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4A
Two-Input One-Output Power Multiplexer With
Low rDS(on) Switch...84 mΩ (Typical)
Reverse and Cross-Conduction Blocking
Wide Operating Voltage Range...2.8 V to 5.5 V
Low Standby Current...0.5 μA (Typical)
Low Operating Current...55 μA (Typical)
Adjustable Current Limit
Controlled Output-Voltage Transition Times Limit
Inrush Current and Minimize Output Voltage HoldUp Capacitance
CMOS- and TTL-Compatible Control Inputs
Manual and Auto-Switching Operating Modes
Thermal Shutdown
Available in TSSOP-8 (PW) Package
•
Automotive Power Multiplexing Applications
Infotainment
Navigation
Multimedia Functions: Digital Radios, MP3
Players, Phone Chargers
Camera Applications
3 Description
The TPS2115A-Q1 power multiplexer enables
seamless transition between two power supplies,
such as a two supply rails or a battery and AC to DC
wall adapter. Each supply operates at 2.8 V to 5.5 V
and the output can deliver up to 1 A. The TPS2115AQ1 device includes extensive protection circuitry
including user-programmable current limiting, thermal
protection, inrush current control, seamless supply
transition, cross-conduction blocking, and reverseconduction blocking. These features greatly simplify
designing power multiplexer applications.
Device Information(1)
PART NUMBER
TPS2115A-Q1
PACKAGE
TSSOP (8)
BODY SIZE (NOM)
4.40 mm × 3.0 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
Switch Status
IN1
2.8 V to 5.5 V
TPS2115A-Q1
1
NC
2
3
4
STAT
IN1
D0
OUT
D1
IN2
ILIM
R1
0.1 µF
GND
8
7
6
CL
5
RL
R ILIM
IN2
2.8 V to 5.5 V
0.1 µF
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2115A-Q1
SBVS124A – NOVEMBER 2008 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
4
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7
Parameter Measurement Information .................. 9
8
Detailed Description ............................................ 11
7.1 Test Circuits .............................................................. 9
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 12
9
Application and Information ............................... 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2008) to Revision A
Page
•
Changed Applications list ...................................................................................................................................................... 1
•
Changed TPS2115A to TPS2155A-Q1 throughout document .............................................................................................. 1
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
•
Changed Continuous output current from 1.5mA to 1.5A in Absolute Maximum Ratings table............................................. 3
•
Moved Figure 1 to Switching Characteristics section............................................................................................................. 6
•
Moved test circuits from Typical Characteristics to Parameter Measurement Information section........................................ 7
•
Changed info in D0 column with info from D1 column and moved table to Device Functional Modes section ................... 12
2
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SBVS124A – NOVEMBER 2008 – REVISED MAY 2016
5 Pin Configuration and Functions
PW Package
8-Pin TSSOP
Top View
STAT
1
8
IN1
D0
2
7
OUT
D1
3
6
IN2
ILIM
4
5
GND
Pin Functions
PIN
NAME
NO.
Type
DESCRIPTION
D0
2
I
D1
3
I
GND
5
GND
Ground
IN1
8
PWR
Primary supply power-switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO
threshold and at least one supply exceeds the internal VDD UVLO.
IN2
6
PWR
Secondary supply power-switch input. The IN2 switch can be enabled only if the IN2 supply is above the
UVLO threshold and at least one supply exceeds the internal VDD UVLO.
ILIM
4
I
A resistor RILIM from ILIM to GND sets the current limit IL to 500/RILIM.
OUT
7
O
Power switch output
STAT
1
O
Open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z
(that is EN is equal to logic 0).
TTL- and CMOS-compatible input pins. Each pin has a 1-μA pullup. The Truth Table shows the functionality
of D0 and D1.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VI
Input voltage range
IN1, IN2, D0, D1, ILIM
–0.3
6
V
VO
Output voltage range
OUT, STAT
–0.3
6
V
IO(sink)
Output sink current
STAT
5
mA
IO
Continuous output current
OUT
1.5
A
See
Thermal
Information
PD
Continuous total-power dissipation
TA
Operating free-air temperature range
–40
85
°C
TJ
Operating virtual-junction temperature range
–40
125
°C
1,6 mm
(1/16 inch)
from case
for 10
seconds
260
°C
–65
150°
°C
Tlead
Lead temperature soldering
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
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SBVS124A – NOVEMBER 2008 – REVISED MAY 2016
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6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM)
±2000
Charged-device model (CDM)
±500
UNIT
V
6.3 Recommended Operating Conditions
MIN
IN1
VI
Input voltage
IN2
NOM
MAX
VI(IN2) ≥ 2.8 V
1.5
5.5
VI(IN2) < 2.8 V
2.8
5.5
VI(IN1) ≥ 2.8 V
1.5
5.5
VI(IN1) < 2.8 V
2.8
5.5
5.5
D0, D1
0
VIH
High-level input voltage
D0, D1
2
VIL
Low-level input voltage
D0, D1
IO
Current limit adjustment range
OUT
TA
Operating free-air temperature
TJ
Operating virtual-junction temperature range
UNIT
V
V
0.7
V
1.25
A
–40
85
°C
–40
125
°C
0.63
6.4 Thermal Information
TPS2115A-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
159.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40.7
°C/W
RθJB
Junction-to-board thermal resistance
90.1
°C/W
ψJT
Junction-to-top characterization parameter
2.1
°C/W
ψJB
Junction-to-board characterization parameter
87.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
POWER SWITCH
TEST CONDITIONS
TA = 25°C, IL = 500 mA
rDS(on)
MIN
TYP
MAX
VI(IN1) = VI(IN2) = 5.0 V
84
110
VI(IN1) = VI(IN2) = 3.3 V
84
110
VI(IN1) = VI(IN2) = 2.8 V
84
110
UNIT
(1)
Drain-source on-state
resistance (INx to OUT)
TA = 85°C, IL = 500 mA
VI(IN1) = VI(IN2) = 5.0 V
150
VI(IN1) = VI(IN2) = 3.3 V
150
VI(IN1) = VI(IN2) = 2.8 V
150
mΩ
LOGIC INPUTS (D0 AND D1)
II
Input current at D0 or D1
D0 or D1 = high, sink current
1
D0 or D1 = low, source current
0.5
1.4
5
D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A
55
90
D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A
1
12
μA
SUPPLY AND LEAKAGE CURRENTS
Supply current from IN1 (operating)
(1)
4
D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A
75
D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A
1
μA
The TPS2115A-Q1 device can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In
this case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
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Electrical Characteristics (continued)
over operating free-air temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A
Supply current from IN2 (operating)
75
D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A
D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A
D0 = D1 = high (inactive), IO(OUT) = 0 A
Quiescent current from IN2 (standby)
D0 = D1 = high (inactive), IO(OUT) = 0 A
Forward leakage current from IN1
(measured from OUT to GND)
UNIT
1
D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A
Quiescent current from IN1 (standby)
MAX
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V
1
12
55
90
0.5
2
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V
1
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V
1
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V
μA
μA
μA
0.5
2
D0 = D1 = high (inactive), VI(IN1) = 5.5 V, IN2 open, VO(OUT) = 0 V (shorted),
TA = 25°C
0.1
5
μA
Forward leakage current from IN2
(measured from OUT to GND)
D0 = D1= high (inactive), VI(IN2) = 5.5 V, IN1 open, VO(OUT) = 0 V (shorted),
TA = 25°C
0.1
5
μA
Reverse leakage current to INx
(measured from INx to GND)
D0 = D1 = high (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, TA = 25°C
0.3
5
μA
CURRENT LIMIT CIRCUIT
Current limit accuracy
RILIM = 400 Ω
0.95
1.25
1.56
RILIM = 700 Ω
0.47
0.71
0.99
td
Current limit settling time
Time for short-circuit output current to settle within 10% of its steady state value
II
Input current at ILIM
VI(ILIM) = 0 V, IO(OUT) = 0 A
–15
1
Falling edge
1.15
A
ms
0
μA
UVLO
IN1 and IN2 UVLO
Rising edge
IN1 and IN2 UVLO hysteresis
Internal VDD UVLO (the higher of IN1
and IN2)
Falling edge
UVLO deglitch for IN1, IN2
1.30
1.35
30
57
65
2.4
2.53
Rising edge
Internal VDD UVLO hysteresis
1.25
30
Falling edge
2.58
2.8
50
75
V
mV
V
mV
μs
110
REVERSE CONDUCTION BLOCKING
Minimum input-to-output
ΔVIO(blk) voltage difference to block
switching
D0 = D1 = high, VI(INx) = 3.3 V. Connect OUT to a 5-V supply through a series
1-kΩ resistor. Set D0 = low. Slowly decrease the supply voltage until OUT
connects to IN1.
80
100
120
mV
THERMAL SHUTDOWN
Thermal shutdown threshold
TPS2115A-Q1 device is in current limit.
135
Recovery from thermal shutdown
TPS2115A-Q1 device is in current limit.
125
Hysteresis
°C
°C
10
°C
IN2-IN1 COMPARATORS
Hysteresis of IN2-IN1 comparator
0.1
Deglitch of IN2-IN1 comparator
(both ↑↓)
10
20
0.2
V
50
μs
STAT OUTPUT
Ileak
Leakage current
VO(STAT) = 5.5 V
0.01
1
μA
Vsat
Saturation voltage
II(STAT) = 2 mA, IN1 switch is on
0.13
0.4
V
td
Deglitch time
(falling edge only)
150
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6.6 Switching Characteristics
over operating free-air temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Switch
tr
Output rise time from an
enable
VI(IN1) = VI(IN2) = 5 V
TA = 25°C, CL = 1 μF, IL = 500 mA,
See Figure 1(a)
1
1.8
3
ms
tf
Output fall time from a
disable
VI(IN1) = VI(IN2) = 5 V
TA = 25°C, CL = 1 μF, IL = 500 mA,
See Figure 1(a)
0.5
1
2
ms
40
60
40
60
tt
IN1 to IN2 transition, VI(IN1) = 3.3 V,
VI(IN2) = 5 V
Transition time
IN2 to IN1 transition, VI(IN1) = 5 V,
VI(IN2) = 3.3 V
TA = 85°C, CL = 10 μF, IL = 500 mA
[Measure transition time as 10%90% rise time or from 3.4 V to 4.8 V
on VO(OUT)], See Figure 1(b)
μs
tPLH1
Turn-on propagation delay
from enable
VI(IN1) = VI(IN2) = 5 V, Measured from
enable to 10% of VO(OUT)
TA = 25°C, CL = 10 μF, IL = 500 mA,
See Figure 1(a)
1
ms
tPHL1
Turn-off propagation delay
from a disable
VI(IN1) = VI(IN2) = 5 V, Measured from
disable to 90% of VO(OUT)
TA = 25°C, CL = 10 μF, IL = 500 mA,
See Figure 1(a)
5
ms
tPLH2
Switch-over rising
propagation delay
Logic 1 to Logic 0 transition on D1,
VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(D0) = 0 V,
Measured from D1 to 10% of VO(OUT)
TA = 25°C, CL = 10 μF, IL = 500 mA,
See Figure 1(c)
40
100
μs
tPHL2
Switch-over falling
propagation delay
Logic 0 to Logic 1 transition on D1,
VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(D0) = 0 V,
Measured from D1 to 90% of VO(OUT)
TA = 25°C, CL = 10 μF, IL = 500 mA,
See Figure 1(c)
5
10
ms
90%
90%
VO(OUT)
10%
10%
0V
2
tr
tf
tPLH1
tPHL1
DO-D1
Switch Off
Switch Enabled
Switch Off
(a)
5V
4.8 V
VO(OUT)
3.4 V
3.3 V
tt
DO-D1
Switch #2 Enabled
Switch #1 Enabled
(b)
5V
VO(OUT)
4.65 V
1.85 V
1.5 V
tPLH2
tPHL2
DO-D1
Switch #1 Enabled
Switch #2 Enabled
Switch #1 Enabled
(c)
Figure 1. Propagation Delays and Transition Timing Waveforms
6
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6.7 Typical Characteristics
VI(D0)
2 V/div
VI(D1)
2 V/div
VI(D0)
2 V/div
VI(D1)
2 V/div
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − T ime − 1 ms/div
Input to D1: f=28 Hz, 78% Duty Cycle
t − Time − 2 ms/div
See Figure 14 for test
circuit
Input to D0: f=28 Hz, 78% Duty Cycle
Figure 2. Output Switchover Response
See Figure 15 for test
circuit
Figure 3. Output Turn-On Response
5
VI = 5 V
4.5
V I(DO)
V I (D1 )
− Output V oltage Droop − V
2 V/div
DV O(OUT)
C L = 1 µF
2 V/div
V O(OUT)
2 V/div
C L = 0 µF
3
R L = 10 W
2.5
2
1.5
1
R L = 50 W
0.5
0
0.1
t − T ime − 40 µs/div
Input to D1: f = 580 Hz, 90% duty
cycle
4
3.5
See Figure 16 for test
circuit
Figure 4. Output Switchover Voltage Droop
1
10
100
C L − Load Capacitance − µF
Input to D1: f = 28 Hz, 50% duty cycle
See Figure 17 for test
circuit
Figure 5. Output Switchover Voltage Droop vs Load
Capacitance
300
V I(IN1)
250
2V/Div
− Inrush Current − mA
200
VI = 5 V
150
V I = 3.3 V
I
I
100
V O(OUT)
2V/Div
75% less output voltage
droop compared to TPS2115
50
0
0
t − T ime − 250 µs/div
Input to IN1 through switch: f = 220
Hz, 20% duty cycle
See Figure 18 for test
circuit
Figure 6. Auto Switchover Voltage Droop
20
40
60
80
100
C L − Load Capacitance − µF
Input to D0: f=28 Hz 90% duty cycle
See Figure 19 for test
circuit
Figure 7. Inrush Current vs Load Capacitance
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Typical Characteristics (continued)
120
180
115
− Switch On-Resistance − mW
140
120
DS(on)
100
r
80
r
DS(on)
− Switch On-Resistance − mW
160
60
110
105
100
95
90
85
80
−50
0
50
100
2
150
3
T J − Junction Temperature − °C
4
5
6
V I(INx) − Supply Voltage − V
Figure 8. Switch On-Resistance vs Junction Temperature
Figure 9. Switch On-Resistance vs Supply Voltage
60
0.96
58
0.94
I(IN1) − IN1 Supply Current − µA
− IN1 Supply Current − µA
56
0.92
0.90
0.88
I
I I(IN1)
0.86
54
52
50
48
46
44
0.84
42
40
0.82
2
3
4
5
6
2
3
4
5
V I(IN1) − Supply Voltage − V
V I(IN1) − IN1 Supply Voltage − V
VI(IN2) = 0 V
VI(IN2) = 0 V
IO(OUT) = 0 A
Figure 10. IN1 Supply Current vs Supply Voltage (Device
Disabled)
IO(OUT) = 0 A
Figure 11. IN1 Supply Current vs Supply Voltage (IN1 Switch
ON)
1.2
80
70
− Supply Current − µA
1
I I(IN1) = 5.5 V
0.8
0.6
I(INx)
0.4
60
I I(IN1)
50
40
30
20
I
I
I(INx)
− Supply Current − µA
6
0.2
10
I I(IN2)
I I(IN2) = 3.3 V
0
−50
0
50
100
150
0
−50
0
VI(IN1) = 5.5 V
VI(IN2) = 3.3 V
IO(OUT) = 0 A
Figure 12. Supply Current vs Junction Temperature (Device
Disabled)
8
50
100
150
T J − Junction Temperature − °C
T J − Junction Temperature − °C
VI(IN1) = 5.5 V
VI(IN2) = 3.3 V
IO(OUT) = 0 A
Figure 13. Supply Current vs Junction Temperature (IN1
Switch ON)
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7 Parameter Measurement Information
7.1 Test Circuits
The following figures are the test circuits for the graphs in the Typical Characteristics section.
5V
TPS2115A-Q1
1
NC
STAT
IN1
2
f = 28 Hz
78% Duty Cycle
0.1 µF
8
7
D0
OUT
D1
IN2
ILIM
GND
3
4
6
50 W
1 µF
5
400 W
3.3 V
0.1 µF
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Figure 14. Output Switchover Response Test Circuit
5V
TPS2115A-Q1
f = 28 Hz
78% Duty Cycle
1
NC
STAT
IN1
2
7
D0
OUT
D1
IN2
3
4
0.1 µF
8
ILIM
6
GND
5
50 W
1 µF
400 W
3.3 V
0.1 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Output Turn-On Response Test Circuit
5V
TPS2115A-Q1
NC
1
STAT
IN1
2
f = 580 Hz
90% Duty Cycle
7
D0
OUT
D1
IN2
ILIM
GND
3
4
0.1 µF
8
6
5
CL
50 W
400 W
0.1 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 16. Output Switchover Voltage Droop Test Circuit
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Test Circuits (continued)
VI
TPS2115A-Q1
1
NC
2
f = 28 Hz
50% Duty Cycle
3
4
400 W
IN1
STAT
D0
OUT
D1
IN2
GND
ILIM
0.1 µF
8
7
6
5
50 W
0.1 µF
0.1 µF
1 µF
10 µF
47 µF
10 W
100 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Output Switchover Voltage Droop vs Load Capacitance Test Circuit
5V
TPS2115A-Q1
1 kW
1
IN 1
ST AT
2
7
D0
f = 220 Hz
20% Duty Cycle
0.1 µF
8
3
6
D1
4
IL IM
VOUT
OUT
IN 2
GND
3.3 V
10 µF
5
50 W
0.1 µF
400 W
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Auto Switchover Voltage Drop Test Circuit
VI
f = 28 Hz
90% Duty Cycle
TPS2115A-Q1
NC
1
2
NC
3
4
400 W
STAT
IN1
D0
OUT
D1
IN2
ILIM
GND
8
0.1 µF
To Oscilloscope
7
6
5
50 W
0.1 µF
0.1 µF
1 µF
10 µF
47 µF
100 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Output Capacitance Inrush Current vs Load Capacitance Test Circuit
10
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8 Detailed Description
8.1 Overview
The TPS2115A-Q1 power multiplexer enables seamless transition between two power supplies, such as a two
supply rails or a battery and AC-to-DC wall adapter. Each supply operates at 2.8 V to 5.5 V and the output can
deliver up to 1 A. The TPS2115A-Q1 device includes extensive protection circuitry including user-programmable
current limiting, thermal protection, inrush current control, seamless supply transition, cross-conduction blocking,
and reverse-conduction blocking. These features greatly simplify designing power multiplexer applications.
8.2 Functional Block Diagram
Internal VDD
1 µA
1 µA
Vf = 0 V
IN1
IN2
Vf = 0 V
IO(OUT)
Q1
8
Q2
6
7
Charge
Pump
OUT
k* IO(OUT)
k = 0.1%
VDD
ULVO
4
_
+
IN2
ILIM
0.5 V
ULVO
IN1
ULVO
Cross-Conduction
Detector
+
_
0.6 V
+
EN2
+
_
EN1
Q1 is ON
Q2 is ON
UVLO (VDD)
VO(OUT) > V I(INx)
UVLO (IN2)
UVLO (IN1)
D0
D1
GND
2
3
EN1
D0
D1
+
_
100 mV
+
Control
Logic
Thermal
Sense
IN2
+
_
5
IN1
1
STAT
Q2 is ON
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 N-Channel MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so output-toinput current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET switch if the
output voltage is greater than the input voltage.
8.3.2 Cross-Conduction Blocking
The switching circuitry ensures that both power switches never conducts at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
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Feature Description (continued)
8.3.3 Reverse-Conduction Blocking
When the TPS2115A-Q1 device switches from a higher-voltage supply to a lower-voltage supply, current can
potentially flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction,
the TPS2115A-Q1 device does not connect a supply to the output until the output voltage has fallen to within 100
mV of the supply voltage. Once a supply has been connected to the output, the supply remains connected
regardless of output voltage.
8.3.4 Charge Pump
The higher voltage of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power
to the current-limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply
voltages. A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
8.3.5 Current Limiting
A resistor RILIM from ILIM to GND sets the current limit to ( ( 500 Ω ) / RILIM ) A. It is recommended to keep the
current limit set to 1.25 A or lower (RILIM ≥ 400 Ω). Setting resistor RILIM equal to zero is not recommended as
that disables current limiting.
8.3.6 Output Voltage Slew-Rate Control
The TPS2115A-Q1 device slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the HiZ state (see Table 1). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can
glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues such as pitting
the connector power contacts when hot-plugging a load such as a PCI card. The TPS2115A-Q1 device slews the
output voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the
output voltage droop and reduces the output voltage hold-up capacitance requirement.
8.4 Device Functional Modes
Table 1 is the Truth Table for the TPS2115A-Q1 power multiplexer.
Table 1. Truth Table
(1)
(2)
D1
D0
0
0
0
1
0
1
1
0
1
1
STAT
OUT (2)
Hi-Z
IN2
No
0
IN1
Yes
Hi-Z
IN2
X
0
IN1
X
0
Hi-Z
VI(IN2) > VI(IN1)
X
(1)
X = don’t care
The undervoltage lockout circuit causes the output OUT to go Hi-Z if
the selected power supply does not exceed the IN1 or IN2 UVLO, or
if neither of the supplies exceeds the internal VDD UVLO.
8.4.1 Auto-Switching Mode
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the
higher of IN1 and IN2.
8.4.2 Manual Switching Mode
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to
logic 1, otherwise OUT connects to IN2.
12
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9 Application and Information
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Some applications have two energy sources, one of which should be used in preference to another. The
TPS2115A-Q1 allows either manual or automatic selection of the input supply depending on the device
configuration and use in the specific application.
Figure 20 shows a circuit that connects IN1 to OUT until IN1 falls below a user-specified value. Once the voltage
on IN1 falls below this value, the TPS2115A-Q1 device selects the higher of the two supplies. This usually
means the TPS2115A-Q1 device swaps to the IN2 supply.
Switch Status
IN1
2.8 V to 5.5 V
TPS2115A-Q1
1
NC
2
3
4
STAT
IN1
D0
OUT
D1
IN2
ILIM
R1
0.1 µF
GND
8
7
6
CL
5
RL
R ILIM
IN2
2.8 V to 5.5 V
0.1 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Auto-Selecting for a Dual Power Supply Application
In Figure 21, the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects
to IN1 if D1 is logic 1; otherwise, OUT connects to IN2. The logic thresholds for the D1 terminal are compatible
with both TTL and CMOS logic.
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Application Information (continued)
Switch Status
IN1
2.8 V to 5.5 V
TPS2115A-Q1
1
2
3
4
IN1
STAT
D0
OUT
D1
IN2
ILIM
R1
0.1 µF
GND
8
7
6
RL
CL
5
R ILIM
IN2
2.8 V to 5.5 V
0.1 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Manually Switching Power Sources
9.2 Typical Application
Figure 22 shows a circuit that connects IN1 to OUT until the voltage at IN1 falls below the voltage at IN2. Once
the voltage on IN1 falls below the voltage on IN2, the TPS2115A-Q1 device selects IN2 since it is the higher of
the two supplies.
Switch Status
5V
TPS2115A-Q1
1
NC
2
3
4
STAT
IN1
D0
OUT
D1
IN2
ILIM
GND
R1 = 10 k
0.1 µF
8
7
6
CL = 1 µF
RL = 50
5
RILIM = 700
3.3 V
0.1 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Auto-Selecting for a Dual Power Supply Application with 5 V for Normal Operation and 3.3 V
Low Power Mode
9.2.1 Design Requirements
The application has two supply rails, the main supply is for normal operation with higher system current, bias
current, and operation at 5 V. In this system, the second supply is needed for lower voltage, 3.3 V, with lower
bias current during low-power mode. In addition, when the system enters low power mode, the other loads on the
main supply need to be off. A power multiplexer is needed to connect the load automatically to the second supply
when the system enters low-power mode keeping the load powered in low-power mode with minimal bias
current. The load is equivalent to 50 Ω and the current limit should be set no higher than 1 A.
14
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The following steps are the detailed design procedure.
1. Connect the main power supply, 5 V, to IN1.
2. Connect the second 3.3-V supply to IN2 for the low-power mode.
3. Place local bypass capacitors of 0.1 μA on IN1 and IN2 to GND to minimize ripple during transition between
the power supply inputs.
4. Leave D0 floating (unconnected). The internal pullup current source to Internal VDD puts a logic high on the
D0 pin.
5. Connect D1 to GND, logic low. The logic combination on D0 and D1 puts the device into Auto-Switching
Mode.
6. The application load, RL, is 50 Ω as given in the design requirements. Use a bulk capacitance, CL, of 1 μF to
buffer the output voltage from dropping on OUT during the transition between IN1 and IN2.
During normal operation of the system, the main power supply connected to IN1 is on and supplies 5 V. The
voltage on IN1 is higher than IN2, so the path automatically selects IN1 to OUT and the device supplies the load,
RL (50 Ω), from IN1.
For low-power mode, the system turns off the main supply. The device automatically switches to the path of IN2
to OUT and the device supplies the load, RL (50 Ω), from IN2 as soon as the voltage on IN1 is lower than the
voltage on IN2.
To return to normal operation, the system turns on the main supply and when the voltage on IN1 is higher than
the voltage on IN2, the path automatically selects IN1 to OUT and the device supplies the load, RL (50 Ω), from
IN1.
1. To set the current limit below 1 A, use an RILIM of 700 Ω according to Equation 1.
(1)
2. Using the current limit accuracy in the electrical characteristics section, using RILIM of 700 Ω has a maximum
current limit of 0.99 A, which is below the design requirement of 1 A.
Connect a pullup resistor, R1, of 10 kΩ, to the host processor to monitor which input supply is selected.
9.2.3 Application Curve
VI(D0)
2 V/div
VI(D1)
2 V/div
VO(OUT)
2 V/div
t − T ime − 1 ms/div
Figure 23. Output Switchover Response
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10 Power Supply Recommendations
Use well-regulated supplies on IN1 and IN2 that have sufficient capacitance for the application load transients.
As close as possible to the device, use a 0.1-μF ceramic bypass capacitor between IN1 and GND for the first
power supply input and a 0.1-μF ceramic bypass capacitor between IN2 and GND for the second power supply
input. The recommendation is to place a high-value capacitor between OUT and GND when the output load is
heavy. This precaution reduces power-supply transients that may cause ringing on the input or voltage drops
during load transients or supply input transitions. Additionally, bypassing the output with a 0.01-μF to 0.1-μF
ceramic capacitor may reduce high-frequency emissions.
11 Layout
11.1 Layout Guidelines
•
•
•
•
For the first supply input (IN1), place the 0.1-μF bypass capacitor between the IN1 and GND as close as
possible ensuring a low-impedance trace.
For the second supply input (IN2), place the 0.1-μF bypass capacitor between the IN2 and GND as close as
possible ensuring a low-impedance trace.
Place a high-value capacitor and a 0.1-μF bypass capacitor between OUT and GND. The recommendation is
to use the high-value capacitor when expecting large-load transients on the output. This trace should be lowimpedance to the load.
Place the resistor used to set the current limit between ILIM and GND. Make sure the traces routing the RILIM
resistor to the device are as short as possible to reduce parasitic effects on the current limit accuracy.
11.2 Layout Example
STAT
IN1
DO
OUT
D1
IN2
ILIM
GND
Via to Ground Plane
Ground Plane (Layer 2)
Figure 24. TPS2115A-Q1 Layout Example
16
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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17
PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS2115AIPWRQ1
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
2115AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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