TPS2148IDGNG4


 SLVS373 − AUGUST 2001     
     
FEATURES D Complete Power Management Solution for D D D D D D D D D DESCRIPTION USB Bus-Powered Peripherals 3.3-V 200 mA Low-Dropout Voltage Regulator With Enable 3.3-V 340-mΩ (Typ) High-Side MOSFET 5-V 340-mΩ (Typ) High-Side MOSFET Independent Thermal- and Short-Circuit Protection for LDO and Each Switch 2.9-V to 5.5-V Operating Range CMOS- and TTL-Compatible Enable Inputs 75-µA (Typ) Supply Current Available in 8-Pin MSOP (PowerPAD) −40°C to 85°C Ambient Temperature Range APPLICATIONS D USB Peripherals The TPS2148 incorporates two power distribution switches and an LDO in one small package, providing a USB peripheral power management solution that saves up to 60% in board space over typical implementations. The TPS2148 meets USB 2.0 bus-powered peripheral requirements. An integrated LDO regulates the 5-V bus power down to 3.3 V for the USB controller, and a MOSFET switch that is internally connected to the output of the LDO simplifies meeting the suspend and enumeration current requirements imposed by the USB specification. A second switch is available to support a downstream port, stage power to a second voltage regulator, or disable power to selected circuitry in power-save modes. Each power-distribution switch is capable of supplying 200 mA of continuous current, and the independent logic enables are compatible with 5-V logic and 3-V logic. The switches and the LDO are designed with controlled rise times and fall times to minimize current surges. − Digital Cameras − Zip Drives − Speakers and Headsets The TPS2148 has active-low enables while the TPS2158 has active-high enables. LDO and dual switch family selection guide and schematics VIN/SW1 LDO LDO_OUT VIN/SW1 LDO TPS2149/59 MSOP−8 TPS2148/58 MSOP−8 TPS2147/57 MSOP−10 TPS2145/55 TSSOP−14 LDO_OUT VIN/SW1 LDO LDO_OUT VIN LDO LDO_OUT LDO_ADJ LDO_EN LDO_EN OC1 OC1 OUT1 OUT1 EN2 EN1 GND OUT2 EN1 EN1 EN1 OUT1 SW2 OUT2 SW2 OUT2 EN2 GND OC2 EN2 GND OC2 OUT1 OC OUT2 EN2 GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. 
 
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 SLVS373 − AUGUST 2001 AVAILABLE OPTIONS TA PACKAGE AND PIN COUNT DESCRIPTION −40°C to 85°C PACKAGED DEVICES ACTIVE LOW (SWITCH) ACTIVE HIGH (SWITCH) Adjustable LDO with LDO enable TSSOP-14 TPS2145IPWP TPS2155IPWP 3.3-V fixed LDO MSOP-10 TPS2147IDGQ TPS2157IDGQ 3.3-V Fixed LDO with LDO enable and LDO output switch MSOP-8 TPS2148IDGN TPS2158IDGN 3.3-V Fixed LDO, shared input with switches MSOP-8 TPS2149IDGN TPS2159IDGN NOTE: All options available taped and reeled. Add an R suffix (e.g. TPS2145IPWPR) TPS2148, TPS2158 MSOP (DGN) PACKAGE (TOP VIEW) OUT1 VIN/SWIN1 LDO_OUT OUT2 1 8 2 7 3 6 4 5 EN1† EN2† LDO_EN GND † Pins 7 and 8 are active high for TPS2158. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Input voltage range: VI(VIN/SWIN1), VI(ENx), VI(LDO_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Output voltage range: VO(OUTx), VO(LDO_OUT), VO(OCx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Continuous output current, IO(OUT), IO(LDO_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual-junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 110°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Electrostatic discharge (ESD) protection: Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Charged device model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltages are with respect to GND. DISSIPATION RATING TABLE 2 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING MSOP8 1455.5 mW 17.1 mW/°C 684.9 mW 428.08 mW www.ti.com 

 SLVS373 − AUGUST 2001 recommended operating conditions VI(VIN/SWIN1) VI(ENx) Input voltage VI(LDO_EN) LDO_OUT Continuous output current, IO Output current limit, IO(LMT) MIN MAX 2.9 5.5 0 5.5 0 5.5 UNIT V 200 OUT1, OUT2 150 mA LDO_OUT 275 550 OUT1, OUT2 200 400 −40 100 °C MAX UNIT Operating virtual-junction temperature range, TJ mA electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, TJ = −40°C to 100°C (unless otherwise noted) general PARAMETER TEST CONDITIONS Off-state supply current VI(VIN/SWIN1) = 5 V Forward leakage current II Total input current at VIN/SWIN1 and SWIN2 VI(VIN/SWIN1) = 5 V, No load on OUTx, No load on LDO_OUT MIN TYP VI(ENx) = 5 V (inactive), VI(LDO_EN) = 0 V (inactive), VO(LDO_OUT) = no load, VO(OUTx) = no load VI(ENx) = 5 V (inactive), VI(LDO_EN) = 0 V (inactive), VO(LDO_OUT) = 0 V, VO(OUTx) = 0 V (measured from outputs to ground) VI(LDO_EN) = 5 V (active), VI(ENx) = on (active) VI(LDO_EN) = 0 V (inactive), VI(ENx) = on (active) VI(LDO_EN) = 5 V (active), VI(ENx) = off (inactive) 20 µA 1 µA 150 µA 100 µA 100 µA MAX UNIT power switches PARAMETER rDS(on) Ilkg(R) Static drain-source on-state resistance, VIN/SWIN1 or SWIN2 to OUTx Reverse leakage current at OUTx TEST CONDITIONS MIN TYP IO(LDO_OUT) = 50 mA, IOUT1 and IOUT2 = 150 mA, TJ = −40°C to 100°C 680 mΩ IO(LDO_OUT) = 50 mA, IOUT1 and IOUT2 = 150 mA, TJ = 25°C VO(OUTx) = 5 V, LDO_EN = don’t care 340 VI(ENx) = 5 V, VI(ENx) = 0 V, VI(VIN/SWIN1) = 5 V 10 VI(ENx) = 5 V, VI(ENx) = 0 V, VI(VIN/SWIN1) = 2.9 V 10 VI(ENx) = 5 V, VI(ENx) = 0 V, VI(VIN/SWIN1) = 0 V 10 IOS Short circuit output current OUTx connected to GND, device enabled into short circuit NOTE 1: Specified by design, not tested in production. www.ti.com 0.2 0.4 µA A 3 

 SLVS373 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, TJ = −40°C to 100°C (unless otherwise noted) timing parameters, power switches PARAMETER TEST CONDITIONS ton Turnon time, OUTx switch, (see Note 1) CL = 100 µF CL = 1 µF RL = 33 Ω toff Turnoff time, OUTx switch (see Note 1) CL = 100 µF CL = 1 µF RL = 33 Ω tr Rise time, OUTx switch (see Note 1) tf Fall time, OUTx switch (see Note 1) CL = 100 µF CL = 1 µF CL = 100 µF CL = 1 µF RL = 33 Ω RL = 33 Ω MIN TYP MAX 0.5 6 0.1 3 5.5 10 0.05 2 0.5 5 0.1 2 5.5 9 0.05 1.2 UNIT ms NOTE 1. Specified by design, not tested in production. undervoltage lockout at VIN/SWIN1 PARAMETER TEST CONDITIONS UVLO Threshold MIN TYP 2.2 Hysteresis (see Note 1) MAX 2.85 260 Deglitch (see Note 1) UNIT V mV µs 50 NOTE 1. Specified by design, not tested in production. undervoltage lockout at switch 2 PARAMETER TEST CONDITIONS UVLO Threshold MIN Hysteresis (see Note 1) Deglitch (see Note 1) 50 www.ti.com MAX 2.85 260 NOTE 1. Specified by design, not tested in production. 4 TYP 2.2 UNIT V mV µs 

 SLVS373 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, VI(ENx) = 0 V, VI(LDO_EN) = 5 V, CL(LDO_OUT) = 10 µF, TJ = −40°C to 100°C (unless otherwise noted) 3.3 V LDO PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT 3.20 3.3 3.40 V Output voltage, dc VI(VIN/SWIN1) = 4.25 V to 5.25 V, IO(LDO_OUT) = 0.5 mA to 200 mA Dropout voltage VI(VIN/SWIN1) = 3.2 V, IO = 200 mA, IO(OUT) = 150 mA 0.35 V Line regulation voltage (see Note 1) VI(VIN/SWIN1) = 4.25 V to 5.25 V, IO(LDO_OUT) = 5 mA 0.1 %/V Load regulation voltage (see Note 1) VI(VIN/SWIN1) = 4.25 V, IO(LDO_OUT) = 5 mA to 200 mA IOS Short-circuit current limit VI(VIN/SWIN1) = 4.25 V, LDO_OUT connected to GND Ilkg(R) Reverse leakage current into LDO_OUT VO 0.275 0.4 1% 0.33 0.55 A VO(LDO_OUT) = 3.3 V, VI(VIN/SWIN1) = 0 V, VI(LDO_EN) = 0 V 10 µA VO(LDO_OUT) = 5.5 V, VI(VIN/SWIN1) = 2.7 V, VI(LDO_EN) = 0 V 10 µA Power supply rejection f = 1 kHz, CL(LDO_OUT) = 4.7 µF, ESR = 0.25 Ω, IO = 5 mA, VI(VIN/SWIN1)p−p = 100 mV 50 dB ton Turnoff time, LDO_EN transitioning low (see Note 1) RL = 16 Ω, CL(LDO_OUT) = 10 µF 0.25 1 ms toff Turnon time, LDO_EN transitioning high (see Note 1) RL = 16 Ω, CL(LDO_OUT) = 10 µF 0.1 1 ms VI(LDO_EN) = 5 V, VIN ramping up from 10% to 90% 0.1 1 ms in 0.1 ms, RL = 16 Ω, CL(LDO_OUT) = 10 µF † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. NOTE 1. Specified by design, not tested in production. Ramp-up time, LDO_OUT (0% to 90%) www.ti.com 5 

 SLVS373 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, 2.9 V ≤ VI(SWIN2) ≤ 5.5 V, VI(ENx) = 0 V, VI(LDO_EN) = 5 V, TJ = −40°C to 100°C (unless otherwise noted) enable input, ENx (active low) PARAMETER VIH VIL High-level input voltage II Input current, pullup (source) TEST CONDITIONS MIN TYP MAX 2 UNIT V Low-level input voltage VI(ENx) = 0 V 0.8 V 5 µA enable input, ENx (active high) PARAMETER VIH VIL High-level input voltage II Input current, pulldown (sink) TEST CONDITIONS MIN TYP MAX 2 UNIT V Low-level input voltage VI(ENx) = 5 V 0.8 V 5 µA enable input, LDO_EN (active high) PARAMETER VIH VIL High-level input voltage II Input current, pulldown TEST CONDITIONS MIN TYP MAX 2 V Low-level input voltage VI(LDO_EN) = 5 V Falling-edge deglitch (see Note 1) UNIT 0.8 V 5 µA µs 50 NOTE 1. Specified by design, not tested in production. thermal shutdown characteristics PARAMETER First thermal shutdown (shuts down switch or regulator in overcurrent) TEST CONDITIONS Occurs at or above specified temperature when overcurrent is present. Recovery from thermal shutdown Second thermal shutdown (shuts down all switches and regulator) TYP Occurs on rising temperature, irrespective of overcurrent. UNIT °C 155 10 www.ti.com MAX 120 110 Second thermal shutdown hysteresis 6 MIN 

 SLVS373 − AUGUST 2001 TPS2148 functional block diagram 3.3 V / 200 mA LDO VIN/SWIN1 LDO_OUT LDO_EN CS Charge Pump Driver OUT2 Current Limit EN2 Thermal Sense OUT1 CS Driver Current Limit EN2 Thermal Sense GND Terminal Functions TERMINAL NAME NO. TPS2148 EN1 EN1 I/O DESCRIPTION TPS2158 8 I Logic level enable to transfer power to OUT1 7 I Logic level enable to transfer power to OUT2 8 EN2 EN2 7 GND 5 5 LDO_EN 6 6 I Logic level LDO enable. Active high. LDO_OUT 3 3 O LDO output OUT1 1 1 O Switch 1 output OUT2 4 4 VIN/SWIN1 2 2 Ground Switch 2 output I Input for LDO and switch 1; device supply voltage www.ti.com 7 

 SLVS373 − AUGUST 2001 detailed description VIN/SWIN1 The VIN/SWIN1 serves as the input to the internal LDO and as the input to one N-channel MOSFET. The 3.3-V LDO has a dropout voltage of 0.35 V and is rated for 200 mA of continuous current. The power switch is an N-channel MOSFET with a maximum on-state resistance of 580 mΩ. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch is rated at 150 mA, continuous current. VIN/SWIN1 must be connected to a voltage source for device operation. OUTx OUT1 and OUT2 are the outputs from the internal power-distribution switches. LDO_OUT LDO_OUT is the output of the internal 200-mA LDO. It is also the input to a second power switch. This power switch in an N-channel MOSFET with a maximum on-state resistance of 580 mΩ. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch is rated at 150 mA, continuous current. LDO_EN The active high input, LDO_EN, is used to enable the internal LDO and is compatible with TTL and CMOS logic. enable (ENx, ENx) The logic enable disables the power switch. Both switches have independent enables and are compatible with both TTL and CMOS logic. current sense A sense FET monitors the current supplied to the load. Current is measured more efficiently by the sense FET than by conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load. thermal sense A dual-threshold thermal trip is implemented to allow fully independent operation of the power distribution switches. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature rises to approximately 120°C, the internal thermal sense circuitry determines which power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the adjacent power switch. Because hysteresis is built into the thermal sense, the switch turns back on after the device has cooled approximately 10 degrees. The switch continues to cycle off and on until the fault is removed. undervoltage lockout A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2.5 V, a control signal turns off the power switch. 50% VI(ENx) 50% tpd(off) ton toff tpd(on) 90% VO(OUTx) 90% 10% 10% tr VO(OUTx) tf 90% 90% 10% 10% TIMING Figure 1. Timing and Internal Voltage Regulator Transition Waveforms 8 www.ti.com 

 SLVS373 − AUGUST 2001 TYPICAL CHARACTERISTICS SWITCH TURNON DELAY AND RISE TIME WITH 1-µF LOAD SWITCH TURNOFF DELAY AND FALL TIME WITH 1-µF LOAD VI(EN) (5 V/div) VI(EN) (5 V/div) VO(OUT) (2 V/div) VO(OUT) (2 V/div) VI = 5 V TA = 25°C CL = 1 µF RL = 25 Ω VI = 5 V TA = 25°C CL = 1 µF RL = 25 Ω 0 0.4 0.8 1.2 1.6 2 2.4 2.8 t − Time − ms 3.2 3.6 0 4.2 0.4 0.8 1.2 Figure 2 1.6 2 2.4 2.8 t − Time − ms 3.2 3.6 4.2 Figure 3 SWITCH TURNOFF DELAY AND FALL TIME WITH 120-µF LOAD SWITCH TURNON DELAY AND RISE TIME WITH 120-µF LOAD VI(EN) (5 V/div) VI(EN) (5 V/div) VO(OUT) (2 V/div) VO(OUT) (2 V/div) VI = 5 V TA = 25°C CL = 120 µF RL = 25 Ω VI = 5 V TA = 25°C CL = 120 µF RL = 25 Ω 0 2 4 6 8 10 12 14 t − Time − ms 16 18 20 Figure 4 0 4 8 12 16 20 24 28 t − Time − ms 32 36 40 Figure 5 www.ti.com 9 

 SLVS373 − AUGUST 2001 TYPICAL CHARACTERISTICS SHORT-CIRCUIT CURRENT, SWITCH ENABLED INTO A SHORT LDO TURNON DELAY AND RISE TIME WITH 4.7-µF LOAD VI(EN) (5 V/div) VI = 5 V TA = 25°C CL = 4.7 µF RL = 13.2 Ω VI(LDO_EN) (5 V/div) VO(LDO_OUT) (1 V/div IO(OUT) (100 mA/div) 0 1 2 3 4 5 6 t − Time − ms 7 8 9 10 0 Figure 6 0.8 1.2 1.6 2 2.4 2.8 t − Time − ms 3.2 3.6 4.2 Figure 7 LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE IO(LDO_OUT) 5.25 V VI(VIN) 4.25 V (200 mA/div) ∆VO(LDO_OUT) (100 mV/div) ∆VO(LDO_OUT) (0.05 V/div) TA = 25°C CL(LDO_OUT) = 4.7 µF ESR = 1 Ω IO(LDO_OUT) = 200 mA 0 TA = 25°C CL(LDO_OUT) = 4.7 µF ESR = 1 Ω 100 200 300 400 500 600 700 800 900 1000 t − Time − µs 0 100 200 300 400 500 600 700 800 900 1000 t − Time − µs Figure 9 Figure 8 10 0.4 www.ti.com 

 SLVS373 − AUGUST 2001 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE 140 140 120 120 I DD − Supply Current − µ A I DD − Supply Current − µ A SUPPLY CURRENT vs JUNCTION TEMPERATURE 100 80 60 40 80 60 40 20 20 0 −40 100 −20 0 20 40 60 80 0 2.5 100 3 TJ − Temperature − °C rDS(on) − Static Drain-Source On-State Resistance − Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 0.6 0.55 0.5 0.45 SW1 0.4 SW2 0.35 0.3 0.25 0.2 0.15 0.1 −40 −20 5 5.5 Figure 11 0 20 40 60 80 TJ − Junction Temperature − °C 100 rDS(on) − Static Drain-Source On-State Resistance − Ω Figure 10 3.5 4 4.5 VCC − Supply Voltage − V Figure 12 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs SUPPLY VOLTAGE 0.38 0.37 0.36 0.35 SW1 0.34 SW2 0.33 0.32 0.31 0.3 2.5 3 3.5 4 4.5 VCC − Supply Voltage 5 5.5 Figure 13 www.ti.com 11 

 SLVS373 − AUGUST 2001 TYPICAL CHARACTERISTICS SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE 400 400 380 380 360 360 Short Circuit Current − mA Short Circuit Current − mA SHORT CIRCUIT CURRENT vs JUNCTION TEMPERATURE 340 320 300 SW1 280 SW2 260 340 320 SW1 300 280 260 240 240 220 220 200 −40 −20 0 20 40 60 80 TJ − Free-Air Temperature − °C 200 2.5 100 SW2 3 3.5 4 4.5 VCC − Supply Voltage Figure 14 Figure 15 UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 2.9 UVLO − Undervoltage Lockout − V 2.8 2.7 Rising 2.6 2.5 2.4 Falling 2.3 2.2 2.1 −40 −25 −10 5 20 35 50 65 80 TJ − Junction Temperature − °C Figure 16 12 www.ti.com 95 110 5 5.5 

 SLVS373 − AUGUST 2001 APPLICATION INFORMATION Upstream Data Port 1.5 kΩ D+ D− GND USB Function Controller TPS2148 5V 4.7 µF 0.1 µF 5-V Circuitry 3.3 V LDO 10 µF 0.1 µF 3.3 V Circuitry Figure 17. Example of a Peripheral Design With TPS2148 external capacitor requirements on power lines A ceramic bypass capacitor (0.01-µF to 0.1-µF) between VIN/SWIN1 and GND, close to the device, is recommended to improve load transient response and noise rejection. A bulk capacitor (4.7-µF ) between VIN/SWIN1 and GND is also recommended, especially if load transients in the hundreds of milliamps with fast rise times are anticipated. A 66-µF bulk capacitor is recommended from OUTx to ground, especially when the output load is heavy. This precaution helps reduce transients seen on the power rails. Additionally, bypassing the outputs with a 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients. LDO output capacitor requirements Stabilizing the internal control loop requires an output capacitor connected between LDO_OUT and GND. The minimum recommended capacitance is a 4.7 µF with an ESR value between 200 mΩ and 10 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the ESR requirements. overcurrent A sense FET is used to measure current through the device. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current. Complete shut down occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output is shorted before the device is enabled or before VIN has been applied. The TPS2148 and TPS2158 sense the short and immediately switches to a constant-current output. In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high currents may flow for a very short time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded. The TPS2148 and TPS2158 are capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. www.ti.com 13 

 SLVS373 − AUGUST 2001 APPLICATION INFORMATION power dissipation and junction temperature The main source of power dissipation for the TPS2148 and TPS2158 comes from the internal voltage regulator and the N-channel MOSFETs. Checking the power dissipation and junction temperature is always a good design practice and it starts with determining the rDS(on) of the N-channel MOSFET according to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from the graphs shown in the Typical Characteristics section of this data sheet. Using this value, the power dissipation per switch can be calculated using: P D + r DS(on) I2 (1) Multiply this number by two to get the total power dissipation coming from the N-channel MOSFETs. The power dissipation for the internal voltage regulator is calculated using: ǒ P D + V –V I O(min) Ǔ I O (2) The total power dissipation for the device becomes: P D(total) + P D(voltage regulator) ǒ ) 2 P D(switch) Ǔ (3) Finally, calculate the junction temperature: TJ + PD R qJA ) T A (4) Where: TA = Ambient Temperature °C RθJA = Thermal resistance °C/W, equal to inverting the derating factor found on the power dissipation table in this datasheet. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. 14 www.ti.com 

 SLVS373 − AUGUST 2001 APPLICATION INFORMATION thermal protection Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS2148 and TPS2158 into constant-current mode at first, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The TPS2148 and TPS2158 implement a dual thermal trip to allow fully independent operation of the power distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die temperature rises to approximately 120°C, the internal thermal sense circuitry checks which power switch is in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 120°C and reach 155°C, the device will turn off. undervoltage lockout (UVLO) An undervoltage lockout ensures that the device (LDO and switches) is in the off state at power up. The UVLO will also keep the device from being turned on until the power supply has reached the start threshold (see undervoltage lockout table), even if the switches are enabled. The UVLO will also be activated whenever the input voltage falls below the stop threshold as defined in the undervoltage lockout table. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switches before input power is removed. Upon reinsertion, the power switches will be turned on with a controlled rise time to reduce EMI and voltage overshoots. universal serial bus (USB) applications The universal serial bus (USB) interface is a multiplexed serial bus operating at either 12 Mb/s, or 1.5 Mb/s for USB 1.1, or 480 Mb/s for USB 2.0. The USB interface is designed to accommodate the bandwidth required by PC peripherals such as keyboards, printers, scanners, and mice. The four-wire USB interface was conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub or across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: • • • • • Hosts/self-powered hubs (SPH) Bus-powered hubs (BPH) Low-power, bus-powered functions High-power, bus-powered functions Self-powered functions The TPS2148 and TPS2158 are well suited for USB peripheral applications. www.ti.com 15 

 SLVS373 − AUGUST 2001 APPLICATION INFORMATION USB power distribution requirements USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented. • Hosts/self-powered hubs must: − − Current-limit downstream ports Report overcurrent conditions on USB VBUS D Bus-powered hubs must: − − − Enable/disable power to downstream ports Power up at