TPS2211APWPG4

  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 D Fully Integrated VCC and Vpp Switching for DB PACKAGE† (TOP VIEW) Single-Slot PC Card Interface D Low rDS(on) (70-mΩ 5-V VCC Switch and VCCD0 VCCD1 3.3V 3.3V 5V 5V GND OC 3.3-V VCC Switch) D Compatible With Industry-Standard Controllers D 3.3-V Low-Voltage Mode D Meets PC Card Standards D 12-V Supply Can Be Disabled Except D D D D 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SHDN VPPD0 VPPD1 AVCC AVCC AVCC AVPP 12V † TPS2211A is pin-for-pin compatible with TPS2211 and TPS2212. During 12-V Flash Programming Short-Circuit and Thermal Protection Space-Saving 16-Pin SSOP (DB) and 20-Pin HTSSOP (PWP) Compatible With 3.3-V, 5-V, and 12-V PC Cards Break-Before-Make Switching PW and PWP§ PACKAGE (TOP VIEW) VCCD0 VCCD1 3.3 V 3.3 V 5V 5V NC GND OC 12 V description 1 2 3 4 5 6 7 8 9 10 See Note 20 19 18 17 16 15 14 13 12 11 SHDN VPPD0 VPPD1 NC AVCC AVCC ‡ AVCC AVCC NC AVPP The TPS2211A PC Card power-interface switch provides an integrated power-management solution for a single PC Card. All of the discrete power MOSFETs, a logic section, current limiting, and NC − No internal connection thermal protection for PC Card control are ‡ Must be tied together externally as close to the device as combined on a single integrated circuit, using the possible. §PowerPAD applies to PWP package only. Texas Instruments LinBiCMOS process. The circuit allows the distribution of 3.3-V, 5-V, and/or 12-V card power, and is compatible with many PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card. controllers. The current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card. The TPS2211A features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. Bias power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs such as sleep mode and pager mode where only 3.3 V is available. End equipment for the TPS2211A includes notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras, and bar-code scanners. AVAILABLE OPTIONS PACKAGED DEVICE TA PLASTIC SMALL OUTLINE (DB) PLASTIC SMALL OUTLINE (PW) PowerPAD PLASTIC SMALL OUTLINE (PWP) −40°C to 85°C TPS2211AIDB TPS2211APW TPS2211APWP The DB, PW, and PWP packages are only available left-end taped and reeled (indicated by the R suffix on the device type, e.g. TPS2211AIDBR). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association). LinBiCMOS, PowerPAD are trademarks of Texas Instruments. Copyright  2002, Texas Instruments Incorporated  
  
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  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 SELECTION GUIDE VCC Vpp 3.3-V TYPICAL rDS(on) (Ω) 5-V TYPICAL rDS(on) (Ω) RECOMMENDED MAXIMUM OUTPUT CURRENT (A) TPS2211AIDB 0.07 0.07 1 4 2 0.15 TPS2211APW 0.07 0.07 1 4 2 0.15 TPS2211APWP 0.07 0.07 1 4 2 0.15 TPS2211IDB 0.048 0.05 1 4 1 0.15 TPS2212IDB 0.16 0.16 0.25 4 1 0.15 DEVICE 3.3-V OR 5-V TYPICAL rDS(on) (Ω) 12-V MAXIMUM rDS(on) (Ω) RECOMMENDED MAXIMUM OUTPUT CURRENT (A) typical PC-card power-distribution application 12 V 0.1 µF +† TPS2211A AVCC 12 V AVCC AVCC ‡ 0.1 µF AVPP VCC1 VCC2 PC Card Vpp1 Connector Vpp2 0.1 µF 5V 0.1 µF 3.3 V 0.1 µF +† 5V 5V PCMCIA Controller +† 3.3 V VCCD0 VCC_EN0 3.3 V VCCD1 VCC_EN1 VPPD0 VPPD1 VPP_EN0 OC GND VPP_EN1 To CPU CS SHDN Shutdown Signal From CPU † Refer to power-supply considerations in application information for selection of appropiate capacitors on supply inputs. ‡ The diagram refers to the 16-pin DB package. It is recommended that the 3 AVCC pins be tied together externally to minimize power loss. For the 20-pin package, the 4 AVCC pins (13, 14, 15, and 16) must be tied together externally as close as possible to the device. 2 WWW.TI.COM 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION PW, PWP DB 3.3V 3, 4 3, 4 I 3.3-V VCC input for card power and/or chip power if 5 V is not present 5V 5, 6 5, 6 I 5-V VCC input for card power and/or chip power 12V 10 9 I 12-V Vpp input card power AVCC 13, 14, 15, 16 11, 12, 13 O Switched output that delivers 0 V, 3.3-V, 5-V, or high impedance to card; must be tied together externally for the 20-pin PWP package. AVPP 11 10 O Switched output that delivers 0 V, 3.3-V, 5-V, 12-V, or high impedance to card GND 8 7 NC 7, 12, 17 − OC 9 8 O Logic-level overcurrent reporting output that goes low when an overcurrent conditions exists SHDN 20 16 I Logic input that shuts down the device and sets all power outputs to high-impedance state VCCD0 1 1 I Logic input that controls voltage of AVCC (see control-logic table) VCCD1 2 2 I Logic input that controls voltage of AVCC (see control-logic table) VPPD0 19 15 I Logic input that controls voltage of AVPP (see control-logic table) VPPD1 18 14 I Logic input that controls voltage of AVPP (see control-logic table) Ground No internal connection absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Input voltage range for card power: VI(5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V VI(3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V VI(12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 14 V Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Output current (each card): IO(VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited IO(VPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DB−16 800 mW 8.0 mW/°C 440 mW 320 mW PW−20 741.3 mW 7.41 mW/°C 407.7 mW 296.5 mW PWP−20 2740 mW 27.4 mW/°C 1507 mW 1096 mW These devices are mounted on a Low-K PCB with 0 LFM. WWW.TI.COM 3 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 recommended operating conditions Input voltage, VI Output current MIN MAX UNIT VI(5V) VI(3.3V) 0 5.25 V 0 5.25 V VI(12V) IO(AVCC) 0 13.5 V 1 IO(AVPP) Operating virtual junction temperature, TJ A 150 mA −40 125 °C TYP MAX UNIT 70 120 70 120 TA = 25°C TA = 25°C 4 6 4 6 TA = 25°C Ipp at 10 mA 1 2 0.3 0.8 V 0.1 0.8 V 1 10 electrical characteristics, TA = −40°C to 85°C (unless otherwise noted) power switch TEST CONDITIONS† PARAMETER 5 V to AVCC VI(5V) = 5 V VI(3.3V) = 3.3 V 3.3 V to AVCC Switch resistance 5 V to AVPP 3.3 V to AVPP 12 V to AVPP VO(AVPP) VO(AVCC) Clamp low voltage Clamp low voltage Ipp high-impedance state Ilkg Leakage current ICC high-impedance state II Input current VI(5V) = 5 V VI(5V) = 0 V, VI(3.3V) = 3.3 V Shutdown mode IOS Short-circuit output-current limit IO(AVCC) IO(AVPP) Thermal shutdown‡ Trip point, TJ MIN ICC at 10 mA TA = 25°C TA = 85°C TA = 25°C 50 1 10 TA = 85°C VO(AVCC) = 5 V, VO(AVPP) = 12 V 40 75 VO(AVCC) = 3.3 V, VO(AVPP) = 12 V 50 90 Ω µA A 50 VO(AVCC) = VO(AVPP) = Hi-Z TA = 85 85°C, C, output powered into a short to GND mΩ µA 1 1 180 2.5 A 400 mA °C 140 Hysteresis 10 °C † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. ‡ Specified by design, not tested in production. logic section PARAMETER TEST CONDITIONS† MIN Logic input current 1 Logic input high level 2 Logic input low level Logic output high level, OC MAX IO = 0.2 mA IO = 0.2 mA, VI(3.3V) = 3.3 V VI(5V) − 0.4 VI(3.3V) − 0.4 µA V 0.8 VI(5V) = 5 V, VI(5V) = 0 V, UNIT V V Logic output low level, OC IO = 1 mA 0.4 V † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. 4 WWW.TI.COM 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 switching characteristics‡ TEST CONDITIONS§ PARAMETER MIN TYP Rise times, output VO(AVCC) (5 V) VO(AVPP) (12 V) 2.8 tr Fall times, output VO(AVCC) (5 V) VO(AVPP) (12 V) 5 tf tpd Propagation delay (see Figure1) MAX UNIT 6 ms 19 VI(VPPD0) to VO(AVPP) (12 V) ton toff 7 2.8 VI(VCCD1) to VO(AVCC) (3.3 V) ton toff VI(VCCD0) to VO(AVCC) (5 V) ton toff 3.7 23 ms 12 13 ‡ Switching characteristics are with CL = 150 µF. §Refer to Parameter Measurement Information PARAMETER MEASUREMENT INFORMATION AVPP AVCC CL CL LOAD CIRCUIT VI(VPPD0) (VI(VPPD1) = 0 V) LOAD CIRCUIT VDD 50% 50% GND VDD VI(VCCD1) (VI(VCCD0) = VDD) GND toff toff ton VO(AVPP) 50% 50% ton VI(12V) 90% 10% VI(3.3V) 90% VO(AVCC) 10% GND VOLTAGE WAVEFORMS GND VOLTAGE WAVEFORMS Figure 1. Test Circuits and Voltage Waveforms Table of Timing Diagrams FIGURE AVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch 2 AVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch 3 AVCC Propagation Delay and Rise Time With 150-µF Load, 3.3-V Switch 4 AVCC Propagation Delay and Fall Time With 150-µF Load, 3.3-V Switch 5 AVCC Propagation Delay and Rise Time With 1-µF Load, 5-V Switch 6 AVCC Propagation Delay and Fall Time With 1-µF Load, 5-V Switch 7 AVCC Propagation Delay and Rise Time With 150-µF Load, 5-V Switch 8 AVCC Propagation Delay and Fall Time With 150-µF Load, 5-V Switch 9 AVPP Propagation Delay and Rise Time With 1-µF Load, 12-V Switch 10 AVPP Propagation Delay and Fall Time With 1-µF Load, 12-V Switch 11 AVPP Propagation Delay and Rise Time With 150-µF Load, 12-V Switch 12 AVPP Propagation Delay and Fall Time With 150-µF Load, 12-V Switch 13 WWW.TI.COM 5 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCCD0 = 3.3 V VCCD0 = 3.3 V VCCD1 (2 V/div) VCCD1 (2 V/div) AVCC (2 V/div) AVCC (2 V/div) 0 1 2 3 4 5 6 7 8 0 9 5 10 t − Time − ms Figure 2. AVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch 30 35 40 45 Figure 3. AVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch VCCD0 = 3.3 V VCCD0 = 3.3 V VCCD1 (2 V/div) VCCD1 (2 V/div) AVCC (2 V/div) AVCC (2 V/div) 0 1 2 3 4 5 t − Time − ms 6 7 8 0 9 Figure 4. AVCC Propagation Delay and Rise Time With 150-µF Load, 3.3-V Switch 6 15 20 25 t − Time − ms 5 10 15 20 25 t − Time − ms 30 35 40 45 Figure 5. AVCC Propagation Delay and Fall Time With 150-µF Load, 3.3-V Switch WWW.TI.COM 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCCD0 (2 V/div) VCCD0 (2 V/div) AVCC (2 V/div) AVCC (2 V/div) VCCD1 = 5 V 0 1 2 3 4 5 t − Time − ms 6 7 8 9 Figure 6. AVCC Propagation Delay and Rise Time With 1-µF Load, 5-V Switch VCCD1 = 5 V 0 5 10 15 20 25 t − Time − ms 30 35 40 45 Figure 7. AVCC Propagation Delay and Fall Time With 1-µF Load, 5-V Switch VCCD0 (2 V/div) VCCD0 (2 V/div) AVCC (2 V/div) AVCC (2 V/div) VCCD1 = 5 V 0 1 2 3 4 5 t − Time − ms 6 7 8 9 Figure 8. AVCC Propagation Delay and Rise Time With 150-µF Load, 5-V Switch VCCD1 = 5 V 0 5 10 15 20 25 t − Time − ms 30 35 40 45 Figure 9. AVCC Propagation Delay and Fall Time With 150-µF Load, 5-V Switch WWW.TI.COM 7 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VPPD1 = 0 V VPPD0 (2 V/div) VPPD0 (2 V/div) AVPP (5 V/div) AVPP (5 V/div) VPPD1 = 0 V 0 0.2 0.4 0.6 0.8 1 1.2 t − Time − ms 1.4 1.6 0 1.8 Figure 10. AVPP Propagation Delay and Rise Time With 1-µF Load, 12-V Switch 1 2 3 4 5 t − Time − ms 6 7 8 9 Figure 11. AVPP Propagation Delay and Fall Time With 1-µF Load, 12-V Switch VPPD1 = 0 V VPPD0 (2 V/div) VPPD0 (2 V/div) AVPP (5 V/div) AVPP (5 V/div) VPPD1 = 0 V 0 2 4 6 8 10 12 t − Time − ms 14 16 Figure 12. AVPP Propagation Delay and Rise Time With 150-µF Load, 12-V Switch 8 0 18 5 10 15 20 25 30 t − Time − ms 35 40 45 Figure 13. AVPP Propagation Delay and Fall Time With 150-µF Load, 12-V Switch WWW.TI.COM 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE ICC(5V) ICC(3.3V) Supply current vs Junction temperature 14 Supply current vs Junction temperature 15 rDS(on) Static drain-source on-state resistance, 5-V VCC switch vs Junction temperature 16 rDS(on) Static drain-source on-state resistance, 3.3-V VCC switch vs Junction temperature 17 rDS(on) Static drain-source on-state resistance, 12-V VPP switch vs Junction temperature 18 VO(AVCC) VO(AVCC) Output voltage, 5-V VCC switch vs Output current 19 Output voltage, 3.3-V VCC switch vs Output current 20 VO(AVPP) IOS(AVCC) Output voltage, 12-V VPP switch vs Output current 21 Short-circuit current, 5-V VCC switch vs Junction temperature 22 IOS(AVCC) IOS(AVPP) Short-circuit current, 3.3-V VCC switch vs Junction temperature 23 Short-circuit current, 12-V VPP switch vs Junction temperature 24 5-V SUPPLY CURRENT vs JUNCTION TEMPERATURE 3.3-V SUPPLY CURRENT vs JUNCTION TEMPERATURE 50 VO(AVCC) = 5 V VO(AVPP) = 12 V No Load 60 I CC − Supply Current − µ A I CC − Supply Current − µ A 46 65 42 38 34 30 −50 VO(AVCC) = 3.3 V VO(AVPP) = 12 V No Load 55 50 45 −25 0 25 50 75 100 TJ − Junction Temperature − °C 125 Figure 14 40 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C 125 Figure 15 WWW.TI.COM 9 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 3.3-V AVCC SWITCH STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 110 VI(5V) VO(AVCC) = 5 V 100 90 80 70 60 50 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C 125 DS(on) − Static Drain-Source On-State Resistance − mΩ 5-V AVCC SWITCH STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE r r DS(on) − Static Drain-Source On-State Resistance − mΩ TYPICAL CHARACTERISTICS 100 VI(3.3V) = 3.3 V VO(AVCC) = 3.3 V 90 80 70 60 50 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C r Figure 17 12-V AVCC SWITCH 5-V AVCC SWITCH STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE OUTPUT VOLTAGE vs OUTPUT CURRENT 1500 1400 5 VI(5V) = 5 V VO(AVPP) = 12 V VI(12V) = 12 V VO(AVCC) − Output Voltage − V DS(on) − Static Drain-Source On-State Resistance − mΩ Figure 16 1300 1200 1100 1000 900 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C 4.98 −40°C 25°C 4.96 85°C 4.94 125°C 4.92 4.9 0 0.2 0.4 0.6 0.8 IO(AVCC) − Output Current − A Figure 18 10 125 Figure 19 WWW.TI.COM 1 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 TYPICAL CHARACTERISTICS 3.3-V AVCC SWITCH 12-V AVCC SWITCH OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 12 3.28 −40°C VO(AVPP) − Output Voltage − V VO(AVCC) − Output Voltage − V 3.3 25°C 3.26 85°C 3.24 125°C 3.22 3.2 0 0.2 0.4 0.6 0.8 11.95 25°C 11.9 85°C 11.85 125°C 11.8 11.75 1 −40°C 0 0.03 IO(AVCC) − Output Current − A 0.06 Figure 20 5-V AVCC SWITCH 0.15 3.3-V AVCC SWITCH SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 1.6 1.95 I OS(AVCC)− Short-Circuit Output Current − mA I OS(AVCC)− Short-Circuit Output Current − mA 0.12 Figure 21 SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 1.57 1.54 1.51 1.48 1.45 −50 0.09 IO(AVPP) − Output Current − A −25 0 25 50 75 100 125 TJ − Junction Temperature − °C 1.92 1.89 1.86 1.83 1.8 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C Figure 22 Figure 23 WWW.TI.COM 11 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 TYPICAL CHARACTERISTICS I OS(AVPP) − Short-Circuit Output Current − mA SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 0.33 0.32 0.31 0.3 0.29 0.28 0.27 0.26 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C Figure 24 APPLICATION INFORMATION overview PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with limited onboard memory. The idea of add-in cards quickly took hold; modems, wireless LANs, GPS systems, multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International Association) was established, comprised of members from leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the plug and play concept, i.e. cards and hosts from different vendors should be compatible. PC Card power specification System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connectors. This power interface consists of two VCC, two Vpp, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two Vpp terminals were originally specified as separate signals but are commonly tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the Vpp terminals. 12 WWW.TI.COM 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION designing for voltage regulation The current PCMCIA specification for output voltage regulation of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply has an output voltage regulation (VPS(reg)) of 2% (100 mV). Also, a voltage drop from the power supply to the PC Card results from resistive losses (VPCB) in the PCB traces and the PCMCIA connector. A typical design limits the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the allowable voltage drop (VDS) for the TPS2211 is the PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops: V DS + V OǒregǓ – V PSǒregǓ – V PCB Typically, this leaves 100 mV for the allowable voltage drop across the TPS2211A. The voltage drop is the output current multiplied by the switch resistance of the TPS2211. Therefore, the maximum output current that can be delivered to the PC Card in regulation is the allowable voltage drop across the TPS2211A divided by the output switch resistance. V I Omax + r DS DSǒonǓ The AVCC outputs deliver 1 A continuous at 5 V and 3.3 V within regulation over the operating temperature range. Using the same equations, the PCMCIA specification for output voltage regulation of the 3.3 V output is 300 mV. Using the voltage drop percentages for power supply regulation (2%) and PCB resistive loss (1%), the allowable voltage drop for the 3.3 V switch is 200 mV. The 12-V outputs (AVPP) of the TPS2211A can deliver 150 mA continuously. overcurrent and overtemperature protection PC Cards are inherently subject to damage from mishandling. Host systems require protection against short-circuited cards that could lead to power supply or PCB trace damage. Even systems sufficiently robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card, resulting in a sudden loss of system power. Most hosts include fuses for protection. The reliability of fused systems is poor and requires troubleshooting and repair, usually by the manufacturer, when fuses are blown. The TPS2211A uses sense FETs to check for overcurrent conditions in each of the AVCC and AVPP outputs. Unlike sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent condition is detected, only the power output affected is limited; all other power outputs continue to function normally. The OC indicator, normally a logic high, is a logic low when an overcurrent condition is detected providing for initiation of system diagnostics and/or sending a warning message to the user. During power up, the TPS2211A controls the rise time of the AVCC and AVPP outputs and limits the current into a faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card), current is initially limited only by the impedance between the short and the power supply. In extreme cases, as much as 10 A to 15 A may flow into the short before the current limiting of the TPS2211A engages. If the AVCC or AVPP outputs are driven below ground, the TPS2211A may latch nondestructively in an off state. Cycling power reestablishes normal operation. Overcurrent limiting for the AVCC outputs is designed to activate if powered up into a short in the range of 1 A to 2.5 A, typically at about 1.6 A. The AVPP outputs limit from 180 mA to 400 mA, typically around 280 mA. The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full shutdown of the supply. Shutdown occurs only during thermal limiting. Thermal limiting prevents destruction of the IC from overheating if the package power dissipation ratings are exceeded. Thermal limiting disables power output until the device has cooled. WWW.TI.COM 13 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION 12-V supply not required Most PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which require that power be present at all times. The TPS2211A offers considerable power savings by using an internal charge pump to generate the required higher voltages from the 5-V input. Therefore, the external 12-V supply can be disabled except when needed for flash-memory functions, thereby extending battery lifetime. Do not ground the 12-V switch inputs when the 12-V input is not used. Additional power savings are realized by the TPS2211A during a software shutdown, in which quiescent current drops to a maximum of 1 µA. 3.3-V low-voltage mode The TPS2211A operates in a 3.3-V low-voltage mode when 3.3 V is the only available input voltage (VI(5V) = 0). This allows host and PC Cards to be operated in low-power 3.3-volts-only modes such as sleep or pager modes. Note that in these operation modes, the TPS2211A derives its bias current from the 3.3-V input pin and only 3.3 V can be delivered to the PC Card. voltage transitioning requirement PC Cards are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2211A meets all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on 3.3-V compatible cards be discharged to below 0.8 V before applying 3.3-V power. This functions as a power reset and ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge. The TPS2211A offers a selectable VCC and Vpp ground state, in accordance with PCMCIA 3.3-V/5-V switching specifications. output ground switches PC Card specification requires that VCC be discharged within 100 ms. PC Card resistance can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. power-supply considerations The TPS2211A has multiple pins for each of its 3.3-V and 5-V power inputs and for the switched AVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and lost power. It is recommended that all input and output power pins be paralleled for optimum operation. To increase the noise immunity of the TPS2211A, the power supply inputs should be bypassed with a 4.7-µF, or larger, electrolytic or tantalum capacitor paralleled by a 0.1-µF ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1-µF, or larger, ceramic capacitor; doing so improves the immunity of the TPS2211A to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2211A and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below −0.3 V. 14 WWW.TI.COM 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION calculating junction temperature The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die and the current through the switch. To calculate TJ, first find rDS(on) from Figures 16 through 18 using an initial temperature estimate about 50°C above ambient. Then calculate the power dissipation for each switch, using the formula: P D + r DSǒonǓ I2 Next, sum the power dissipation and calculate the junction temperature: TJ + ǒȍ PD Ǔ R qJA ) T A, R qJA + 108°CńW Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate. ESD protection All TPS2211A inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV human-bodymodel discharge as defined in MIL-STD-883C, Method 3015. The AVCC and AVPP outputs can be exposed to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV. TPS2211A 3.3 V 3.3 V 5V 5V 12 V 3 S1 4 S2 5 S3 See Note B CS Card B 13 12 11 51 VCC1 VCC2 S4 6 S5 9 17 S6 CS 18 10 52 Vpp1 Vpp2 See Note A CPU 16 15 Controller 14 1 2 8 Internal Current Monitor SHDN Thermal VPPD0 VPPD1 VCCD0 VCCD1 GND OC 7 NOTE A: MOSFET switch S6 has a back-gate diode from the source to the drain. Unused switch inputs should never be grounded. NOTE B: The diagram refers to the 16-pin DB package. Figure 25. Internal Switching Matrix, TPS2211A Control Logic WWW.TI.COM 15 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION TPS2211A control logic AVPP CONTROL SIGNALS INTERNAL SWITCH SETTINGS SHDN VPPD0 VPPD1 S4 1 0 0 1 0 1 1 1 OUTPUT S5 S6 AVPP CLOSED OPEN OPEN 0V OPEN CLOSED OPEN AVCC† 0 OPEN OPEN CLOSED VPP (12 V) 1 1 1 OPEN OPEN OPEN Hi-Z 0 X X OPEN OPEN OPEN Hi-Z † Output depends on AVCC AVCC CONTROL SIGNALS INTERNAL SWITCH SETTINGS OUTPUT SHDN VCCD1 VCCD0 S1 S2 S3 AVCC 1 0 0 CLOSED OPEN OPEN 0V 1 0 1 OPEN CLOSED OPEN 3.3 V 1 1 0 OPEN OPEN CLOSED 5V 1 1 1 CLOSED OPEN OPEN 0V 0 X X OPEN OPEN OPEN Hi-Z 12-V flash memory supply The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 1, the only external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of PCB space when implemented with surface-mount components. An enable input is provided to shut the converter down and reduce the supply current to 3 µA when 12 V is not needed. The TPS6734 is a 170-kHz current-mode PWM ( pulse-width modulation) controller with an n-channel MOSFET power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use. For additional information, see the TPS6734 data sheet (SLVS127). 16 WWW.TI.COM 
  
    
 
       
  SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION 3.3 V or 5 V R1 10 kΩ ENABLE (see Note A) C1 33 µF, 20 V TPS6734 1 VCC EN + 2 REF 3 SS FB 8 L1 18 µH 7 U1 OUT 4 D1 6 TPS2211A AVCC C5 5 COMP 12 V GND AVCC AVCC + 33 µF, 20 V C2 0.01 µF 12 V 0.1 µF C4 0.001 µF AVPP 0.1 µF 5V 0.1 µF 3.3 V 0.1 µF + + 5V 10 µF 10 µF 5V 3.3 V VCCD0 3.3 V VCCD1 VPPD0 VPPD1 OC GND To CPU SHDN NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high. Figure 26. TPS2211A With TPS6734 12-V, 120-mA Supply WWW.TI.COM 17 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS2211AIDB ACTIVE SSOP DB 16 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PU2211A Samples TPS2211AIDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PU2211A Samples TPS2211APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS2211A Samples TPS2211APWP ACTIVE HTSSOP PWP 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS2211A Samples TPS2211APWPR ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS2211A Samples TPS2211APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS2211A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of