SLVS179D − MARCH 1999 − REVISED JUNE 2000
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Fully Integrated xVCC and xVPP Switching
xVPP Programmed Independent of xVCC
3.3-V, 5-V, and/or 12-V Power Distribution
Low rDS(on) (60-mΩ xVCC Switch Typical)
Short Circuit and Thermal Protection
150-µA (Maximum) Quiescent Current
Standby Mode: 50-mA Current Limit (Typ)
12-V Supply Can Be Disabled
3.3-V Low-Voltage Mode
Meets PC Card Standards
TTL-Logic Compatible Inputs
Available in 30-Pin SSOP (DB) and 32-Pin
TSSOP (DAP) Packages
Break-Before-Make Switching
Internal Power-On Reset
DAP PACKAGE†
(TOP VIEW)
5V
5V
NC
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
GND
RESET
NC
3.3V
description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
5V
NC
MODE
NC
NC
NC
NC
12V
BVPP
BVCC
BVCC
BVCC
OC
STBY
3.3V
3.3V
DB PACKAGE†
(TOP VIEW)
The TPS2216 PC Card power-interface switch
provides an integrated power-management
solution for two PC Cards. All of the discrete
power MOSFETs, a logic section, current limiting,
and thermal protection for PC Card control are
combined on a single integrated circuit. This
device allows the distribution of 3.3-V, 5-V, and/
or 12-V power to the card. The current-limiting
feature eliminates the need for fuses. Currentlimit reporting can help the user isolate a system
fault.
The TPS2216 features a 3.3-V low-voltage mode
that allows for 3.3-V switching without the need for
5-V power. This feature facilitates low-power
system designs such as sleep modes where only
3.3 V is available. This device also has the ability
to program the xVPP outputs independent of the
xVCC outputs. A standby mode that changes all
output-current limits to 50 mA (typical) has been
incorporated.
5V
5V
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
GND
NC
RESET
3.3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
MODE
NC
NC
NC
NC
12V
BVPP
BVCC
BVCC
BVCC
STBY
OC
3.3V
3.3V
† The TPS2216 is identical to the TPS2214 in all respects
except packaging and pin assignments.
NC − No internal connection
End-equipment applications for the TPS2216 include: notebook computers, desktop computers, personal
digital assistants (PDAs), digital cameras, and bar-code scanners.
The TPS2216 is backward-compatible with the TPS2202A and TPS2206.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).
Copyright 2000, Texas Instruments Incorporated
!" #!$% & "'
&! #" #" (" " ") !"
& & * +' &! # " , &" " " %+ %!&"
" , %% # " " '
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLVS179D − MARCH 1999 − REVISED JUNE 2000
AVAILABLE OPTIONS
PACKAGED DEVICES†
TJ
PLASTIC SMALL OUTLINE
(DB)
PowerPAD PLASTIC SMALL
OUTLINE
(DAP)
−40°C to 125°C
TPS2216DB(R)
TPS2216DAP(R)
† The DB and DAP packages are available in tubes and left-end taped and reeled. Add R
suffix to device type (e.g., TPS2216DBR) for taped and reeled.
Terminal Functions
TERMINAL
NO.
NAME
I/O
DESCRIPTION
DB
DAP
15, 16, 17
16, 17, 18
I
3.3-V input for card power and/or chip power if 5 V is not present
5V
1, 2, 30
1, 2, 32
I
5-V input for card power and/or chip power
12V
7, 24
8, 25
I
12-V Vpp input card power
9, 10, 11
10, 11, 12
O
VCC output: 3.3-V, 5-V, GND or high impedance to card
3.3V
AVCC
AVPP
8
9
O
VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card
BVCC
20, 21, 22
21, 22, 23
O
VCC output: 3.3-V, 5-V, GND or high impedance to card
BVPP
23
24
O
VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card
GND
12
13
MODE
29
30
I
TPS2206 operation when floating or pulled low; must be pulled high externally for TPS2216
operation. MODE is internally pulled low with a 150-kΩ pulldown resistor.
OC
18
20
O
Logic-level output that goes low when an overcurrent or overtemperature condition exists.
RESET
6
7
I
Logic-level reset input active high. Do not connect if RESET pin is used. RESET is internally
pulled low with a 150-kΩ pulldown resistor.
RESET
14
14
I
Logic-level reset input active low. Do not connect if RESET pin is used. The pin is internally pulled
high with a 150-kΩ pullup resistor.
STBY
19
19
I
Logic-level active low input sets the TPS2216 to standby mode and sets all current limits to
50 mA. The pin is internally pulled high with a 150-kΩ pullup resistor.
CLOCK
4
5
I
Logic-level clock for serial data word
DATA
3
4
I
Logic-level serial data word
5
6
I
Logic-level latch for serial data word
13, 25, 26,
27, 28
3, 15, 26,
27, 28, 29,
31
LATCH
NC
Ground
No internal connection
PowerPAD is a trademark of Texas Instruments Incorporated.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLVS179D − MARCH 1999 − REVISED JUNE 2000
functional block diagram (pin numbers refer to DB package)
9
TPS2216
3.3V
3.3V
3.3V
15
10
S1
11
16
17
AVCC
AVCC
AVCC
S2
CS
S7
S3
8
CS
AVPP
S8
CS
S9
CS
S10
5V
5V
5V
CS
1
2
20
21
S4
22
30
BVCC
BVCC
BVCC
S5
CS
S11
S6
23
CS
BVPP
S12
CS
12V†
12V†
S13
7
CS
S14
24
CS
Internal
Current Monitor
29
Thermal
MODE
19
STBY
3
DATA
4
CLOCK
5
LATCH
6
RESET
14
GND
12
RESET
18
OC
† Both 12V pins must be connected together.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SLVS179D − MARCH 1999 − REVISED JUNE 2000
absolute maximum ratings over operating virtual free-air temperature (unless otherwise noted)†
Input voltage range for card power: VI(3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
VI(5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
VI(12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 14 V
Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Output voltage range: VO(xVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
VO(xVPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 14 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Output current: IO(xVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
IO(xVPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
DERATING FACTOR‡
TA = 70°C
POWER RATING
ABOVE TA = 25°C
PACKAGE
TA ≤ 25°C
POWER RATING
DB
1095 mW
10.99 mW/°C
602 mW
438 mW
DAP
4255 mW
42.55 mW/°C
2340 mW
1702 mW
TA = 85°C
POWER RATING
‡ These devices are mounted on an JEDEC low-k board (2 oz. traces on surface), 1-W power applied.
recommended operating conditions
Input voltage, VI
Output current, IO
MIN
MAX
UNIT
VI(3.3V)
VI(5V)
2.7
5.25
V
2.7
5.25
V
VI(12V)
IO(VCC) at TA = 70°C
2.7
13.5
V
1
A
IO(VPP) at TA = 70°C
Clock frequency
Pulse duration
Data
200
Latch
250
Clock
100
200
mA
2.5
MHz
ns
Data hold time§
100
ns
Data setup time§
Latch delay time§
100
ns
100
ns
Clock delay time§
250
Operating virtual junction temperature, TJ
−40
§ Refer to Figures 2 and 3.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
125
°C
SLVS179D − MARCH 1999 − REVISED JUNE 2000
electrical characteristics, TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, STBY floating, all
outputs unloaded (unless otherwise noted)
power switch
PARAMETER
TEST CONDITIONS
Ilkg
IOS
Leakage current
Short-circuit
output current
limit†
II
Input current§
85
90
120
VI(5V) = 0,
VI(5V) = 0,
TJ = 25°C,
TJ = 125°C,
IO = 1 A
IO = 1 A
60
85
90
120
TJ = 25°C,
TJ = 125°C,
IO = 1 A each
IO = 1 A each
65
105
95
140
TJ = 25°C,
TJ = 125°C,
VI(5V) = 0,
VI(5V) = 0,
70
105
100
140
5 V to xVCC, with two
switches on
TJ = 25°C,
TJ = 125°C,
IO = 1 A each
IO = 1 A each
70
105
100
140
3.3 V/5 V/12 V to xVPP
TJ = 25°C,
TJ = 125°C,
IO = 50 mA
IO = 50 mA
3.3 V/5 V to xVCC
TJ = 25°C,
TJ = 125°C,
STBY = low,
3.3 V/5 V/12 V to xVPP
TJ = 25°C,
TJ = 125°C,
STBY = low,
VO(xVCC)
VO(xVPP)
IO(xVCC) at 10 mA, After reset
IO(xVPP) at 10 mA, After reset
IO(xVCC) High-impedance
state
IO(xVPP) High-impedance
state
3.3 V to xVCC, with two
switches on
IO(xVCC)
IO(xVPP)
Standby mode IO(xVCC)
xVCC switch
II(3.3V)
II(5V)
II(12V)
II(3.3V)
II(5V)
II(12V)
Shutdown mode
STBY = low,
IO = 1 A each
IO = 1 A each
II(3.3V)
II(5V)
65
85
90
130
0.7
1
1.4
2.5
IO = 30 mA
IO = 30 mA
1.4
2
2
3
IO = 30 mA
IO = 30 mA
5
7
10
16
0.275
0.8
0.275
0.8
TJ = 25°C
TJ = 125°C
1
10
2
50
TJ = 25°C
TJ = 125°C
1
10
2
TJ = 85°C,
Output powered into a short to GND,
STBY = 0 V
100-mΩ short circuit
xVPP switch
Normal operation
and in reset
mode
STBY = low,
IO = 1 A
IO = 1 A
TJ = 85°C, output powered into a short to GND
Standby mode IO(xVPP)
Current limit
response time‡
MAX
60
TJ = 25°C,
TJ = 125°C,
5 V to xVCC, with one
switch on
Clamp low
voltage
TYP
IO = 1 A
IO = 1 A
3.3 V to xVCC, with one
switch on
Switch
resistance†
MIN
TJ = 25°C,
TJ = 125°C,
VO(xVCC) = VO(xVPP) = 5 V
VI(5V) = 0,
VO(xVCC) = 3.3 V,
VO(xVPP) = 12 V
mΩ
Ω
V
µA
50
1
2.2
A
250
500
mA
35
50
65
30
50
60
mA
100
µs
16
0.01
2
100
120
6
10
100
120
µA
µA
0
22
30
1
1
VO(xVCC) = Hi-Z, VO(xVPP) = Hi-Z
II(12V)
Thermal
shutdown‡
UNIT
µA
1
Trip point, TJ
155
Hysteresis
10
°C
† Pulse-testing techniques maintain junction temperature close to ambient temperature (250-µs-wide pulse, less than 0.5% duty cycle); thermal
effects must be taken into account separately.
‡ Specified by design, not tested in production.
§ Input currents do not include logic input currents (presented in electrical characteristics for logic section); clock is inactive.
NOTE: VI(3.3V) or VI(5V) must be biased for switches to function.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SLVS179D − MARCH 1999 − REVISED JUNE 2000
logic section (CLOCK, DATA, LATCH, MODE, RESET, RESET, STBY, OC)
PARAMETER
Logic input current
TEST CONDITIONS
MIN
TYP
MAX
50
VI(RESET) = 5 V or VI(RESET) = 0 V
VI(RESET) = 0 V or VI(RESET) = 5 V
30
II(RESET) or II(RESET)†
II(MODE)†
VI(MODE) = 5 V
VI(MODE) = 0 V
30
II(STBY)†
VI(STBY) = 5 V
VI(STBY) = 0 V
1
30
50
1
VI(5V) = 5 V
VI(5V) = 0 V
2
V
2
0.8
VI(5V) = 5 V,
VI(5V) = 0 V,
IO = 1 mA
IO = 1 mA
VI(5V)−0.4
VI(3.3V)−0.4
Logic output low level, OC
IO = 1 mA
† RESET and MODE have internal 150-kΩ pulldown resistors; RESET and STBY have internal 150-kΩ pullup resistors.
6
µA
1
Logic input low level
Logic output high level, OC
50
1
II(CLOCK) or II(DATA) or II(LATCH)
Logic input high level
UNIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
V
0.4
V
SLVS179D − MARCH 1999 − REVISED JUNE 2000
switching characteristics
PARAMETER†
tr
tf
Output rise times‡
Output fall times‡
LOAD CONDITION†
CL(xVCC) = 0.1 µF,
CL(xVPP) = 0.1 µF,
IO(xVCC) = 0§,
IO(xVPP) = 0§
CL(xVCC) = 150 µF,
CL(xVPP) = 10 µF,
IO(xVCC) = 1 A,
IO(xVPP) = 50 mA
CL(xVCC) = 0.1 µF,
CL(xVPP) = 0.1 µF,
IO(xVCC) = 0§,
IO(xVPP) = 0§
CL(xVCC) = 150 µF,
CL(xVPP) = 10 µF,
IO(xVCC) = 1 A,
IO(xVPP) = 50 mA
CL(xVCC) = 0.1 µF,
CL(xVPP) = 0.1 µF,
IO(xVCC) = 0§,
IO(xVPP) = 0§
tpd
Propagation delay‡
CL(xVCC) = 150 µF,
CL(xVPP) = 10 µF,
IO(xVCC) = 1 A,
IO(xVPP) = 50 mA
TEST CONDITIONS†
MIN
TYP
VO(xVCC)
1
VO(xVPP)
0.8
VO(xVCC)
1.2
VO(xVPP)
2.5
VO(xVCC)
0.01
VO(xVPP)
0.01
VO(xVCC)
3
VO(xVPP)
8
MAX
UNIT
ms
ms
Latch↑ to xVPP (12 V)
tpd(on)
tpd(off)
3
tpd(on)
tpd(off)
0.6
Latch↑ to xVPP (5 V)
Latch↑ to xVPP (3.3 V),
VI(5V) = 5 V
tpd(on)
tpd(off)
0.6
Latch↑ to xVPP (3.3 V),
VI(5V) = 0 V
tpd(on)
tpd(off)
1.4
tpd(on)
tpd(off)
0.3
Latch↑ to xVCC (5 V)
Latch↑ to xVCC (3.3 V),
VI(5V) = 5 V
tpd(on)
tpd(off)
0.2
Latch↑ to xVCC (3.3 V),
VI(5V) = 0 V
tpd(on)
tpd(off)
0.4
4.5
Latch↑ to xVPP (12 V)
tpd(on)
tpd(off)
tpd(on)
tpd(off)
3.3
Latch↑ to xVPP (5 V)
Latch↑ to xVPP (3.3 V),
VI(5V) = 5 V
tpd(on)
tpd(off)
3
Latch↑ to xVPP (3.3 V),
VI(5V) = 0 V
tpd(on)
tpd(off)
3
Latch↑ to xVCC (5 V)
tpd(on)
tpd(off)
Latch↑ to xVCC (3.3 V),
VI(5V) = 5 V
tpd(on)
tpd(off)
0.6
Latch↑ to xVCC (3.3 V),
VI(5V) = 0 V
tpd(on)
tpd(off)
1
25
8.5
9
9
15
15
15
ms
13
8
9
9
1
12
12
12
† Refer to Parameter Measurement Information
‡ Specified by design: not tested in production.
§ No card inserted, assumes 0.1-µF recommended output capacitor (see Figure 34).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLVS179D − MARCH 1999 − REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
xVPP
xVCC
IO(xVPP)
IO(xVCC)
LOAD CIRCUITS
LATCH
VDD
50%
LATCH
VDD
50%
GND
tpd(on)
GND
tpd(off)
tpd(on)
90%
VO(xVPP)
VO(xVCC)
Propagation Delay (xVCC)
tf
VO(xVCC)
GND
GND
Rise/Fall Time (xVCC)
VDD
50%
90%
10%
Rise/Fall Time (xVPP)
LATCH
tf
tr
90%
10%
GND
10%
Propagation Delay (xVPP)
VO(xVPP)
90%
GND
10%
tr
tpd(off)
VDD
50%
GND
GND
ton
VO(xVPP)
toff
toff
ton
VO(xVCC)
90%
10%
90%
GND
10%
Turn On/Off Time (xVCC)
Turn On/Off Time (xVPP)
VOLTAGE WAVEFORMS
Figure 1. Test Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
GND
SLVS179D − MARCH 1999 − REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
DATA
D10
D9
D8
D6
D7
Data Setup Time
D5
D4
D3
Data Hold Time
D2
D1
D0
Latch Delay Time
LATCH
Clock Delay Time
CLOCK
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of
the clock. For definition of D0 to D10, see the control logic table.
Figure 2. Serial-Interface Timing for Independent xVPP Switching When MODE = 5 V or 3.3 V
DATA
D8
D7
D6
D5
D4
Data Setup Time
D3
D2
D1
D0
Latch Delay Time
Data Hold Time
LATCH
Clock Delay Time
CLOCK
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of
the clock. For definition of D0 to D8, see the control logic table.
Figure 3. Serial-Interface Timing When MODE = 0 V or Floating
Table of Timing Diagrams†
FIGURE
Short-circuit current response, short applied to powered-on 5-V xVCC switch output
4
Short-circuit current response, short applied to powered-on 12-V xVPP switch output
5
OC response with ramped load on 5-V xVCC switch output
6
OC response with ramped load on 12-V xVPP switch output
7
† Timing tests are conducted at free-air temperature, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, CL = 0.1 µF on each output, STBY floating.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SLVS179D − MARCH 1999 − REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
VO(OC)
5 V/div
VO(OC)
5 V/div
IO(VPP)
5 A/div
IO(VCC)
5 A/div
0
200
400
600
800
0
1000
200
Figure 4. Short-Circuit Response, Short Applied
to Powered-on 5-V xVCC-Switch Output
VO(OC)
5 V/div
IO(VCC)
1 A/div
IO(VPP)
0.2 A/div
20
30
40
50
1000
0
4
8
12
16
20
t − Time − ms
t − Time − ms
Figure 6. OC Response With Ramped Load
on 5-V xVCC-Switch Output
10
800
Figure 5. Short-Circuit Response, Short Applied
to Powered-on 12-V xVPP-Switch Output
VO(OC)
5 V/div
10
600
t − Time − µs
t − Time − µs
0
400
POST OFFICE BOX 655303
Figure 7. OC Response With Ramped Load on
12-V xVPP-Switch Output
• DALLAS, TEXAS 75265
SLVS179D − MARCH 1999 − REVISED JUNE 2000
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
tpd(on)
tpd(off)
Turnon propagation delay time, 3.3-V xVCC switch
vs Load capacitance
Turnoff propagation delay time, 3.3-V xVCC switch
vs Load capacitance
9
tpd(on)
tpd(off)
Turnon propagation delay time, 5-V xVCC switch
vs Load capacitance
10
Turnoff propagation delay time, 5-V xVCC switch
vs Load capacitance
11
tpd(on)
tpd(off)
Turnon propagation delay time, 12-V xVPP switch
vs Load capacitance
12
Turnoff propagation delay time, 12-V xVPP switch
vs Load capacitance
13
tr
tf
Rise time, 3.3-V xVCC switch
vs Load capacitance
14
Fall time, 3.3-V xVCC switch
vs Load capacitance
15
tr
tf
Rise time, 5-V xVCC switch
vs Load capacitance
16
Fall time, 5-V xVCC switch
vs Load capacitance
17
tr
tf
Rise time, 12-V xVPP switch
vs Load capacitance
18
Fall time, 12-V xVPP switch
vs Load capacitance
19
Input current at VO(xVCC) = VO(xVPP) =3.3 V
vs Junction temperature
20
Input current at VO(xVCC) = VO(xVPP) =5 V
vs Junction temperature
21
Input current at VO(xVCC) = 5 V, VO(xVPP) =12 V
Static drain-source on-state resistance, 3.3-V xVCC switch (VI(5V)=0)
vs Junction temperature
22
vs Junction temperature
23
Static drain-source on-state resistance, 3.3-V xVCC switch
vs Junction temperature
24
Static drain-source on-state resistance, 5-V xVCC switch
vs Junction temperature
25
Static drain-source on-state resistance, 12-V xVPP switch
vs Junction temperature
26
DC input-to-output voltage (drop), 3.3-V xVCC switch (VI(5V)=0)
vs Load current
27
DC input-to-output voltage (drop), 3.3-V xVCC switch
vs Load current
28
DC input-to-output voltage (drop), 5-V xVCC switch
vs Load current
29
DC input-to-output voltage (drop), 12-V xVPP switch
vs Load current
30
Short-circuit current limit, 3.3-V xVCC switch
vs Junction temperature
31
Short-circuit current limit, 5-V xVCC switch
vs Junction temperature
32
Short-circuit current limit, 12-V xVPP switch
vs Junction temperature
33
II
rDS(on)
VIO(xVCC)
VIO(xVPP)
IOS
8
NOTE: Electrical characteristics tests are conducted at VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, CL = 0.1 µF on each output, STBY floating
(unless otherwise noted on Figures).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SLVS179D − MARCH 1999 − REVISED JUNE 2000
TYPICAL CHARACTERISTICS
14
TJ = 125°C
t pd(off) − Turn-off Propagation Delay Time − ms
t pd(on) − Turn-on Propagation Delay Time − ms
1.4
TURNON PROPAGATION DELAY TIME,
3.3-V xVCC SWITCH
vs
LOAD CAPACITANCE
1.2
TJ = 85°C
1
TJ = 25°C
0.8
0.6
TJ = 0°C
TJ = −40°C
0.4
dc Load = 1 A
0.2
0.1
1
10
100
TURNOFF PROPAGATION DELAY TIME,
3.3-V xVCC SWITCH
vs
LOAD CAPACITANCE
12
TJ = 125°C
10
TJ = 25°C
dc Load = 1 A
6
1000
0.1
1
t pd(off) − Turn-off Propagation Delay Time − ms
t pd(on) − Turn-on Propagation Delay Time − ms
14
1.4
TJ = 125°C
1.2
TJ = 85°C
TJ = 25°C
TJ = −40°C
TJ = 0°C
0.6
0.4
dc Load = 1 A
0.2
0.1
1
10
1000
100
1000
TURNOFF PROPAGATION DELAY TIME,
5-V xVCC SWITCH
vs
LOAD CAPACITANCE
12
TJ = 125°C
TJ = 25°C
TJ = 85°C
10
dc Load = 1 A
6
0.1
1
10
100
CL − Load Capacitance − µF
Figure 10
Figure 11
POST OFFICE BOX 655303
TJ = −40°C
TJ = 0°C
8
CL − Load Capacitance − µF
12
100
Figure 9
TURNON PROPAGATION DELAY TIME,
5-V xVCC SWITCH
vs
LOAD CAPACITANCE
0.8
10
CL − Load Capacitance − µF
Figure 8
1
TJ = −40°C
8
CL − Load Capacitance − µF
1.6
TJ = 0°C
TJ = 85°C
• DALLAS, TEXAS 75265
1000
SLVS179D − MARCH 1999 − REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TURNON PROPAGATION DELAY TIME,
12-V xVPP SWITCH
vs
LOAD CAPACITANCE
TURNOFF PROPAGATION DELAY TIME dc,
12-V xVPP SWITCH
vs
LOAD CAPACITANCE
16
5
t pd(off) − Turn-off Propagation Delay Time − ms
t pd(on) − Turn-on Propagation Delay Time − ms
6
TJ = 125°C
TJ = 85°C
4
3
TJ = 0°C
TJ = 25°C
TJ = −40°C
2
1
dc Load = 50 mA
0
0.1
1
10
100
CL − Load Capacitance − µF
1000
14
TJ = 0°C
TJ = −40°C
12
TJ = 25°C
10
TJ = 85°C
TJ = 125°C
8
dc Load = 50 mA
6
0.1
1
10
100
CL − Load Capacitance − µF
Figure 12
1000
Figure 13
FALL TIME, 3.3-V xVCC SWITCH
vs
LOAD CAPACITANCE
RISE TIME, 3.3-V xVCC SWITCH
vs
LOAD CAPACITANCE
2
3.5
TJ = 125°C
1.8
3
1.6
TJ = 85°C
TJ = 25°C
2.5
t f − Fall Time − ms
t r − Rise Time − ms
1.4
1.2
1
TJ = 0°C
0.8
TJ = −40°C
0.6
TJ = 125°C
TJ = 85°C
TJ = 0°C
2
TJ = 25°C
1.5
TJ = −40°C
1
0.4
0.5
0.2
dc Load = 1 A
dc Load = 1 A
0
0
0.1
1
10
100
1000
0.1
CL − Load Capacitance − µF
1
10
100
1000
CL − Load Capacitance − µF
Figure 14
Figure 15
POST OFFICE BOX 655303
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13
SLVS179D − MARCH 1999 − REVISED JUNE 2000
TYPICAL CHARACTERISTICS
FALL TIME, 5-V xVCC SWITCH
vs
LOAD CAPACITANCE
RISE TIME, 5-V xVCC SWITCH
vs
LOAD CAPACITANCE
1.8
4
1.6
3.5
TJ = 85°C
TJ = 125°C
3
1.2
t f − Fall Time − ms
t r − Rise Time − ms
1.4
1
0.8
TJ = 25°C
TJ = 0°C
TJ = −40°C
0.6
TJ = 125°C
2.5
TJ = 0°C
TJ = 85°C
2
TJ = −40°C
TJ = 25°C
1.5
1
0.4
0.5
0.2
dc Load = 1 A
dc Load = 1 A
0
0
0.1
1
10
100
1000
0.1
CL − Load Capacitance − µF
1
10
100
1000
CL − Load Capacitance − µF
Figure 16
Figure 17
FALL TIME, 12-V xVPP SWITCH
vs
LOAD CAPACITANCE
RISE TIME, 12-V xVPP SWITCH
vs
LOAD CAPACITANCE
5
20
4.5
18
4
16
3.5
14
TJ = 125°C
TJ = 85°C
3
2.5
2
TJ = −40°C
TJ = 125°C
TJ = 85°C
1.5
TJ = 0°C
1
t f − Fall Time − ms
t r − Rise Time − ms
TJ = 25°C
12
TJ = 0°C
10
TJ = −40°C
8
6
4
TJ = 25°C
.5
2
dc Load = 50 mA
dc Load = 50 mA
0
0
0.1
1
10
100
1000
0.1
CL − Load Capacitance − µF
Figure 18
14
1
10
Figure 19
POST OFFICE BOX 655303
100
CL − Load Capacitance − µF
• DALLAS, TEXAS 75265
1000
SLVS179D − MARCH 1999 − REVISED JUNE 2000
TYPICAL CHARACTERISTICS
INPUT CURRENT AT VI(xVCC) = VI(xVPP) = 3.3 V
vs
JUNCTION TEMPERATURE
INPUT CURRENT AT VI(xVCC) = VI(xVPP) = 5 V
vs
JUNCTION TEMPERATURE
100
120
II(5V)
90
II(5V)
110
100
90
70
I I − Input Current − µ A
I I − Input Current − µ A
80
60
50
40
30
70
60
50
40
30
20
II(3.3V)
20
80
II(12V)
10
10
0
−10
II(12V)
0
−50
0
50
100
150
−50
TJ − Junction Temperature − °C
Figure 20
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
3.3-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
II(5V)
100
90
I I − Input Current − µ A
80
70
60
50
40
II(12V)
20
10
II(3.3V)
0
−10
−50
0
50
100
TJ − Junction Temperature − °C
150
rDS(on) − Static Drain-Source On-State Resistance −Ω
120
30
150
Figure 21
INPUT CURRENT AT VI(xVCC) = 5 V, VI(xVPP) = 12 V
vs
JUNCTION TEMPERATURE
110
II(3.3V)
0
50
100
TJ − Junction Temperature − °C
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
dc Load = 1 A
VI(5V) = 0
0.01
0
−50
0
50
100
TJ − Junction Temperature − °C
150
Figure 23
Figure 22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SLVS179D − MARCH 1999 − REVISED JUNE 2000
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
3.3-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
dc Load = 1 A
0.01
0
−50
0
50
100
TJ − Junction Temperature − °C
150
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
5-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
r
− Static Drain-Source On-State Resistance −Ω
DS(on)
rDS(on) − Static Drain-Source On-State Resistance −Ω
TYPICAL CHARACTERISTICS
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
dc Load = 1 A
0
0
50
100
TJ − Junction Temperature − °C
0
Figure 25
DC INPUT-TO-OUTPUT VOLTAGE (DROP),
3.3-V xVCC SWITCH
vs
LOAD CURRENT
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
12-V xVPP SWITCH
vs
JUNCTION TEMPERATURE
0.1
1
V IO − dc Input-to-Output Voltage (Drop) − V
rDS(on) − Static Drain-Source On-State Resistance −Ω
Figure 24
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
dc Load = 50 mA
VI(5V) = 0 V
125°C
0.09
85°C
0.08
25°C
0.07
0°C
0.06
−40°C
0.05
0.04
0.03
0.02
0.01
0
0
−50
0
50
100
TJ − Junction Temperature − °C
150
0
0.2
0.4
0.6
IL − Load Current − A
Figure 27
Figure 26
16
150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.8
1
SLVS179D − MARCH 1999 − REVISED JUNE 2000
TYPICAL CHARACTERISTICS
DC INPUT-TO-OUTPUT VOLTAGE (DROP),
3.3-V xVCC SWITCH
vs
LOAD CURRENT
DC INPUT-TO-OUTPUT VOLTAGE (DROP),
5-V xVCC SWITCH
vs
LOAD CURRENT
0.1
125°C
0.09
dc Input-to-Output Voltage (Drop) − V
dc Input-to-Output Voltage (Drop) − V
0.1
85°C
0.08
25°C
0.07
0°C
0.06
−40°C
0.05
0.04
0.03
0.02
125°C
0.09
85°C
0.08
25°C
0.07
0°C
0.06
−40°C
0.05
0.04
0.03
0.02
0.01
0.01
0
0
0
0.2
0.4
0.6
IL − Load Current − A
0.8
0
1
0.2
Figure 28
1.9
125°C
I OS − Short-Circuit Current Limit − A
dc Input-to-Output Voltage (Drop) − V
0.06
85°C
25°C
0.04
0°C
−40°C
0.03
0.02
0.01
0
0
0.01
0.02
0.03
IL − Load Current − A
0.8
1
Figure 29
DC INPUT-TO-OUTPUT VOLTAGE (DROP),
12-V xVPP SWITCH
vs
LOAD CURRENT
0.05
0.4
0.6
IL − Load Current − A
0.04
0.05
SHORT-CIRCUIT CURRENT LIMIT,
3.3-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
1.85
1.8
1.75
1.7
1.65
1.6
−50
Figure 30
0
50
100
TJ − Junction Temperature − °C
150
Figure 31
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SLVS179D − MARCH 1999 − REVISED JUNE 2000
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT CURRENT LIMIT, 5-V xVCC
SWITCH
vs
JUNCTION TEMPERATURE
SHORT-CIRCUIT CURRENT LIMIT, 12-V xVPP
SWITCH
vs
JUNCTION TEMPERATURE
0.4
I OS − Short-Circuit Current Limit − A
I OS − Short-Circuit Current Limit − A
1.9
1.85
1.8
1.75
1.7
1.65
1.6
−50
0
50
100
TJ − Junction Temperature − °C
150
0.38
0.36
0.34
0.32
0.3
−50
Figure 32
0
50
100
TJ − Junction Temperature − °C
150
Figure 33
APPLICATION INFORMATION
overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with
limited onboard memory. The idea of add-in cards quickly took hold; modems, wireless LANs, Global Positioning
Satellite System (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card
applications grew, the engineering community quickly recognized the need for a standard to ensure
compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International
Association), comprising members from leading computer, software, PC Card, and semiconductor
manufacturers, was established. One key goal was to realize the plug-and-play concept. Cards and hosts from
different vendors should be compatible or able to communicate with one another transparently.
PC Card power specification
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of the 68 terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four
ground terminals. Multiple VCC and ground terminals minimize connector terminal and line resistance. The two
Vpp terminals were originally specified as separate signals, but are commonly tied together in the host to form
a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals;
flash-memory programming and erase voltage is supplied through the Vpp terminals.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLVS179D − MARCH 1999 − REVISED JUNE 2000
APPLICATION INFORMATION
designing for voltage regulation
The current PCMCIA specification for output voltage regulation, VO(reg), of the 5-V output is 5% (250 mV). In
a typical PC power-system design, the power supply has an output-voltage regulation, VPS(reg), of 2% (100 mV).
Also, a voltage drop from the power supply to the PC Card will result from resistive losses, VPCB, in the PCB
traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than
1% (50 mV) of the output voltage. Therefore, the allowable voltage drop, VDS, for the TPS2216 would be the
PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops:
V
DS
+V
O(reg)
–V
PS(reg)
–V
PCB
Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification for
output voltage regulation of the 3.3-V output is 300 mV; so, using the same equation by deducting the voltage
drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltage drop for
the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance of the
TPS2216. Therefore, the maximum output current, IO max, that can be delivered to the PC Card in regulation
is the allowable voltage drop across the IC, divided by the output-switch resistance.
V
I max + r DS
O
DS(on)
The xVCC outputs can deliver 1 A continuously at 5 V and 3.3 V within regulation over the operating temperature
range. The xVPP outputs of the IC can deliver 200 mA continuously.
overcurrent and overtemperature protection
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that could lead to power-supply or PCB trace damage. Even systems robust
enough to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,
resulting in the rather sudden and unacceptable loss of system power. Most hosts include fuses for protection.
However, the reliability of fused systems is poor, as blown fuses require troubleshooting and repair, usually by
the manufacturer.
The TPS2216 takes a two-pronged approach to overcurrent protection, which is designed to activate if an output
is shorted or when an overcurrent condition is present when switches are powered up. First, instead of fuses,
sense FETs monitor each of the xVCC and xVPP power outputs. Unlike sense resistors or polyfuses, these FETs
do not add to the series resistance of the switch; therefore voltage and power losses are reduced. Overcurrent
sensing is applied to each output separately. Excessive current generates an error signal that limits the output
current of only the affected output, preventing damage to the host. Each xVCC output overcurrent limits from
1 A to 2.2 A, typically around 1.6 A; the xVPP outputs limit from 250 mA to 500 mA, typically around 375 mA.
Second, when an overcurrent condition is detected, the TPS2216 asserts an active low OC signal that can be
monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message.
In the event that an overcurrent condition persists, causing the IC to exceed its maximum junction temperature,
thermal-protection circuitry activates. This shuts down all power outputs until the device cools to within a safe
operating region, which is ensured by a thermal shutdown hysteresis.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLVS179D − MARCH 1999 − REVISED JUNE 2000
APPLICATION INFORMATION
12-V supply not required
Many PC Card switches use the externally supplied 12 V to power gate drive and other chip functions; this
requires that power be present at all times. The TPS2216 offers considerable power savings by using an internal
charge pump to generate the required higher gate drive voltages from the 5-V or 3.3-V power supplies.
Therefore, the external 12-V supply can be disabled except when needed for flash-memory functions, thereby
extending battery lifetime. Additional power savings are realized by the IC during shutdown mode, in which
quiescent current drops to a maximum of 1 µA.
3.3-V low-voltage mode
The TPS2216 will operate in 3.3-V low-voltage mode when 3.3 V is the only available input voltage (VI(5V) = 0,
VI(12V) = 0). This feature allows host and PC Cards to be operated in low-power 3.3-V-only modes such as sleep
modes. Note that in this operation mode, the IC will derive its bias current from the 3.3-V input pin and can only
provide 3.3 V to the outputs.
voltage transitioning requirement
PC Cards are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase
logic speeds. The TPS2216 meets all combinations of power delivery as currently defined in the PCMCIA
standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V, then
polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on
3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that
sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. PC Card
specification requires that VCC be discharged within 100 ms. PC Card resistance can not be relied on to provide
a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by
power-management schemes. The TPS2216 includes discharge transistors on all xVCC and xVPP outputs to
meet the specification requirement.
shutdown mode
In the shutdown mode, which can be controlled by bit D8 of the input serial DATA word, each of the xVCC and
xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is limited to 1 µA
or less to conserve battery power.
standby mode
The TPS2216 can be put in standby mode by pulling STBY low to conserve power during low-power operation.
In this mode, all of the power outputs (xVCC and xVPP) will have a nominal current limit of 50 mA. STBY has
an internal 150-kΩ pullup resistor. The output-switch status of the device must be set, allowing the output
capacitors to charge, prior to enabling the standby mode. Changing the setting of the output switches with the
device in standby mode may cause an overcurrent response to be generated.
mode
The mode pin programs the switches in either TPS2216 or TPS2206 mode. An internal 150-kΩ pulldown
resistor is connected to the pin. Floating or pulling the mode pin low sets the switches in TPS2206 mode; pulling
the mode pin high sets the switches in TPS2216 mode. In TPS2206 mode, xVPP outputs are dependent on
xVCC outputs. In TPS2216 mode, xVPP is programmed independent of xVCC. Refer to TPS2216 control-logic
tables for more information.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLVS179D − MARCH 1999 − REVISED JUNE 2000
APPLICATION INFORMATION
power supply considerations
The TPS2216 has multiple pins for each of its 3.3-V and 5-V power inputs and for the switched xVCC outputs.
Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the
series resistance is higher than that specified, resulting in increased voltage drops and less power. It is
recommended that all input and output power pins be paralleled for optimum operation. Because the two 12-V
pins are not internally connected, they must be tied together externally.
To increase the noise immunity of the TPS2216, the power-supply inputs should be bypassed with a 1-µF
electrolytic or tantalum capacitor paralleled by a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly
recommended that the switched outputs be bypassed with a 0.1-µF (or larger) ceramic capacitor; doing so
improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the
inductance of PCB traces between the IC and the load. High switching currents can produce large negative
voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no
pin should be taken, or allowed to fall, below −0.3 V.
RESET and RESET inputs
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should
be reset at the same time as the host by applying low impedance paths from xVCC and xVPP terminals to
ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter
capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active-high RESET
or active low RESET input will close internal switches S1, S4, S7, and S11 with all other switches left open. The
TPS2216 remains in the low-impedance output state until the signal is deasserted and further data is clocked
in and latched. The input serial data can not be latched during reset mode. RESET and RESET are provided
for direct compatibility with systems that use either an active-low or active-high reset voltage supervisor. The
RESET pin has an internal 150-kΩ pulldown resistor and the RESET pin has an internal 150-kΩ pullup resistor.
The device will be reset automatically when powered up.
calculating junction temperature
The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature
is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures 23
through 26, using an initial temperature estimate about 50°C above ambient. Then calculate the power
dissipation for each switch, using the formula:
P
D
+r
DS(on)
I2
Next, sum the power dissipation of all switches and calculate the junction temperature:
ǒȍ
Ǔ
T +
P
R
)T
J
D
qJA
A
Where:
RθJA is the inverse of the derating factor given in the dissipation rating table.
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not
within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
logic inputs and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge
of the clock (see Figures 2 and 3). The 11-bit (D0−D10) serial data word is loaded during the positive edge of
the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock
occurs.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SLVS179D − MARCH 1999 − REVISED JUNE 2000
APPLICATION INFORMATION
logic inputs and outputs (continued)
The TPS2216 serial interfaces are compatible with serial-interface PCMCIA controllers and current PCMCIA
and Japan Electronic Industry Development Association (JEIDA) standards.
An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the
xVCC and xVPP outputs as previously discussed.
TPS2216 control logic
TPS2216 mode (MODE pulled high)
xVPP
AVPP CONTROL SIGNALS
BVPP CONTROL SIGNALS
OUTPUT
V_AVPP
D8 (SHDN)
D4
D5
D10
X
0V
1
0
0
X
0V
0
3.3 V
1
0
1
0
3.3 V
1
1
5V
1
0
1
1
5V
1
0
X
12 V
1
1
0
X
12 V
1
1
X
Hi-Z
1
1
1
X
Hi-Z
X
X
X
Hi-Z
0
X
X
X
Hi-Z
D8 (SHDN)
D0
D1
D9
1
0
0
1
0
1
1
0
1
1
0
OUTPUT
V_BVPP
xVCC
AVCC CONTROL SIGNALS
BVCC CONTROL SIGNALS
D8 (SHDN)
D3
D2
OUTPUT
V_AVCC
D8 (SHDN)
D6
D7
OUTPUT
V_BVCC
1
0
0
0V
1
0
0
0V
1
0
1
3.3 V
1
0
1
3.3 V
1
1
0
5V
1
1
0
5V
1
1
1
0V
1
1
1
0V
0
X
X
Hi-Z
0
X
X
Hi-Z
OUTPUT
V_BVPP
TPS2206 mode (MODE floating or pulled low)
xVPP
AVPP CONTROL SIGNALS
BVPP CONTROL SIGNALS
OUTPUT
V_AVPP
D8 (SHDN)
D4
D5
D8 (SHDN)
D0
D1
1
0
0
0V
1
0
0
0V
1
0
1
V_AVCC
1
0
1
V_BVCC
1
1
0
12 V
1
1
0
12 V
1
1
1
Hi-Z
1
1
1
Hi-Z
0
X
X
Hi-Z
0
X
X
Hi-Z
OUTPUT
V_BVCC
xVCC
AVCC CONTROL SIGNALS
22
BVCC CONTROL SIGNALS
OUTPUT
V_AVCC
D8 (SHDN)
D6
D7
D8 (SHDN)
D3
D2
1
0
0
0V
1
0
0
0V
1
0
1
3.3 V
1
0
1
3.3 V
1
1
0
5V
1
1
0
5V
1
1
1
0V
1
1
1
0V
0
X
X
Hi-Z
0
X
X
Hi-Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLVS179D − MARCH 1999 − REVISED JUNE 2000
APPLICATION INFORMATION
ESD protections (see Figure 34)
All TPS2216 inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can
be exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.
TPS2216
AVCC
AVCC
0.1 µF†
12V
10 µF
12V
0.1 µF
5V
33 µF
0.1 µF
0.1 µF†
BVCC
12V
BVCC
5V
BVCC
5V
BVPP
0.1 µF†
33 µF
0.1 µF
Vpp1
Vpp2
VCC
VCC
PC Card
Connector B
0.1 µF†
5V
3.3V
VCC
PC Card
Connector A
AVCC
AVPP
VCC
Vpp1
Vpp2
3.3V
3.3V
3.3V
Controller
DATA
DATA
CLOCK
CLOCK
LATCH
LATCH
MODE
RESET
STBY
RESET
OC
From PCI or
System RST
GPI/O
† Maximum recommended output capacitance for xVCC is 220 µF and for xVPP is 10 µF without OC glitch when switches are powered on.
Figure 34. Detailed Interconnections and Capacitor Recommendations
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SLVS179D − MARCH 1999 − REVISED JUNE 2000
APPLICATION INFORMATION
12-V flash memory supply
The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V.
The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower
supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 35, the only
external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter
capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of PCB
space when implemented with surface-mount components. An enable input is provided to shut the converter
down and reduce the supply current to 3 µA when 12 V is not needed.
The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET
power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area
needed to realize the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is
accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use.
For additional information, see the TPS6734 data sheet (SLVS127).
TPS2216
AVCC
3.3V or 5V
ENABLE
(see Note A)
R1
10 kΩ
1
2
C1
33 µF
20V
+
3
4
C2
0.01 µF
AVCC
TPS6734
EN
VCC
REF
FB
SS
OUT
COMP
GND
8
L1
18 µH
AVCC
7
AVPP
D1
6
5
33 µF, 20 V
+
C1
12 V
0.1 µF
12V
12V
BVCC
BVCC
C4
0.001 µF
5V
33 µF
0.1 µF
5V
5V
BVCC
BVPP
5V
3.3 V
33 µF
0.1 µF
3.3V
3.3V
3.3V
DATA
CLOCK
LATCH
MODE
RESET
STBY
RESET
OC
NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high.
Figure 35. TPS2216 with TPS6734 12-V, 120-mA Supply
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS2216DAP
ACTIVE
HTSSOP
DAP
32
46
RoHS & Green
NIPDAU
Level-3-260C-168 HR
TPS2216DB
ACTIVE
SSOP
DB
30
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
TPS2216
-40 to 85
TPS2216
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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