TPS2220BDB

TPS2220B www.ti.com SLVS554 – JANUARY 2005 POWER-INTERFACE SWITCHES FOR SERIAL PCMCIA CONTROLLERS FEATURES • • • • • • • • • • • Single-Slot Switch: TPS2220B Fast Current Limit Response Time Fully Integrated VCC and VPP Switching for 3.3 V, 5 V, and 12 V Meets Current PC Card™ Standards Vpp Output Selection Independent of VCC 12-V and 5-V Supplies Can Be Disabled TTL-Logic Compatible Inputs Short-Circuit and Thermal Protection 24-Pin HTSSOP and 24-Pin SSOP 140-µA (Typical) Quiescent Current from 3.3-V Input Break-Before-Make Switching • • Power-On Reset -40°C to 85°C Operating Ambient Temperature Range APPLICATIONS • • • • • Notebook and Desktop Computers Bar Code Scanners Digital Cameras Set-Top Boxes PDAs DESCRIPTION The TPS2220B power-interface switch provides an integrated power-management solution for single Card sockets. The device allows the controlled distribution of 3.3 V, 5 V, and 12 V to one card slot. The current-limiting and thermal-protection features eliminate the need for fuses. Current-limit reporting helps the user isolate a system fault. The switch rDS(on) and current-limit values have been set for the peak and average current requirements stated in the PC Card specification, and optimized for cost. Like the TPS2220A this device supports independent VPP/VCC switching. The TPS2220B is pin compatible with the TPA2220A execept for pin 20 of the TPS2220B which has no connection. AVAILABLE OPTIONS PACKAGED DEVICE (1) TA PLASTIC SMALL OUTLINE (DB-24) (1) PowerPAD™ PLASTIC SMALL OUTLINE (PWP-24) (1) -40°C to 85°C TPS2220BDB TPS2220BPWP The DB and PWP packages are also available taped and reeled. Add R suffix to device type (e.g., TPS2220BPWPR) for taped and reeled. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association). PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TPS2220B www.ti.com SLVS554 – JANUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA SSOP(DB) (1) STATUS HTSSOP (PWP) (1) STATUS –40°C to 85°C TPS2220BDB Active TPS2220BPWP Active For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TPA2220B VI Input voltage range for card power VI(3.3V) –0.3 V to 5.5 V VI(5V) –0.3 V to 5.5 V VI(12V) –0.3 V to 14 V Logic input/output voltage VO Output voltage –0.3 V to 6 V VO(AVCC) –0.3 V to 6 V VO(AVPP) –0.3 V to 14 V Continuous total power dissipation See Dissipation Rating Table IO(AVCC) Internally Limited IO(AVPP) Internally Limited IO Output current TJ Operating virtual junction temperature range –40°C to 100°C Tstg Storage temperature range –55°C to 150°C (1) Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) 260°C OC sink current 10 mA Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE (1) TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DB 24 890 mW 8.9 mW/°C 489 mW 356 mW PWP 24 3322 mW 33.22 mW/°C 1827 mW 1329 mW (1) 2 These devices are mounted on aa JEDEC low-k board (2-oz. traces on surface). TPS2220B www.ti.com SLVS554 – JANUARY 2005 RECOMMENDED OPERATING CONDITIONS Input voltage, VI(3.3V) is required for all circuit operations. 5V and 12V are only required for their respective functions. IO Output current f(clock) Clock frequency tw Pulse duration VI(3.3V) (1) MIN MAX 3 3.6 VI(5V) 3 5.5 VI(12V) 7 13.5 UNIT V IO(AVCC) at TJ = 100°C 1 IO(AVPP) at TJ = 100°C 100 mA 2.5 MHz Data 200 Latch 250 Clock 100 Reset 100 A ns th Data-to-clock hold time (see Figure 2) 100 ns tsu Data-to-clock setup time (see Figure 2) 100 ns td(latch) Latch delay time (see Figure 2) 100 ns td(clock) Clock delay time (see Figure 2) 250 TJ –40 (1) Operating virtual junction temperature (maximum to be calculated at worst case PD at 85°C ambient) ns 100 °C It is understood that for VI(3.3V) < 3 V, voltages within the absolute maximum ratings applied to pin 5V or pin 12V do not damage the IC. ELECTRICAL CHARACTERISTICS TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT POWER SWITCH IO = 750 mA each 3.3V to AVCC Static drain-source on-state resistance 3.3V or 5V to AVPP 12V to AVPP Output discharge resistance IOS TJ 140 95 130 IO = 500 mA each, TJ = 100°C 120 160 IO = 50 mA each 0.8 1 IO = 50 mA each, TJ = 100°C 1 1.3 IO = 50 mA each 2 2.5 2.5 3.4 IO = 50 mA each, TJ = 100°C Discharge at AVCC IO(disc) = 1 mA 0.5 0.7 1 Discharge at AVPP IO(disc) = 1 mA 0.2 0.4 0.5 Short-circuit output current Thermal shutdown temperature 110 IO = 500 mA each 5V to AVCC rDS(on) 85 110 IO = 750 mA each, TJ = 100°C Thermal trip point Limit (steady-state value), output powered into a short circuit IOS(AVCC) 1 1.4 2 IOS(AVPP) 120 200 300 Limit (steady-state value), output powered into a short circuit, TJ = 100°C IOS(AVCC) 1 1.4 2 IOS(AVPP) 120 200 300 Rising temperature Hysteresis 5V to AVCC = 5 V, with 100-mΩ short to GND 10 5V to AVPP = 5 V, with 100-mΩ short to GND 3 II(3.3V) II Input current, quiescent Shutdown mode II(5V) 12 100 180 II(3.3V) 0.3 2 0.1 2 0.3 2 (2) (3) VO(AVCC) = VO(AVPP) = Hi-Z A mA A mA 200 II(12V) II(5V) kΩ µs 8 II(12V) (1) 140 VO(AVCC) = VO(AVPP) = 3.3 V and also for RESET = 0 V Ω °C 10 Current-limit response time (2) (3) Normal operation 135 mΩ µA Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Specified by design; not tested in production. From application of short to 110% of final current limit. 3 TPS2220B www.ti.com SLVS554 – JANUARY 2005 ELECTRICAL CHARACTERISTICS (continued) TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VO(AVCC) = 5 V, VI(5V) = VI(12V) = 0 V Leakage current, output off state Ilkg Shutdown mode VO(AVPP) = 12 V, VI(5V) = VI(12V) = 0 V MIN TYP MAX UNIT 10 TJ = 100°C 50 10 TJ = 100°C µA 50 LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC) (4) II(/RESET) II Input current, logic RESET = 0 V II(/SHDN) (4) II(LATCH) (4) II(CLOCK, RESET = 5.5 V DATA) SHDN = 5.5 V SHDN = 0 V –1 –30 1 –20 –10 –1 1 –50 -3 LATCH = 5.5 V LATCH = 0 V –1 1 0 V to 5.5 V –1 1 VIH High-level input voltage, logic VIL Low-level input voltage, logic VO(sat) Output saturation voltage at OC IO = 2 mA Ilkg Leakage current at OC VO(/OC) = 5.5 V µA 50 2 V 0.8 V 0.14 0.4 V 0 1 µA 2.7 2.9 UVLO AND POR (POWER-ON RESET) VI(3.3V) Input voltage at 3.3V pin, UVLO Vhys(3.3V) UVLO hysteresis voltage at VA (5) VI(5V) Input voltage at 5V pin, UVLO 5-V level below which only 5V switches are Hi-Z Vhys(5V) UVLO hysteresis voltage at 5V (5) Delay from voltage hit (step from 3 V to 2.3 V) to Hi-Z control (90% VG to GND) tdf Delay time for falling response, VI(POR) (4) (5) 4 Input voltage, power-on reset (5) 3.3-V level below which all switches are Hi-Z 2.4 100 UVLO (5) 3.3-V voltage below which POR is asserted causing a RESET internally with all line switches open and all discharge switches closed. LATCH has low-current pulldown. RESET and SHDN have low-current pullup. Specified by design; not tested in production. 2.3 2.5 V mV 2.8 V 100 mV 4 µs 1.7 V TPS2220B www.ti.com SLVS554 – JANUARY 2005 SWITCHING CHARACTERISTICS VCC = 5 V, TA = 25°C, VI(3.3V) = 3.3 V, VI(5V) = 5 V, VI(12) = 12 V, all outputs unloaded (unless otherwise noted) PARAMETER (1) tr tf Output rise LOAD CONDITION times (3) Output fall times (3) TEST CONDITIONS (2) CL(AVCC) = 0.1 µF, CL(AVPP) = 0.1 µF, IO(AVCC) = 0 A, IO(AVPP) = 0 A VO(AVPP) = 12 V 0.26 CL(AVCC) = 150 µF, CL(AVPP) = 10 µF, IO(AVCC) = 0.75 A, IO(AVPP) = 50 mA VO(AVCC) = 5 V 1.1 VO(AVPP) = 12 V 0.6 VO(AVCC) = 5 V, Discharge switches ON 0.5 VO(AVPP) = 12 V, Discharge switches ON 0.2 CL(AVCC) = 0.1 µF, CL(AVPP) = 0.1 µF, IO(AVCC) = 0 A, IO(AVPP) = 0 A VO(AVCC) = 5 V Latch↑ to AVPP (5V) CL(AVCC) = 0.1 µF, CL(AVPP) = 0.1 µF, IO(AVCC) = 0 A, IO(AVPP) = 0 A Latch↑ to AVPP (3.3V) Latch↑ to AVCC (5V) Latch↑ to AVCC (3.3V) Propagation delay times (3) Latch↑ to AVPP (12V) Latch↑ to AVPP (5V) CL(AVCC) = 150 µF, CL(AVPP) = 10 µF, IO(AVCC) = 0.75 A, IO(AVPP) = 50 mA Latch↑ to AVPP (3.3V) Latch↑ to AVCC (5V) Latch↑ to AVCC (3.3V) UNIT ms ms 2.35 VO(AVPP) = 12 V Latch↑ to AVPP (12V) (1) (2) (3) TYP MAX 0.9 CL(AVCC) = 150 µF, CL(AVPP) = 10 µF, IO(AVCC) = 0.75 A, IO(AVPP) = 50 mA tpd MIN VO(AVCC) = 5 V 3.9 tpdon 2 tpdoff 0.62 tpdon 0.77 tpdoff 0.51 tpdon 0.75 tpdoff 0.52 tpdon 0.3 tpdoff 2.5 tpdon 0.3 tpdoff 2.8 tpdon 2.2 tpdoff 0.8 tpdon 0.8 tpdoff 0.6 tpdon 0.8 tpdoff 0.6 tpdon 0.6 tpdoff 2.5 tpdon 0.5 tpdoff 2.6 ms ms Refer to Parameter Measurement Information in Figure 1. No card inserted, assumes a 0.1-µF output capacitor (see Figure 1). Specified by design; not tested in production. 5 TPS2220B www.ti.com SLVS554 – JANUARY 2005 FUNCTIONAL BLOCK DIAGRAM See Note A S2 3.3 V CS AVCC S1 AVCC S3 5V S4 See Note A CS AVPP S5 S7 5V 12 V S6 Control Logic Current Limit SHDN RESET Thermal Limit DATA CLOCK LATCH GND UVLO OC POR NOTES: A. Current sense PIN ASSIGNMENTS TPS2220B DB OR PWP PACKAGE (TOP VIEW) 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC GND RESET 1 2 3 4 5 6 7 8 9 10 11 12 NC − No internal connection 6 24 23 22 21 20 19 18 17 16 15 14 13 NC NC NC SHDN NC NC NC NC NC OC NC 3.3V TPS2220B www.ti.com SLVS554 – JANUARY 2005 PIN ASSIGNMENTS (continued) Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION TPS2220B 3.3V 13 I 3.3-V input for card power and chip power 5V 1, 2 I 5-V input for card power 12V 7 I 12-V input for card power (AVPP). 9, 10 O Switched output that delivers 3.3 V, 5 V, ground or high impedance to card AVPP 8 O Switched output that delivers 3.3 V, 5 V, 12 V, ground or high impedance to card GND 11 OC 15 O Open-drain overcurrent reporting output that goes low when an overcurrent condition exists. An external pullup is required. SHDN 21 I Hi-Z (open) all switches. Identical function to serial D8. Asynchronous active-low command, internal pullup RESET 12 I Logic-level RESET input active low. Asynchronous active-low command, internal pullup CLOCK 4 I Logic-level clock for serial data word DATA 3 I Logic-level serial data word LATCH 5 I Logic-level latch for serial data word, internal pulldown AVCC NC 6, 14, 16, 17, 18, 19, 20, 22, 23, 24 Ground No internal connection 7 TPS2220B www.ti.com SLVS554 – JANUARY 2005 PARAMETER MEASUREMENT INFORMATION AVPP AVCC IO(AVPP) IO(AVCC) LOAD CIRCUIT (AVPP) LOAD CIRCUIT (AVCC) VDD LATCH VDD LATCH 50% 50% GND GND tpd(off) tpd(on) VI(12V/5V/3.3V) VI(5V/3.3V) 90% VO(AVPP) VO(AVCC) Propagation Delay (AVCC) tf tf tr VI(12V/5V/3.3V) VI(5V/3.3V) VO(AVCC) 90% GND 10% GND 10% Propagation Delay (AVPP) VO(AVPP) 90% GND 10% tr tpd(off) tpd(on) 90% GND 10% Rise/Fall Time (AVCC) Rise/Fall Time (AVPP) VDD LATCH VDD 50% 50% LATCH GND GND toff ton VI(5V/3.3V) VI(12V/5V/3.3V) VO(AVPP) toff ton VO(AVCC) 90% 90% GND 10% 10% Turnon/off Time (AVPP) GND Turnon/off Time (AVCC) VOLTAGE WAVEFORMS Figure 1. Test Circuits and Voltage Waveforms DATA D10 D9 Data Setup Time D8 D7 D6 D5 Data Hold Time D4 D3 D2 D1 D0 Latch Delay Time LATCH Clock Delay Time CLOCK NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D10, see the control logic table. Figure 2. Serial-Interface Timing for TPS2220B 8 TPS2220B www.ti.com SLVS554 – JANUARY 2005 Table of Graphs FIGURE Short-circuit response, short applied to powered-on 5-V AVCC-switch output vs Time 3 Short-circuit response, short applied to powered-on 12-V AVPP-switch output vs Time 4 OC response with ramped overcurrent-limit load on 5-V AVCC-switch output vs Time 5 OC response with ramped overcurrent-limit load on 12-V AVPP-switch output vs Time 6 AVCC Turnon propagation delay time (CL = 150 µF) vs Junction temperature 7 AVCC Turnoff propagation delay time (CL = 150 µF) vs Junction temperature 8 AVPP Turnon propagation delay time (CL = 10 µF) vs Junction temperature 9 AVPP Turnoff propagation delay time (CL = 10 µF) vs Junction temperature 10 AVCC Turnon propagation delay time (TJ = 25°C) vs Load capacitance 11 AVCC Turnoff propagation delay time (TJ = 25°C) vs Load capacitance 12 AVPP Turnon propagation delay time (TJ = 25°C) vs Load capacitance 13 AVPP Turnoff propagation delay time (TJ = 25°C) vs Load capacitance 14 AVCC Rise time (CL = 150 µF) vs Junction temperature 15 AVCC Fall time (CL = 150 µF) vs Junction temperature 16 AVPP Rise time (CL = 10 µF) vs Junction temperature 17 AVPP Fall time (CL = 10 µF) vs Junction temperature 18 AVCC Rise time (TJ = 25°C) vs Load capacitance 19 AVCC Fall time (TJ = 25°C) vs Load capacitance 20 AVPP Rise time (TJ = 25°C) vs Load capacitance 21 AVPP Fall time (TJ = 25°C) vs Load capacitance 22 9 TPS2220B www.ti.com SLVS554 – JANUARY 2005 SHORT-CIRCIUT RESPONSE, SHORT APPLIED TO POWERED-ON 5-V AVCC-SWITCH OUTPUT SHORT-CIRCIUT RESPONSE, SHORT APPLIED TO POWERED-ON 12-V AVPP-SWITCH OUTPUT VO(/OC) 5 V/div VO(/OC) 2 V/div VIN(5V) 2 V/div IO(xVPP) 2 A/div IO(VCC) 5 A/div 0 100 200 300 400 500 0 1 2 t − Time − µs 4 5 Figure 3. Figure 4. OC RESPONSE WITH RAMPED OVERCURRENT-LIMIT LOAD ON 5-V AVCC-SWITCH OUTPUT OC RESPONSE WITH RAMPED OVERCURRENT-LIMIT LOAD ON 12-V AVPP-SWITCH OUTPUT VO(/OC) 5 V/div VO(/OC) 5 V/div IO(xVCC) 1 A/div IO(xVPP) 100 mA/div 0 10 20 30 t − Time − ms Figure 5. 10 3 t − Time − ms 40 50 0 2 4 6 t − Time − ms Figure 6. 8 10 TPS2220B www.ti.com SLVS554 – JANUARY 2005 0.8 AVCC = 5 V IO = 0.75 A CL = 150 µF 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 t pd(off) − Turnoff Propagation Delay Time, AVCC − ms TURNOFF PROPAGATION DELAY TIME, AVCC vs JUNCTION TEMPERATURE 2.6 AVCC = 5 V IO = 0.75 A CL = 150 µF 2.55 2.5 2.45 2.4 2.35 2.3 2.25 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 7. Figure 8. TURNON PROPAGATION DELAY TIME, AVPP vs JUNCTION TEMPERATURE TURNON PROPAGATION DELAY TIME, AVPP vs JUNCTION TEMPERATURE 3 AVPP = 12 V IO = 0.05 A CL = 10 µF 2.5 2 1.5 1 0.5 0 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 9. 100 t pd(off) − Turnoff Propagation Delay Time, AVCC − ms t pd(on) − Turnon Propagation Delay Time, AVPP − ms t pd(on) − Turnon Propagation Delay Time, AVCC − ms TURNON PROPAGATION DELAY TIME, AVCC vs JUNCTION TEMPERATURE 100 0.9 0.8 0.7 0.6 0.5 0.4 0.3 AVCC = 12 V IO = 0.05 A CL = 10 µF 0.2 0.1 0 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 Figure 10. 11 TPS2220B www.ti.com SLVS554 – JANUARY 2005 AVCC = 5 V IO = 0.75 A TJ = 25°C 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 1 10 100 CL − Load Capacitance − µF 1000 t pd(off) − Turnoff Propagation Delay Time, AVCC − ms 0.7 2.55 AVCC = 5 V IO = 0.75 A TJ = 25°C 2.5 2.45 2.4 2.35 2.3 2.25 0.1 1 10 100 CL − Load Capacitance − µF Figure 11. Figure 12. TURNON PROPAGATION DELAY TIME, AVPP vs LOAD CAPACITANCE TURNON PROPAGATION DELAY TIME, AVPP vs LOAD CAPACITANCE 2.25 2.2 AVPP = 12 V IO = 0.05 A TJ = 25°C 2.15 2.1 2.05 2 1.95 0.1 1 CL − Load Capacitance − µF Figure 13. 12 TURNON PROPAGATION DELAY TIME, AVCC vs LOAD CAPACITANCE 10 t pd(off) − Turnoff Propagation Delay Time, AVPP − ms t pd(on) − Turnon Propagation Delay Time, AVPP − ms t pd(on) − Turnon Propagation Delay Time, AVCC − ms TURNON PROPAGATION DELAY TIME, AVCC vs LOAD CAPACITANCE 1000 0.9 0.8 AVPP = 12 V IO = 0.05 A TJ = 25°C 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 1 CL − Load Capacitance − µF Figure 14. 10 TPS2220B www.ti.com SLVS554 – JANUARY 2005 RISE TIME, AVCC vs JUNCTION TEMPERATURE FALL TIME, AVCC vs JUNCTION TEMPERATURE 1.22 2.41 AVCC = 5 V IO = 0.75 A CL = 150 µF 1.18 2.4 t f − Fall Time AVCC − ms t r − Rise Time, AVCC − ms 1.2 1.16 1.14 1.12 1.1 AVCC = 5 V IO = 0.75 A CL = 150 µF 2.39 2.38 2.37 2.36 1.08 2.35 1.06 1.04 −50 −20 10 40 70 TJ − Junction Temperature − °C 2.34 −50 100 Figure 15. Figure 16. RISE TIME, AVPP vs JUNCTION TEMPERATURE FALL TIME, AVPP vs JUNCTION TEMPERATURE AVPP = 12 V IO = 0.05 A CL = 10 µF 4.1 t f − Fall Time, AVPP − ms 0.6 t r − Rise Time AVPP − ms 100 4.15 0.605 0.595 0.59 0.585 0.58 0.575 −50 −20 10 40 70 TJ − Junction Temperature − °C AVPP = 12 V IO = 0.05 A CL = 10 µF 4.05 4 3.95 3.9 −20 10 40 70 TJ − Junction Temperature − °C Figure 17. 100 3.85 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 Figure 18. 13 TPS2220B www.ti.com SLVS554 – JANUARY 2005 FALL TIME, AVCC vs LOAD CAPACITANCE 1.2 2.5 1 2 t f − Fall Time AVCC − ms t r − Rise Time, AVCC − ms RISE TIME, AVCC vs LOAD CAPACITANCE 0.8 0.6 0.4 AVCC = 5 V IO = 0.75 A TJ = 25°C 0.2 0 0.1 1 10 100 CL − Load Capacitance − µF 1 0 0.1 1000 1 10 100 CL − Load Capacitance − µF Figure 19. Figure 20. RISE TIME, AVPP vs LOAD CAPACITANCE FALL TIME, AVPP vs LOAD CAPACITANCE 1000 4.5 AVPP = 12 V IO = 0.05 A TJ = 25°C 4 t f − Fall Time, AVPP − ms t r − Rise Time, AVPP − ms 1.5 0.5 0.7 0.6 AVCC = 5 V IO = 0.75 A TJ = 25°C 0.5 0.4 0.3 0.2 AVPP = 12 V IO = 0.05 A TJ = 25°C 3.5 3 2.5 2 1.5 1 0.1 0 0.1 0.5 1 CL − Load Capacitance − µF Figure 21. 14 10 0 0.1 1 CL − Load Capacitance − µF Figure 22. 10 TPS2220B www.ti.com SLVS554 – JANUARY 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Input current, AVCC = 3.3 V II rDS(on) VO IOS Input current, AVCC = 5 V 23 vs Junction temperature 24 Input current, AVPP = 12 V 25 Static drain-source on-state resistance, 3.3 V to AVCC switch 26 Static drain-source on-state resistance, 5 V to AVCC switch vs Junction temperature 27 Static drain-source on-state resistance, 12 V to AVPP switch 28 AVCC switch voltage drop, 3.3-V input 29 AVCC switch voltage drop, 5-V input vs Load current 30 AVPP switch voltage drop, 12-V input 31 Short-circuit current limit, 3.3 V to AVCC 32 Short-circuit current limit, 5 V to AVCC Short-circuit current limit, 12 V to AVPP vs Junction temperature 33 34 15 TPS2220B www.ti.com SLVS554 – JANUARY 2005 INPUT CURRENT, AVCC = 3.3 V vs JUNCTION TEMPERATURE INPUT CURRENT, AVCC = 5 V vs JUNCTION TEMPERATURE 160 µA 14 140 I I − Input Current, AVCC = 5 V − I I − Input Current, AVCC = 3.3 V − µ A 180 120 100 80 60 40 −20 10 40 70 TJ − Junction Temperature − °C 6 4 2 100 Figure 24. INPUT CURRENT, AVPP = 12 V vs JUNCTION TEMPERATURE STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 3.3 V TO AVCC SWITCH vs JUNCTION TEMPERATURE 100 80 60 40 20 0 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 23. rDS(on) − Static Drain-Source On-State Resistance, 3.3 V to AVCC Switch − Ω µA 8 0 −50 100 120 I I − Input Current, AVPP = 12 V − 10 20 0 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 25. 16 12 100 0.12 0.1 0.08 0.06 0.04 0.02 0 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 26. 100 TPS2220B www.ti.com SLVS554 – JANUARY 2005 STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 12 V TO AVPP SWITCH vs JUNCTION TEMPERATURE 0.14 rDS(on) − Static Drain-Source On-State Resistance, 12 V to AVPP Switch − Ω rDS(on) − Static Drain-Source On-State Resistance, 5 V to AVCC Switch − Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 5 V TO AVCC SWITCH vs JUNCTION TEMPERATURE 0.12 0.1 0.08 0.06 0.04 0.02 0 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 2 1.5 1 0.5 0 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 28. AVCC SWITCH VOLTAGE DROP, 3.3-V INPUT vs LOAD CURRENT AVCC SWITCH VOLTAGE DROP, 5-V INPUT vs LOAD CURRENT 100 0.14 0.1 VO − AVCC Switch Voltage Drop, 5-V Input − V VO − AVCC Switch Voltage Drop, 3.3-V Input − V 2.5 Figure 27. 0.12 TJ = 100°C 0.08 TJ = 0°C TJ = 25°C 0.06 TJ = −40°C 0.04 TJ = 85°C 0.02 0 3 0 0.2 0.4 0.6 IL − Load Current − A Figure 29. 0.8 1 0.12 TJ = 100°C 0.1 TJ = 0°C 0.08 TJ = 25°C 0.06 TJ = −40°C 0.04 TJ = 85°C 0.02 0 0 0.2 0.4 0.6 IL − Load Current − A 0.8 1 Figure 30. 17 TPS2220B www.ti.com SLVS554 – JANUARY 2005 AVPP SWITCH VOLTAGE DROP, 12-V INPUT vs LOAD CURRENT SHORT-CIRCUIT CURRENT LIMIT, 3.3 V TO AVCC vs JUNCTION TEMPERATURE 1.395 0.12 0.1 TJ = 100°C 0.08 TJ = 0°C TJ = 25°C 0.06 0.04 TJ = −40°C 0.02 0 TJ = 85°C 0 0.01 0.02 0.03 IL − Load Current − A 0.04 0.05 1.385 1.38 1.375 1.37 1.365 1.36 1.355 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 Figure 32. SHORT-CIRCUIT CURRENT LIMIT, 5 V TO AVCC vs JUNCTION TEMPERATURE SHORT-CIRCUIT CURRENT LIMIT, 12 V TO AVPP vs JUNCTION TEMPERATURE I OS − Short-Circuit Current Limit, 12 V to AVPP − A I OS − Short-Circuit Current Limit, 5 V to AVCC − A 1.39 Figure 31. 1.435 1.43 1.425 1.42 1.415 1.41 1.405 1.4 1.395 1.39 1.385 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 33. 18 I OS − Short-Circuit Current Limit, 3.3 V to AVCC − A VO − AVPP Switch Voltage Drop, 12-V Input − V 0.14 100 0.208 0.206 0.204 0.202 AVPP = 12 V 0.2 0.198 0.196 0.194 0.192 0.19 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 34. 100 TPS2220B www.ti.com SLVS554 – JANUARY 2005 APPLICATION INFORMATION OVERVIEW PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-in cards quickly took hold, and modems, wireless LANs, global positioning satellite system (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. Therefore, the PCMCIA (Personal Computer Memory Card International Association) was established, comprising members from leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the plug-and-play concept, so that cards and hosts from different vendors would be transparently compatible. PC CARD POWER SPECIFICATION System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two Vpp terminals were originally specified as separate signals, but are normally tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the Vpp terminals. Cardbus cards of today typically do not use 12 V, which is now more of an optional requirement in the host. DESIGNING FOR VOLTAGE REGULATION The current PCMCIA specification for output voltage regulation, VO(reg), of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply has an output-voltage regulation, VPS(reg), of 2% (100 mV). Also, a voltage drop from the power supply to the PC Card results from resistive losses, VPCB, in the PCB traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the allowable voltage drop, VDS, for the TPS2220B would be the PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops: V
V –V –V DS O(reg) PS(reg) PCB Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification for output voltage regulation of the 3.3-V output is 300 mV; therefore, using the same equation by deducting the voltage drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltage drop for the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance of the device. Therefore, the maximum output current, IO max, that can be delivered to the PC Card in regulation is the allowable voltage drop across the IC, divided by the output-switch resistance. V I max
r DS O DS(on) The AVCC outputs have been designed to deliver the peak and average currents defined by the PC Card specification within regulation over the operating temperature range. The AVPP outputs of the device have been designed to deliver 100 mA continuously. OVERCURRENT AND OVERTEMPERATURE PROTECTION PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against short-circuited cards that can lead to power-supply or PCB trace damage. Even extremely robust systems can undergo rapid battery discharge into a damaged PC Card, resulting in the sudden and unacceptable loss of system power. In comparison, the reliability of fused systems is poor because blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2220B takes a two-pronged approach to overcurrent protection, which is designed to activate if an output is shorted or when an overcurrent condition is present when switches are powered up. First, instead of fuses, sense FETs monitor each of the AVCC and AVPP power outputs. Unlike sense resistors or polyfuses, 19 TPS2220B www.ti.com SLVS554 – JANUARY 2005 APPLICATION INFORMATION (continued) these FETs do not add to the series resistance of the switch; therefore, voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. Excessive current generates an error signal that limits the output current of only the affected output, preventing damage to the host. Each AVCC output overcurrent limits from 1 A to 2.0 A, typically around 1.6 A; the AVPP outputs limit from 100 mA to 250 mA, typically around 200 mA. Second, when an overcurrent condition is detected, the TPS2220B asserts an active low OC signal that can be monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message. If an overcurrent condition persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis. Thermal limiting prevents destruction of the IC from overheating beyond the package power-dissipation ratings. During power up, the devices control the rise times of the AVCC and AVPP outputs and limit the inrush current into a large load capacitance, faulty card, or connector. 12-V SUPPLY NOT REQUIRED Some PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which requires that power be present at all times. The TPS2220B offers considerable power savings by using an internal charge pump to generate the required higher gate drive voltages from the 3.3-V input. Therefore, the external 12-V supply can be disabled except when needed by the PC Card in the slot, thereby extending battery lifetime. A special feature in the 12-V circuitry actually helps to reduce the supply current demanded from the 3.3-V input. When 12 V is supplied and requested at the VPP output, a voltage selection circuit draws the charge-pump drive current for the 12-V FETs from the 12-V input. This selection is automatic and effectively reduces demand fluctuations on the normal 3.3-V VCC rail. For proper operation of this feature, a minimum 3.3-V input capacitance of 4.7 µF is recommended, and a minimum 12-V input ramp-up rate of 12 V/50 ms (240 V/s) is required. Additional power savings are realized during a software shutdown in which quiescent current drops to a maximum of 1 µA. VOLTAGE-TRANSITIONING REQUIREMENT PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2220B meets all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. PC Card specification requires that VCC be discharged within 100 ms. PC Card resistance cannot be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. The devices include discharge transistors on all AVCC and AVPP outputs to meet the specification requirement. SHUTDOWN MODE In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the AVCC and AVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced to 1 µA or less to conserve battery power. POWER-SUPPLY CONSIDERATIONS The devices has multiple pins for 5-V power input and for the switched AVCC output. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is higher than that specified, resulting in increased voltage drops and power loss. It is recommended that all input and output power pins be paralleled for optimum operation. To increase the noise immunity of the TPS2220B the power-supply inputs should be bypassed with at least a 4.7-µF electrolytic or tantalum capacitor paralleled by a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly 20 TPS2220B www.ti.com SLVS554 – JANUARY 2005 APPLICATION INFORMATION (continued) recommended that the switched outputs be bypassed with a 0.1-µF (or larger) ceramic capacitor; doing so improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the devices and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below –0.3 V. RESET INPUT To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at the same time as the host by applying low-impedance paths from AVCC and AVPP terminals to ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active low RESET input closes internal ground switches S1, S4, S7, and S11 with all other switches left open. The TPS2220B remains in the low-impedance output state until the signal is deasserted and further data is clocked in and latched. The input serial data cannot be latched during reset mode. RESET is provided for direct compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an internal 150-kΩ pullup resistor. CALCULATING JUNCTION TEMPERATURE The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figure 26 through Figure 28, using an initial temperature estimate about 30°C above ambient. Then, calculate the power dissipation for each switch, using the formula: P r
I2 D DS(on) Next, sum the power dissipation of all switches and calculate the junction temperature:   T  P
R T J D
JA A where: RθJA is the inverse of the derating factor given in the dissipation rating table. Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate. LOGIC INPUTS AND OUTPUTS The serial interface consists of the DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge of the clock (see Figure 2). The 11-bit (D0-D10) serial data word is loaded during the positive edge of the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock occurs. The serial interface of the device is compatible with serial-interface PCMCIA controllers. An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the AVCC and AVPP outputs as previously discussed. 21 TPS2220B www.ti.com SLVS554 – JANUARY 2005 APPLICATION INFORMATION (continued) TPS2220B CONTROL LOGIC AVPP AVCC AVPP CONTROL SIGNALS AVCC CONTROL SIGNALS OUTPUT V_AVPP D8 (SHDN) D3 D2 X 0V 1 0 0 0V 0 3.3 V 1 0 1 3.3 V 1 1 5V 1 1 0 5V 1 0 X 12 V 1 1 1 0V 1 1 X Hi-Z 0 X X Hi-Z X X X Hi-Z D8 (SHDN) D0 D1 D9 1 0 0 1 0 1 1 0 1 1 0 OUTPUT V_AVCC ESD PROTECTIONS (see Figure 35) All inputs and outputs of these devices incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C, Method 3015. The AVCC and AVPP outputs can be exposed to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV. TPS2220B AVCC 0.1 µF† AVCC VCC VCC PC Card Connector A AVPP 12 V 4.7 µF 0.1 µF 4.7 µF 0.1 µF 5V 12 V 0.1 µF† Vpp1 Vpp2 5V 5V Controller DATA DATA 3.3 V 4.7 µF 0.1 µF 3.3 V LATCH LATCH RESET OC † CLOCK CLOCK From PCI or System RST GPI/O Maximum recommended output capacitance for AVCC is 220 µF including card capacitance, and for AVPP is 10 µF, without OC glitch when switches are powered on. Figure 35. Detailed Interconnections and Capacitor Recommendations 22 TPS2220B www.ti.com SLVS554 – JANUARY 2005 12-V FLASH MEMORY SUPPLY The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 36, the only external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of PCB space when implemented with surface-mount components. An enable input is provided to shut the converter down and reduce the supply current to 3 µA when 12 V is not needed. The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one small capacitor. A 1.22-V reference, pin 2 of TPS6734, is brought out for external use. For additional information, see the TPS6734 data sheet (SLVS127). TPS2220B AVCC 3.3 V or 5 V Enable (see Note A) R1 10 kΩ 1 2 C1 33 µF 20 V + 3 4 C2 0.01 µF AVCC TPS6734 EN VCC REF FB SS OUT COMP GND C4 0.001 µF 8 L1 18 µH AVPP 7 6 5 D1 33 µF, 20 V + C1 12 V 5V 1 µF 12 V 0.1 µF 0.1 µF 5V DATA 5V CLOCK LATCH 3.3 V 4.7 µF 0.1 µF 3.3 V† RESET OC SHDN NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high. Figure 36. TPS2220B With TPS6734 12-V, 120-mA Supply 23 PACKAGE OPTION ADDENDUM www.ti.com 11-Sep-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS2220BDB ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TPS2220B TPS2220BDBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TPS2220B TPS2220BPWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS2220B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Sep-2016 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2220BDBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 TPS2220BPWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2220BDBR SSOP DB 24 2000 367.0 367.0 38.0 TPS2220BPWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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