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TPS2221PWPR

TPS2221PWPR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    HTSSOP-14_5X4.4MM-EP

  • 描述:

    TPS2221 1A SINGLE-SLOT CARDBAY P

  • 数据手册
  • 价格&库存
TPS2221PWPR 数据手册
TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 PC CARD POWER-INTERFACE SWITCH FOR PCMCIA CONTROLLERS FEATURES D Provides S−CARD abd M−CARD Power D D D D D D D D D D D D Management for CableCARDTM Applications Fully Integrated VCC and VPP/VCORE Switching Meets PC Card Standards VPP/VCORE Output Programmed Independent of VCC TTL-Logic Compatible Inputs Short Circuit and Thermal Protection 20-Pin HTSSOP or 30-Pin SSOP (Dual With Serial Interface) Package 14-pin HTSSOP Package (Single With Parallel Interface) 95 µA Typ Quiescent Current on 3.3 VIN Input (Dual With Serial Interface) 64 µA Typ Quiescent Current on 3.3 VIN Input (Single With Parallel Interface) Break-Before-Make Switching Power On Reset −40°C to 85°C Ambient Operating Temperature Range DESCRIPTION The TPS2228 and TPS2221 PC card power interface switches provide an integrated power management solution for both dual and single PC card sockets. The TPS2228 is a dual-slot power interface switch for serial PCMCIA controllers. The TPS2221 is a single-slot power interface switch for parallel PCMCIA controllers. These power interface switches support the distribution of 3.3 V, 5 V and 1.8 V to the PC card slot while providing current-limiting protection with overcurrent reporting. ORDERING INFORMATION(1) PACKAGED DEVICES TA DUAL HTSSOP, SSOP TPS2228PWP (20) −40°C 40°C to 85°C (1) SINGLE HTSSOP TPS2221PWP (14) TPS2228DB (30) Both DB and PWP packages are available taped and reeled (indicated by the R suffix on the device type; e.g., TPS2228PWPR). APPLICATIONS D Notebook/Desktop Computers D Personal Digital Assistants (PDAs) D Digital Cameras D Bar-code Scanners Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CableCard is a trademark of Cable Television Laboratories, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS2228, TPS2221 Input voltage range for card power VI(3.3VIN) −0.3 V to 6 V VI(5VIN) −0.3 V to 6 V VI(1.8VIN) −0.3 V to 6 V Logic input/output voltage −0.3 V to 6 V Output voltage range VO(XVCC) −0.3 V to 6 V VO(XVPP/VCORE) −0.3 V to 6 V Continuous total power dissipation See Dissipation Rating Table IO(XVCC) Output current Internally Limited IO(XVPP/VCORE) Operating virtual junction temperature range, TJ −40°C to 100°C Storage temperature range, Tstg −55°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C OC sink current 10 mA (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS TABLE (THERMAL RESISTANCE = °C/W)(1) PACKAGE(2) DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 20-PWP 30.67 mW/°C 2300 mW 920.25 mW 460.12 mW 14-PWP 26.67 mW/°C 2000 mW 800 mW 400 mW DB-30 10.95 mW/°C 821.47 mW 328.59 mW 164.3 mW (1) Reference Calculating Junction Temperature in the application information section of this data sheet. (2) These devices are mounted on an JEDEC low-k board (2 oz. traces on surface) (Based on the maximum recommended junction temperature of 100°C) RECOMMENDED OPERATING CONDITIONS Input voltage, VI 3.3VIN is required for all circuit operations. 5VIN and 1.8VIN are only required for their respective functions. MIN MAX VI(3.3VIN) 3.0 3.6 V VI(5VIN) 2.7 5.5 V VI(1.8VIN) 1.7 5.5 V 1 A IO(XVCC) at TJ =100°C Output current UNIT IO(XVPP/VCORE) when switched to 5VIN at TJ =100°C 100 mA IO(XVPP/VCORE) when switched to 3.3VIN or 1.8VIN at TJ =100°C 500 mA 2.5 MHz Clock frequency Data 200 ns Latch 250 ns Clock 100 ns Reset 100 ns Data to clock hold time (Figure 2) 100 ns Data to clock setup time (Figure 2) 100 ns Latch delay time (Figure 2) 100 ns Clock delay time (Figure 2) 250 ns Operating virtual junction temperature, TJ (maximum to be calculated at worst case PD at 85°C ambient) −40 Pulse duration 2 100 °C TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS TJ = −40°C to 100°C, VI(5VIN) = 5 V, VI(3.3VIN) = 3.3 V, VI(1.8VIN) = 1.8 V, all outputs unloaded (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SWITCH Switch resistance 3.3VIN to XVCC with two switches on for dual TJ = 25°C, I = 750 mA each 5VIN to XVCC with two switches on for dual TJ = 25°C, I = 500 mA each 1.8VIN to XVPP/VCORE with two switches on for dual TJ = 25°C, I = 375 mA each 3.3VIN to XVPP/VCORE with two switches on for dual TJ = 25°C, I = 250 mA each 5VIN to XVPP/VCORE with two switches on for dual TJ = 25°C, I = 100 mA each RO(XVCC) discharge resistance RO(XVPP/VCORE) discharge resistance Limit IO(XVCC) 3.3VIN or 5VIN to XVCC IOS Short-circuit Short circuit output current(1) IO(XVPP/VCORE) 5VIN to XVPP/VCORE IO(XVPP/VCORE) 1 8VIN or 3 1.8VIN 3.3VIN 3VIN to XVPP/VCORE Thermal shutdown ( (limit is th steady the t d state value.) 97 TJ = 100°C, I = 500 mA each 69 196 TJ = 100°C, I = 100 mA each 1.3 1.6 mΩ Ω Idischarge = 1 mA 0.1 0.5 kΩ Idischarge = 1 mA 0.1 0.5 kΩ TJ at 25°C, output powered into a short 1 TJ [−40, 100°C], output powered into a short 1 1.5 A 2.5 120 TJ [−40, 100°C], output powered into a short 120 Limit TJ at 25°C, output powered into a short 500 Limit TJ [−40, 100°C], output powered into a short 500 175 Rising temperature, not in overcurrent condition 155 165 Overcurrent condition 120 130 300 mA 680 mA 1250 °C 10 Current limit response time(2)(3) VO(xVCC) = 5 V, 100 mΩ short to GND, TJ = 25°C 10 VO(xVCC) = 3.3 V, 100 mΩ short to GND, TJ = 25°C 20 VO(xVPP/VCORE) = 5 V, 100 mΩ short to GND, TJ = 25°C 2 VO(xVPP/VCORE) = 3.3 V, 100 mΩ short to GND TJ = 25°C 35 VO(xVPP/VCORE) = 1.8 V, 100 mΩ short to GND, TJ = 25°C 250 II (3.3VIN) II(5VIN) VO(xVCC) = VO(xVPP/VCORE) = VI(3.3VIN), Output pins are floated 140 5 10 64 100 5 10 µA 5 II (3.3VIN) II(5VIN) µs 95 II (1.8VIN) Normall operation N ti off TPS2221 mΩ 260 325 0.9 mΩ 95 120 TJ = 100°C, I = 250 mA each mΩ 125 160 TJ = 100°C, I = 375 mA each Hysteresis Ii IInputt Q Quiescent i t current 95 120 TJ at 25°C, output powered into a short Limit Trip point, point TJ Normall operation N ti off TPS2228 72 TJ = 100°C, I = 750 mA each VO(xVCC) = VO(xVPP/VCORE) = VI(3.3VIN), Output pins are floated II (1.8VIN) 5 Shutdown mode (based on control data) II (3.3VIN) 5 VO(xVCC) = Hi-Z II (5VIN) VO(xVPP/VCORE) = Hi-Z II (1.8VIN) O t t pins Output i are floated fl t d 5 µA µA A 5 (1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Specified by design, not tested in production. (3) From application of short to 110% of final current limit. (2) 3 TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) TJ = −40°C to 100°C, VI(5VIN) = 5 V, VI(3.3VIN) = 3.3 V, VI(1.8VIN) = 1.8 V, all outputs unloaded (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX 1 10 UNIT POWER SWITCH (continued) Forward leakage g current Ilkg_FWD (current measured from output pins to ground) IO(xVCC) All switches are in Hi-Z Hi Z state xVCC and xVPP/VCORE are grounded µA A IO(xVPP/VCORE) Reverse leakage current Ilkg_RVS lk RVS (current measured f from output t t pins i going i in) i ) IO(3.3VIN) All switches are in Hi-Z Hi Z state, state 3 3VIN 5VIN 3.3VIN, 5VIN, and 1 1.8VIN 8VIN are grounded VO(xVPP/VCORE) ( ) = VO(xVCC) ( )= 5 V IO(5VIN) IO(1.8VIN) 1 10 1 10 1 10 1 10 µA A (1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Specified by design, not tested in production. (3) From application of short to 110% of final current limit. (2) ELECTRICAL CHARACTERISTICS TJ = −40°C to 100°C, VI(5VIN) = 5 V, VI(3.3VIN) = 3.3 V, VI(1.8VIN) = 1.8 V, all outputs unloaded (unless otherwise noted)(1) TEST CONDITIONS(1) PARAMETER MIN TYP MAX UNIT LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC, VDO, VD1, VD2, VD3) RESET = 5.5 V, sinking or sourcing I(RESET)(3) Logic input current RESET = 0 V, sourcing I(SHDN)(3) Or I(SHDN_RST)(3) 0 10 SHDN or SHDN_RST = 5.5 V, sinking or sourcing SHDN or SHDN_RST = 0 V, sourcing 0 10 I(CLOCK,DATA, VD0, VD1, VD2, VD3) 50 LATCH = 0 V, sinking or sourcing 1 0 V to 5.5 V, sinking or sourcing 1 Logic input high level(4) µA 2 Logic input low level(4) 0.8 OC output saturation voltage IO = 2 mA OC leakage current VO(OC) = 5.5 V OC d deglitch lit h(2) 1 30 LATCH = 5.5 V, sinking I(LATCH)(1) 1 30 0.4 1 Falling edge Falling into overcurrent condition 5 15 Rising edge Coming out of overcurrent condition 5 15 PARAMETER TEST CONDITIONS(1) V MIN TYP MAX µA mS S UNIT UVLO 3.3VIN UVLO 3.3VIN level below which all switches are in Hi-Z state 2.2 3.3VIN Hysteresis(2) 5VIN UVLO 5VIN level below which only 5VIN switches are in Hi-Z state 2.0 5VIN Hysteresis(2) 1.8VIN UVLO 1.8VIN (1) 4 V 2.6 80 1.8VIN level below which only 1.8VIN switches are in Hi-Z state Hysteresis(2) Refer to Parameter Measurement Information, Figure 1. Specified by design, not tested in production. (3) RESET and SHDN (or SHDN/RST for TPS2221) have low current pullup; LATCH has low current pulldown. (4) For recommended operating ranges only. (2) 2.9 0.1 1.25 mV 1.62 50 V mV TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS TJ = −40°C to 100°C, VI(5VIN) = 5 V, VI(3.3VIN) = 3.3 V, VI(1.8VIN) = 1.8 V, all outputs unloaded (unless otherwise noted)(1) PARAMETER(1) TEST CONDITIONS(1) MIN TYP MAX UNIT SWITCHING CHARACTERISTICS 5VIN to xVCC 3.3VIN to xVCC 1.8VIN to xVPP/VCORE 3.3VIN to xVPP/VCORE 5VIN to xVPP/VCORE tr Output rise times(2) 5VIN to xVCC 3.3VIN to xVCC 1.8VIN to xVPP/VCORE 3.3VIN to xVPP/VCORE 5VIN to xVPP/VCORE 5VIN to xVCC 3.3VIN to xVCC 1.8VIN to xVPP/VCORE 3.3VIN to xVPP/VCORE 5VIN to xVPP/VCORE tf Output fall times(2) 5VIN to xVCC 3.3VIN to xVCC 1.8VIN to xVPP/VCORE 3.3VIN to xVPP/VCORE tpd Propagation delay(2) tpd Propagation delay(2) (1) (2) CL(xVCC) = 0 0.1 1 µF, µF IO(xVCC) = 0 A, A CL(xVPP/VCORE) = 0.1 µF, IO(xVPP/VCORE) = 0 A CL(xVPP/VCORE) = 0.1 µF, IO(xVPP/VCORE) = 0 A CL(xVCC)= 150 µF, µF IO(xVCC) = 0 0.75A 75A CL(xVPP/VCORE) = 150 µF, IO(xVPP/VCORE) = 0.375A CL(xVPP/VCORE) = 10 µF, IO(xVPP/VCORE) = 0.05A CL(xVCC) = 0 0.1 1 µF, µF IO(xVCC) = 0 A, A CL(xVCC) = 0 0.1 1 µF, µF IO(xVCC) = 0 A, A CL(xVPP/VCORE) = 0.1 µF, IO(xVPP/VCORE) = 0 A CL(xVCC) = 150 µF, µF IO(xVCC) = 0.75A 0 75A CL(xVCC) = 150 µF, IO(xVPP/VCORE) = 0.375 A 0.5 2 0.5 2 0.5 2 0.15 1 0.05 0.14 0.75 2.0 0.75 2.0 0.50 2.0 0.50 1.15 0 15 0.15 0 375 0.375 0.25 1.0 0.35 1.0 0.25 1.0 0.1 0.5 0 075 0.075 0 15 0.15 1.4 2.5 1.4 1.7 1.4 2.0 2.5 3.1 1.7 2.1 5VIN to xVPP/VCORE CL(xVPP/VCORE) = 10 µF, IO(xVPP/VCORE) = 0.05 A Latch↑ to xVPP/VCORE (1 (1.8 8 V) CL(xVPP/VCORE) = 0.1 µF, IO(xVPP/VCORE) = 0 A tpdon 0.15 1.4 tpdoff 2.5 8.6 Latch↑ to xVPP/VCORE (3 (3.3 3 V) CL(xVPP/VCORE) = 0.1 µF, IO(xVPP/VCORE) = 0 A tpdon 0.05 0.5 tpdoff 0.5 2.5 Latch↑ to xVPP/VCORE (5 V) CL(xVPP/VCORE) = 0.1 µF, IO(xVPP/VCORE) = 0 A tpdon 0.02 0.3 tpdoff 0.10 0.3 Latch↑ to xVCC (5 V) CL(xVCC) = 0.1 µF, IO(xVCC) = 0 A tpdon 0.15 0.85 tpdoff 1.3 3.7 Latch↑ to xVCC (3.3 (3 3 V) CL(xVCC) = 0.1 µF, IO(xVCC) = 0 A tpdon 0.15 1.0 tpdoff 1.7 5.3 Latch↑ to xVPP/VCORE (1 (1.8 8 V) CL(xVPP/VCORE) = 150 µF, IO(xVPP/VCORE) = 0.375 A tpdon 0.35 1.9 tpdoff 2.4 8.5 Latch↑ to xVPP/VCORE (3 (3.3 3 V) CL(xVPP/VCORE) = 150 µF, IO(xVPP/VCORE) = 0.375 A tpdon 0.2 0.75 tpdoff 0.5 2.5 Latch↑ to xVPP/VCORE (5 V) CL(XVPP/VCORE) = 10 µF, IO(xVPP/VCORE) = 0.05 A tpdon 0.05 0.15 tpdoff 0.15 0.35 Latch↑ to xVCC (5 V) CL(XVCC) = 150 µF, IO(xVCC) = 0.75 A tpdon 0.35 1.2 tpdoff 1.3 3.7 Latch↑ to xVCC (3 (3.3 3 V) V), CL(XVCC) = 150 µF, IO(xVCC) = 0.75 A tpdon 0.4 1.4 tpdoff 1.5 5.2 ms ms ms ms Refer to Parameter Measurement Information, Figure 1. Specified by design, not tested in production 5 TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION xVPP/VCORE xVCC IO(xVPP/VCORE) IO(xVCC) LOAD CIRCUIT (xVPP/VCORE) LOAD CIRCUIT (xVCC) VDD LATCH VDD LATCH 50% 50% GND tpd(on) GND tpd(off) VI(1.8V/5V/3.3V) 90% VO(xVPP/VCORE) tpd(on) VI(5V/3.3V) VO(xVCC) Propagation Delay (xVCC) tf tf tr VI(1.8V/5V/3.3V) VO(xVCC) 90% GND 10% GND 10% Propagation Delay (xVPP) VO(xVPP/VCORE) 90% GND 10% tr tpd(off) VI(5V/3.3V) 90% GND 10% Rise/Fall Time (xVCC) Rise/Fall Time (xVPP) VDD LATCH VDD 50% 50% LATCH GND ton VO(xVPP/VCORE) GND toff toff ton VI(1.8V/5V/3.3V) 90% 10% VI(5V/3.3V) VO(xVCC) 90% GND 10% Turn On/Off Time (xVPP) Turn On/Off Time (xVCC) VOLTAGE WAVEFORMS Figure 1. Test Circuits and Voltage Waveforms 6 GND TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION DATA D10 D9 D8 D7 Data Setup Time D6 D5 D4 Data Hold Time D3 D2 D1 D0 Latch Delay Time LATCH Clock Delay Time CLOCK NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D10, see the control logic table. Figure 2. Serial-Interface Timing for TPS2228/TPS2221 Power Interface Switch TABLE OF GRAPHS FOR POWER MEASUREMENT INFORMATION FIGURE Short-Circuit Current Response, Short Applied to Powered-on 5VIN-to-xVCC Switch Output vs Time 3 Short-Circuit Current Response, Short Applied to Powered-on 3.3VIN-to-xVCC Switch Output vs Time 4 OC Response With 5VIN-to-xVCC Switch Output Turned on Into a Short vs Time 5 OC Response With 3.3VIN-to-xVCC Switch Output Turned on Into a Short vs Time 6 3.3VIN and 5VIN Input Current vs Junction Temperature 7 3.3VIN and 5VIN Input Current vs Junction Temperature 8 1.8VIN Input Current vs Junction Temperature 9 Static Drain-Source On-State Resistance, 3.3VIN to xVCC Switch vs Junction Temperature 10 Static Drain-Source On-State Resistance, 5VIN to xVCC Switch vs Junction Temperature 11 Static Drain-Source On-State Resistance, 3.3VIN to xVPP/VCORE Switch vs Junction Temperature 12 Static Drain-Source On-State Resistance, 5VIN to xVPP/VCORE Switch vs Junction Temperature 13 Static Drain-Source On-State Resistance, 1.8VIN to xVPP/VCORE Switch vs Junction Temperature 14 Short-Circuit Current Limit, 3.3VIN to xVCC Switch vs Junction Temperature 15 Short-Circuit Current Limit, 5VIN to xVCC Switch vs Junction Temperature 16 Short-Circuit Current Limit, 3.3VIN to xVPP/VCORE Switch vs Junction Temperature 17 Short-Circuit Current Limit, 5VIN to xVPP/VCORE Switch vs Junction Temperature 18 Short-Circuit Current Limit, 1.8VIN to xVPP/VCORE Switch vs Junction Temperature 19 7 TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION 5VIN 1V/DIV 3.3VIN 0.5V/DIV IO(xVCC) IO(xVCC) 5A/DIV 5A/DIV 0 10 20 30 t − Time − µs 40 Figure 3. Short-Circuit Response, Short Applied to Powered-on 5VIN-to-xVCC Switch Output CI = 10 µF CO = 150 µF OC 2V/div 40 80 120 t − Time − µs 160 180 Figure 4. Short-Circuit Response, Short Applied to Powered-on 3.3VIN-to-xVCC-Switch Output CI = 10 µF CO = 150 µF OC 2V/div IO(VCC) 1A/div IO(VCC) 1A/div 0 4 8 12 16 t − Time − ms Figure 5. OC Response With 5VIN-to-xVCC Switch Output Turned on Into a Short 8 0 50 20 0 4 8 12 16 20 t − Time − ms Figure 6. OC Response With 3.3VIN-to-xVCC Switch Output Turned on Into a Short TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION 3.3VIN AND 5VIN INPUT CURRENT vs JUNCTION TEMPERATURE 3.3VIN AND 5VIN INPUT CURRENT vs JUNCTION TEMPERATURE 100 180 xVCC = xVPP/VCORE = 5 V I I − 3.3VIN And 5VIN Input Current − µ A I I − 3.3VIN And 5VIN Input Current − µ A xVCC, xVPP/VCORE = 3.3 V 160 140 120 100 80 TPS2228 −3.3VIN TPS2221 − 3.3VIN 60 40 20 0 −50 TPS2228 and TPS2221 − 5VIN 90 80 70 50 40 30 20 Figure 8 STATIC DRAIN-SOURCE ON-STATE RESISTANCE (3.3VIN TO xVCC SWITCH) vs JUNCTION TEMPERATURE I I − 1.8VIN Input Current − µ A rDS(on)− Static Drain-Source On-State Resistance (3.3IN to xVCCSwitch) − Ω 40 xVCC = 3.3 V xVPP/VCORE = 1.8 V 30 25 20 15 TPS2228 TPS2221 5 0 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 9 TPS2221 − 5VIN −40 25 100 TJ − Junction Temperature − °C 100 1.8VIN INPUT CURRENT vs JUNCTION TEMPERATURE 10 TPS2228 − 5VIN 10 Figure 7 35 TPS2221 − 3.3VIN 60 0 −20 10 40 70 TJ − Junction Temperature − °C TPS2228 − 3.3VIN 100 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 Figure 10 9 TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 −50 STATIC DRAIN-SOURCE ON-STATE RESISTANCE (3.3VIN TO xVPP/VCORE SWITCH) vs JUNCTION TEMPERATURE rDS(on)− Static Drain-Source On-State Resistance (3.3VIN to xVPP/VCORE Switch) − Ω rDS(on)− Static Drain-Source On-State Resistance (5VIN to xVCC Switch) − Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE (5VIN TO xVCC SWITCH) vs JUNCTION TEMPERATURE −20 10 40 70 100 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 −50 TJ − Junction Temperature − °C Figure 11 1.6 1.4 1.2 1 0.8 0.6 0.40 0.2 10 40 70 Figure 13 100 rDS(on)− Static Drain-Source On-State Resistance (1.8VIN to xVPP/VCORE Switch) − Ω rDS(on)− Static Drain-Source On-State Resistance (5VIN to xVPP/VCORE Switch) −Ω 1.8 TJ − Junction Temperature − °C 10 STATIC DRAIN-SOURCE ON-STATE RESISTANCE (1.8VIN TO xVPP/VCORE SWITCH) vs JUNCTION TEMPERATURE 2 −20 100 Figure 12 STATIC DRAIN-SOURCE ON-STATE RESISTANCE (5VIN TO xVPP/VCORE SWITCH) vs JUNCTION TEMPERATURE 0 −50 −20 10 40 70 TJ − Junction Temperature − °C 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 14 100 TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION SHORT-CIRCUIT CURRENT LIMIT (5VIN TO xVCC) vs JUNCTION TEMPERATURE 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 I OS − Short-Circuit Current Limit (5VIN to xVCC) − A I OS − Short-Circuit Current Limit (3.3VIN to xVCC) − A SHORT-CIRCUIT CURRENT LIMIT (3.3VIN TO xVCC) vs JUNCTION TEMPERATURE 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 −50 SHORT-CIRCUIT CURRENT LIMIT (3.3VIN TO xVPP/VCORE) vs JUNCTION TEMPERATURE 1000 900 800 700 600 500 400 300 200 100 0 −50 −20 10 40 70 TJ − Junction Temperature − °C Figure 17 100 Figure 16 100 I OS − Short-Circuit Current Limit (5VIN to xVPP/Vcore) − mA I OS − Short-Circuit Current Limit (3.3VIN to xVPP/VCORE) − mA Figure 15 −20 10 40 70 TJ − Junction Temperature − °C SHORT-CIRCUIT CURRENT LIMIT (5VIN TO xVPP/VCORE) vs JUNCTION TEMPERATURE 300 250 200 150 100 50 0 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 Figure 18 11 TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 I OS − Short-Circuit Current Limit (1.8VIN to xVPP/VCORE) − mA PARAMETER MEASUREMENT INFORMATION SHORT-CIRCUIT CURRENT LIMIT (1.8VIN TO xVPP/VCORE) vs JUNCTION TEMPERATURE 1000 900 800 700 600 500 400 300 200 100 0 −50 −20 10 40 70 100 TJ − Junction Temperature − °C Figure 19 PIN ASSIGNMENTS TPS2228DB 5VIN 5VIN DATA CLOCK LATCH 1.8VIN NC AVPP/VCORE AVCC AVCC AVCC GND NC RESET 3.3VIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TPS2228PWP 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5VIN 5VIN NC DATA 1.8VIN CLOCK NC LATCH NC 1.8VIN SHDN AVPP/VCORE NC AVCC AVCC BVPP/VCORE GND BVCC RESET BVCC BVCC NC OC 3.3VIN 3.3VIN NC − No internal connection TPS2221PWP VD1 VD0 3.3VIN VCC VCC 5VIN GND 12 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VD2 VD3 VPP/VCORE VPP/VCORE 1.8VIN OC SHDN_RST 20 19 18 17 16 15 14 13 12 11 5VIN 1.8VIN SHDN BVPP/VCORE NC BVCC BVCC OC 3.3VIN 3.3VIN TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION Terminal Functions (Dual-Serial) TERMINAL NO. NAME I/O DESCRIPTION 2228 (DB−30) 2228 (PWP−20) 1.8VIN 6, 28 5, 19 I 1.8-V input for card power (xVPP/VCORE). Pins 6 and 28 must be connected together externally. 3.3VIN 15, 16, 17 11, 12 I 3.3-V input for card power (xVCC and xVPP/Vcore) and chip power (3.3VIN must be connected to a voltage source for the device to operate) 5VIN 1, 2, 30 1, 20 I 5-V input for card power (xVCC and xVPP/Vcore) AVCC 9, 10, 11 7, 8 O Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance to card 8 6 O Switched output that delivers 0 V, 1.8 V, 3.3 V, 5 V, or high impedance to card 20, 21, 22 14, 15 O Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance to card BVPP/VCORE 23 17 O Switched output that delivers 0 V, 1.8 V, 3.3 V, 5 V, or high impedance to card CLOCK 4 3 I Logic-level clock for serial data word DATA 3 2 I Logic-level serial data word GND 12 9 LATCH 5 4 NC 7,13,19, 24, 26, 27, 29 16 OC 18 13 O Open-drain output that is asserted low when an overcurrent condition exists. RESET 14 10 I Logic-level RESET input. Asynchronous command active low. An internal pullup is provided. When active, all line switches are off and all the output discharge switches are on. SHDN 25 18 I Hi-Z (open) all switches. Identical function to serial shutdown with D8=0. Asynchronous command active low. An internal pullup is provided. AVPP/VCORE BVCC Ground I Logic-level latch for serial data word, an internal pulldown is provided No internal connection Terminal Functions (Single − Parallel) TERMINAL NO. NAME I/O DESCRIPTION 2221 (PWP−14) 1.8VIN 10 I 1.8-V input for card power (VPP/VCORE) 3.3VIN 3 I 3.3-V input for card power (VCC and VPP/Vcore) and chip power (3.3VIN must be connected to a voltage source for the device to operate) 5VIN 6 I 5-V input for card power (VCC and VPP/Vcore) GND 7 OC 9 O Open-drain output that is asserted low when an overcurrent condition exists. SHDN_RST 8 I Hi-Z (open) all switches. Identical function to serial shutdown mode by parallel data VD (3:0). Asynchronous command active low. An internal pullup is provided. VCC 4, 5 O Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance to card VD0 2 I Parallel control signal 0 (see Table 2. TPS2221 Control Logic) VD1 1 I Parallel control signal 1 (see Table 2. TPS2221 Control Logic) VD2 14 I Parallel control signal 2 (see Table 2. TPS2221 Control Logic) VD3 13 I Parallel control signal 3 (see Table 2. TPS2221 Control Logic) 11, 12 O Switched output that delivers 0 V, 1.8 V, 3.3 V, 5 V, or high impedance to card VPP/VCORE Ground 13 TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 FUNCTIONAL BLOCK DIAGRAM DUAL WITH SERIAL INTERFACE S2 3.3VIN AVCC CS S5 S1 3.3VIN AVCC S3 5VIN 5VIN 5VIN 1.8VIN{ 1.8VIN{ S6 CS S13 BVCC S4 BVCC S14 S8 AVPP/AVCORE CS S9 S7 S11 BVPP/BVCORE CS S12 S10 Control Logic Current Limit SHDN RESET Thermal Limit DATA CLOCK LATCH GND UVLO OC † 14 POR The two 1.8VIN pins must be connected together externally TPS2228 TPS2221 www.ti.com SLVS419C − MAY 2002 REVISED DECEMBER 2008 FUNCTIONAL BLOCK DIAGRAM SINGLE WITH PARALLEL INTERFACE S2 3.3 V CS VCC S1 VCC S3 5V S5 1.8 V S6 CS VPP/VCORE S7 S4 VPP/VCORE Control Logic SHDN VD3 Current Limit VD2 Thermal Limit VD1 VD0 GND UVLO OC POR 15 TPS2228 TPS2221 www.ti.com SLVS419A − MAY 2002 REVISED SEPTEMBER 2002 APPLICATION INFORMATION OVERVIEW PC cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with limited onboard memory. The idea of add-in cards quickly took hold; modems, wireless LANs, GPS systems, multimedia, and hard-disk versions were soon available. As the number of PC card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. As a result, the PCMCIA (Personal Computer Memory Card International Association) was established, comprised of members from leading computer, software, PC card, and semiconductor manufacturers. One key goal was to realize the plug-and-play concept, so that cards and hosts from different vendors could communicate with one another transparently. PC CARD POWER SPECIFICATION The current PC card standard set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the PC card connector’s 68 terminals. This power interface consists of two VCC, two VPP/VCORE, and four ground terminals. Multiple power and ground terminals minimize connector-terminal and line resistance. The two Vpp/ Vcore terminals were originally specified as separate signals, but the host is no longer required to provide separate programmable voltages on each pin. Primary power for the card is supplied through the VCC terminals; flash- memory programming and erase voltage is supplied through the VPP/VCORE terminals. The VPP/VCORE terminals are also intended to be used as a supplemental source of power, such as a core voltage for integrated circuits. OVERCURRENT AND OVER TEMPERATURE PROTECTION PC cards are inherently subject to damage caused by mishandling. Host systems require protection against short-circuited cards that could lead to power supply or PCB trace damage. Even systems sufficiently robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC card, resulting in the rather sudden and unacceptable loss of system power. The TPS2228/2221 power interface switch is designed to respond quickly to an overcurrent condition to protect the system. During an overcurrent event, the current limit circuit of the TPS2228/2221 generates an internal error signal that linearly limits the output current of the affected output. The propogation delay associated with activating the current-limit circuit has an effect on the amount of current initially delivered to the output. During this time, the 16 input voltage to the switch may droop a small amount. The amount of voltage droop is system dependent. Power supply bulk capacitors play an important role in minimizing this voltage droop. Overcurrent sensing is applied to each output separately. As a result, only the affected output is current-limited during an overcurrent event. The TPS2228/2221 also has an overcurrent status output (OC) that is asserted low to provide feedback that an overcurrent condition has occurred. The TPS2228/2221 has two thermal shutdown circuits. The higher thermal shutdown circuit protects the device from a high junction temperature condition. In the event that the junction temperature exceeds a minimum of 155°C, the higher thermal shutdown circuit turns off all switches to protect the device. Normal switch operation resumes when the junction temperature cools down approximately 10°C. In the event of an overcurrent condition, the lower thermal shutdown circuit activates when the junction temperature exceeds a minimum of 120°C. On the TPS2221, this lower thermal shutdown circuit disables both the VCC and the VPP/VCORE switches once the junction temperature exceeds the lower thermal trip point. On the TPS2228, only the channel in overcurrent (either AVCC and AVPP/VCORE, or BVCC and BVPP/VCORE) is disabled. For both the TPS2221 and the TPS2228, normal operation of the switches resumes once the junction temperature cools down approximately 10°C. This cycle continues until the overcurrent condition is removed. VOLTAGE TRANSISTIONING REQUIREMENT PC cards, like portables, are migrating from 5 V to 3.3 V and even 1.8 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2228/2221 power interface switch is designed to meet all combinations of power delivery as currently defined in the PC card standard. The latest protocol accommodates mixed 3.3 V/ 5 V systems by first powering the card with 5 V, then polling it to determine if it is compatible with 3.3-V power. The PC card standard requires that the capacitors on 3.3-V compatible cards be discharged to below 0.8 V before applying 3.3 V power. This ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. The PC card standard requires that VCC be discharged within 100 ms. PC card resistance can not be relied on to provide a discharge path for voltages stored on PC card capacitance because of possible high-impedance isolation by power-management schemes. The TPS2228/2221 power interface switch includes discharge transistors on all VCC and VPP/VCORE outputs to meet the specification requirement. TPS2228 TPS2221 www.ti.com SLVS419A − MAY 2002 REVISED SEPTEMBER 2002 Next, sum the power dissipation and calculate the junction temperature: SHUTDOWN MODE In the shutdown mode, each of the VCC and VPP/VCORE outputs is forced to a high-impedance state (Hi-Z). In this mode, the chip quiescent current is reduced to conserve battery power. ǒ TJ + S P D R qJA Ǔ ) TA POWER SUPPLY CONSIDERATIONS Where RθJA is the inverse of the derating factor in the dissipation rating table. The TPS2228/2221 power interface switch has multiple pins for each of its power inputs and for the switched VCC outputs. The two 1.8VIN pins must be connected together externally. It is recommended that all input and output power pins be parallel connected for optimum operation. Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate. To increase the noise immunity of the TPS2228/2221 power interface switch, the power supply inputs should have a minimum of 1µF electrolytic or tantalum bypass capacitor connected in parallel with a 0.047 µF to 0.1 µF ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1 µF or larger ceramic capacitor. Doing so improves the immunity of the TPS2228/2221 power interface switch to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2228/2221 power interface switch and the load. RESET To ensure that cards are in a known state after power brownouts or system initialization, the PC cards should be reset at the same time via the host, by applying low impedance paths from VCC and VPP/VCORE terminals to ground. A low-impedance output state allows discharging of residual voltage remaining on PC card filter capacitance, permitting the system (host and PC cards) to be powered up concurrently. The active low RESET input will program all outputs to 0 V. The TPS2228 power interface switch remains in the low-impedance output state until the signal is deasserted and new data is received. For the TPS2228, the input serial data cannot be latched during reset mode. CALCULATING JUNCTION TEMPERATURE The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures 10 through 14 using an initial temperature estimate about 50°C above ambient. Then calculate the power dissipation for each switch, using the formula: PD + r DS(on) LOGIC INPUTS AND OUTPUTS For the TPS2228, the serial interface consists of DATA, CLOCK, and LATCH signals. The data is clocked in on the positive leading edge of the clock (see Figure 2). The 11-bit (D0−D10) serial data word is loaded during the positive edge of the latch signal. The latch signal should occur before the next positive leading edge of the clock. The serial interface of the TPS2228 power interface switch is designed to be compatible with serial-interface PCMCIA controllers and current PCMCIA and Japan Electronic Industry Development Association (JEIDA) standards. For the TPS2221, the parallel interface consists of four bits (D3:D0). These four bits must be driven continuously to select the desired voltage outputs based on the input bit pattern. During power up, these inputs can be connected to an external pulldown resistor to ensure that the outputs are at zero volts, especially if the device driving these inputs is in a high impedance state while initializing. An overcurrent output (OC) is provided to indicate an overcurrent or over-temperature condition in any of the VCC and VPP/VCORE outputs as previously discussed. ESD PROTECTION All TPS2228/2221 power interface switch inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C, Method 3015. The VCC and VPP/ VCORE outputs can be exposed to potentially higher discharges from the external environment through the PC card connector. Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV. I2 17 TPS2228 TPS2221 www.ti.com SLVS419A − MAY 2002 REVISED SEPTEMBER 2002 Table 1. TPS2228 Power Interface Switch Control Logic TPS2228 Serial Interface xVPP/VCORE AVPP/VCORE CONTROL SIGNALS D8(SHDN) D0 D1 D9 OUTPUT V_AVPP/ VCORE 1 0 0 X 1 0 1 1 0 1 1 1 0 1 1 1 1 1 0 X BVPP/VCORE CONTROL SIGNALS D8(SHDN) D4 D5 D10 OUTPUT V_BVPP/ VCORE 0V 1 0 0 X 0V 0 3.3 V 1 0 1 0 3.3 V 1 5V 1 0 1 1 5V X Hi-Z 1 1 0 X Hi-Z 0 1.8 V 1 1 1 0 1.8 V 1 1 1.8 V 1 1 1 1 1.8 V X X Hi-Z 0 X X X Hi-Z xVCC AVCC CONTROL SIGNALS D8(SHDN) D3 D2 1 0 0 1 0 1 1 BVCC CONTROL SIGNALS OUTPUT V_AVCC V AVCC D6 D7 0V 1 0 0 0V 1 3.3 V 1 0 1 3.3 V 0 5V 1 1 0 5V 1 1 1 0V 1 1 1 0V 0 X X Hi-Z 0 X X Hi-Z Table 2. TPS2221 Control Logic TPAS2221 SINGLES D0 D1 D2 D3 0 0 0 0 0V 0V 0 0 0 1 Hi-Z Hi-Z 0 0 1 0 Hi-Z Hi-Z 0 0 1 1 Hi-Z Hi-Z 0 1 0 0 3.3 V 0V 0 1 0 1 3.3 V 3.3 V 0 1 1 0 3.3 V 5V 0 1 1 1 3.3 V 1.8 V 1 0 0 0 5V 0V 1 0 0 1 5V 3.3 V 1 0 1 0 5V 5V 1 0 1 1 5V 1.8 V 1 1 0 0 Hi-Z Hi-Z 1 1 0 1 3.3 V Hi-Z 1 1 1 0 5V Hi-Z 1 1 1 Hi-Z Hi-Z 1 NOTE: 18 OUTPUT V_BVCC V BVCC D8(SHDN) VCC VPP/CORE VCC = VPP/VCORE = Hi-Z indicates the device is in shutdown mode. TPS2228 TPS2221 www.ti.com SLVS419A − MAY 2002 REVISED SEPTEMBER 2002 TPS2228 AVCC VCC 0.1 µF† AVCC AVPP/VCORE 1.8 V 1.8 V 4.7 µF 0.1 µF 5V 1.8 V PC Card Connector A VPP1 0.1 µF† BVCC 0.1 µF 5V BVCC 3.3 V 0.1 µF† VPP2 3.3 V 4.7 µF 0.1 µF 3.3 V 3.3 V Controller DATA DATA CLOCK CLOCK LATCH LATCH RESET From PCI or System RST OC † VCC PC Card Connector B VPP1 BVPP/VCORE 5V VPP2 VCC 0.1 µF† 5V 4.7 µF VCC GPI/O Maximum recommended output capacitance for xVCC is 150 µF including card capacitance, and for xVPP is 10 µF, without OC glitch when switches are powered on. Figure 20. TPS2228 Dual Slot Application 19 TPS2228 TPS2221 www.ti.com SLVS419A − MAY 2002 REVISED SEPTEMBER 2002 TPS2221 VCC VCC 1.8 V 1.8 V 0.1 µF + 4.7 µF VCC1 VCC 0.1 µF 1.8 V VCC2 VPP1 PC Card Connector VPP2 VPP/VCORE 0.1 µF 5V 0.1 µF + 5V 4.7 µF 5V PCMCIA Controller 3.3 V 0.1 µF + 4.7 µF 3.3 V VD0 VCC_EN0 3.3 V VD1 VCC_EN1 VD2 VPP_EN0 VD3 VPP_EN1 OC GND To CPU SHDN Shutdown Signal From CPU Figure 21. TPS2221 Single Slot Application 20 CS PACKAGE OPTION ADDENDUM www.ti.com 11-Sep-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS2221PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS2221 TPS2221PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS2221 TPS2221PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS2221 TPS2228DB ACTIVE SSOP DB 30 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TPS2228 TPS2228PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS2228 TPS2228PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS2228 TPS2228PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS2228 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Sep-2016 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS2221PWPR HTSSOP PWP 14 2000 330.0 12.4 TPS2228PWPR HTSSOP PWP 20 2000 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 6.95 7.1 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2221PWPR HTSSOP PWP 14 2000 367.0 367.0 38.0 TPS2228PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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