TPS22917DBVR

Product Folder Order Now Support & Community Tools & Software Technical Documents TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 TPS22917 1 V–5.5-V, 2-A, 80-mΩ Ultra-Low Leakage Load Switch 1 Features 3 Description • • • The TPS22917 device is a small, single channel load switch utilizing a low leakage P-Channel MOSFET for minimum power loss. Advanced gate control design supports operating voltages as low as 1 V with minimal increase in ON-Resistance and power loss. 1 • • • • • Input Operating Voltage Range (VIN): 1 V to 5.5 V Maximum Continuous Current (IMAX): 2 A On-Resistance (RON): – 5 VIN = 80 mΩ (Typical) – 1.8 VIN = 120 mΩ (Typical) – 1 VIN = 220 mΩ (Typical) Ultra-Low Power Consumption: – ON State (IQ): 0.5 µA (Typical) – OFF State (ISD): 10 nA (Typical) Smart ON Pin Pull Down (RPD): – ON ≥ VIH (ION): 10 nA (Maximum) – ON ≤ VIL (RPD): 750 kΩ (Typical) Adjustable Turn ON Limits Inrush Current (tON): – 5-V tON = 100 μs at 72 mV/μs (CT = Open) – 5-V tON = 4000 μs at 2.3 mV/μs (CT = 1000 pF) Adjustable Output Discharge and Fall Time: – Optional QOD Resistance ≥ 150 Ω (Internal) Always-ON True Reverse Current Blocking (RCB): – Activation Current (IRCB): –500 mA (Typical) – Reverse Leakage (IIN,RCB): –1 µA (Maximum) 2 Applications • • • • Industrial Systems Set Top Box Blood Glucose Meters Electronic Point of Sale The Rise and Fall times can be independently adjusted with external components for system level optimizations. The timing capacitor (CT) and turn on time can be adjusted to manage inrush current without adding unnecessary system delays. The output discharge resistance (QOD) can be used to adjust the output fall time. Connect the QOD pin directly to the output for a fastest fall time or leave it open for the slowest fall time. The switch ON state is controlled by a digital input that can interface directly with low-voltage control signals. When power is first applied, a Smart Pull Down is used to keep the ON pin from floating until system sequencing is complete. Once the ON pin is deliberately driven high (≥VIH), the Smart Pull Down (RPD) is disconnected to prevent unnecessary power loss. The TPS22917 device is available in a small, leaded SOT-23 package (DBV) which allows visual inspection of solder joints. The device is characterized for operation over a temperature range of –40°C to +125°C. Device Information(1) PART NUMBER PACKAGE TPS22917 SOT-23 (6) BODY SIZE (NOM) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VIN VOUT CT + ± VIN RQOD CIN CL RL CT QOD H ON TPS22917 L Copyright © 2018, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. 7 Parameter Measurement Information ................ 12 8 Detailed Description ............................................ 13 7.1 Test Circuit and Timing Waveforms Diagrams ....... 12 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 14 8.4 Full-Time Reverse Current Blocking ...................... 15 8.5 Device Functional Modes........................................ 15 9 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Application ................................................. 16 10 Power Supply Recommendations ..................... 18 11 Layout................................................................... 19 11.1 Layout Guidelines ................................................. 19 11.2 Layout Example .................................................... 19 11.3 Thermal Considerations ........................................ 19 12 Device and Documentation Support ................. 20 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 13 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 2017) to Revision A • 2 Page Changed product status from Advanced Information to Production Data ............................................................................. 1 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 TPS22917 www.ti.com SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 5 Pin Configuration and Functions DBV Package 6-Pin SOT-23 Top View VIN 1 6 VOUT GND 2 5 QOD ON 3 4 CT Pin Functions PIN NO. NAME I/O DESCRIPTION 1 VIN I 2 GND — Switch input. 3 ON I Active high switch control input. Do not leave floating. 4 CT O Switch slew rate control. Connect capacitor from this pin to VIN to inrease output slew rate and turn on time. Can be left floating for fastest timing. Device ground. 5 QOD O Quick Output Discharge pin. This functionality can be enabled in one of three ways. • Placing an external resistor between VOUT and QOD • Tying QOD directly to VOUT and using the internal resistor value (RPD) • Disabling QOD by leaving pin floating See the Fall Time (tFALL) and Quick Output Discharge (QOD) section for more information. 6 VOUT O Switch output. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 3 TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VIN Input voltage –0.3 6 V VOUT Output voltage –0.3 6 V VON Enable voltage –0.3 6 V VQOD QOD pin voltage –0.3 6 V IMAX Maximum continuous switch current 2 A IPLS Maximum pulsed switch current, pulse < 300-µs, 2% duty cycle 2.5 A TJ,MAX Maximum junction temperature 125 °C TSTG Storage temperature 150 °C TLEAD Maximum Lead temperature (10-s soldering time) 300 °C (1) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance. 6.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) MIN MAX VIN Input voltage 1 5.5 UNIT V VOUT Output voltage 0 5.5 V VIH High-level input voltage, ON 1 5.5 V VIL Low-level input voltage, ON 0 0.35 V VQOD QOD Pin Voltage 0 5.5 V VCT Timing Capacitor Voltage Rating 7 V 6.4 Thermal Information TPS22917 Thermal Parameters (1) DBV (SOT-23) UNIT 6 PINS θJA Junction-to-ambient thermal resistance 183 °C/W θJCtop Junction-to-case (top) thermal resistance 152 °C/W θJB Junction-to-board thermal resistance 34 °C/W ψJT Junction-to-top characterization parameter 37 °C/W ψJB Junction-to-board characterization parameter 33 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 TPS22917 www.ti.com SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 6.5 Electrical Characteristics Unless otherwise noted, the specification in the following table applies for all variants over the entire recommended power supply voltage range of 1 V to 5.5 V. Typical Values are at 25°C. PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT INPUT SUPPLY(VIN) IQ,VIN ISD,VIN VIN Quiescent current VIN Shutdown current –40°C to +85°C VON ≥ VIH, VOUT = Open 0.5 –40°C to +125°C –40°C to +85°C VON ≤ VIL, VOUT = GND 10 –40°C to +105°C 1.0 µA 1.2 µA 100 nA 250 nA ON-RESISTANCE(RON) 25°C VIN = 5 V 80 120 –40°C to +105°C 130 –40°C to +125°C 140 25°C VIN = 3.6 V 90 140 –40°C to +105°C 150 160 25°C ON-Resistance IOUT = 200 mA VIN = 1.8 V 120 175 –40°C to +105°C 185 –40°C to +125°C 200 170 mΩ 220 –40°C to +85°C 265 –40°C to +105°C 280 –40°C to +125°C 300 25°C VIN = 1.0 V 150 –40°C to +85°C 25°C VIN = 1.2 V 110 –40°C to +85°C –40°C to +125°C RON 100 –40°C to +85°C 220 300 –40°C to +85°C 350 –40°C to +105°C 370 –40°C to +125°C 390 ENABLE PIN(ON) ION ON Pin leakage VON ≥ VIH –40°C to +125°C RPD Smart Pull Down Resistance VON ≤ VIL –40°C to +105°C 750 –10 10 nA kΩ REVERSE CURRENT BLOCKING(RCB) IRCB RCB Activation Current VON ≥ VIH, VOUT > VIN –40°C to +125°C -0.5 tRCB RCB Activation time VON ≥ VIH, VOUT > VIN + 200mV –40°C to +125°C 10 µs VRCB RCB Release Voltage VON ≥ VIH, VOUT > VIN –40°C to +125°C 25 mV IIN,RCB VIN Reverse Leakage Current 0 V ≤ VIN + VRCB ≤ VOUT ≤ 5.5 V –40°C to +105°C VON ≤ VIL –40°C to +105°C -1 –1 A µA QUICK OUTPUT DISCHARGE(QOD) QOD Output discharge resistance 150 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 Ω 5 TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com 6.6 Switching Characteristics Unless otherwise noted, the typical characteristics in the following table applies over the entire recommended power supply voltage range of 1 V to 5.5 V at 25°C with a load of CL = 1 µF, RL = 10 Ω PARAMETER TEST CONDITIONS VIN = 5.0 V VIN = 3.6 V tON Turn ON Time VIN = 1.8 V VIN = 1.2 V VIN = 1.0 V VIN = 5.0 V VIN = 3.6 V tR Output Rise Time VIN = 1.8 V VIN = 1.2 V VIN = 1.0 V VIN = 5.0 V VIN = 3.6 V SRON Turn ON Slew Rate (1) VIN = 1.8 V VIN = 1.2 V VIN = 1.0 V tOFF tFALL 6 CT ≥ 100 pF Output Fall Time (2) MIN TYP 100 4 UNIT µs µs/pF 120 µs CT ≥ 100 pF 3.8 µs/pF CT = Open 200 µs CT ≥ 100 pF 3.6 µs/pF CT = Open 300 µs CT ≥ 200 pF 3.4 µs/pF CT = Open 400 CT ≥ 400 pF µs 3 µs/pF CT = Open 55 µs CT ≥ 100 pF 1.8 µs/pF CT = Open 65 µs CT ≥ 100 pF 1.6 µs/pF CT = Open 100 µs CT ≥ 100 pF 1.2 µs/pF CT = Open 150 µs CT ≥ 200 pF 0.95 µs/pF CT = Open 200 µs CT ≥ 400 pF 0.6 µs/pF CT = Open 72 mV/µs CT ≥ 100 pF CT = Open CT ≥ 100 pF CT = Open CT ≥ 100 pF CT = Open CT ≥ 200 pF CT = Open CT ≥ 400 pF 2300 44 1900 14 1100 6.2 1000 3.9 1100 10 RL = Open MAX CT = Open Turn OFF Time RL = 10 Ω (1) (2) CT = Open (mV/µs)*pF mV/µs (mV/µs)*pF mV/µs (mV/µs)*pF mV/µs (mV/µs)*pF mV/µs (mV/µs)*pF µs CL = 1uF, RQOD = Short 22 µs CL = 10uF, RQOD = Short 3.8 ms CL = 10uF, RQOD = 100 Ω 5.9 ms CL = 220uF, RQOD = Short 72 ms SRON is the fastest Slew Rate during the turn on time (tON) Output may not discharge completely if QOD is not connected to VOUT. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 TPS22917 www.ti.com SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 6.7 Typical Characteristics 6.7.1 Typical Electrical Characteristics The typical characteristics curves in this section apply at 25°C unless otherwise noted. 10 0.8 105 qC 85 qC 25 qC 40 qC 8 0.75 0.7 6 IQ,VIN (nA) ISD,VIN (nA) 0.65 4 0.6 0.55 0.5 0.45 2 105 qC 85 qC 25 qC 40 qC 0.4 0.35 0 0.3 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 1 1.5 2 2.5 D002 VON ≤ VIL 3 3.5 VIN (V) 4 4.5 5.5 D001 VON ≥ VIH Figure 1. Shutdown Current (ISD) Figure 2. Quiescent Current (IQ) 260 275 1V 1.2 V 250 1.8 V 3.6 V 85qC 25qC 40qC 5V 240 225 220 QOD (:) 200 RON (m:) 5 175 150 125 200 180 100 160 75 50 -40 -20 0 20 40 60 Temperature (°C) 80 100 140 120 1 VON ≥ VIH 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 D007 VON ≤ VIL Figure 3. ON-Resistance (RON) Figure 4. Quick Output Discharge (QOD) 0.725 1050 0.7 1000 950 RPD (k:) 0.675 VON (V) 1.5 D004 0.65 0.625 900 850 800 0.6 750 0.575 700 VIH VIL 0.55 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 650 -50 0 D006 50 Temperature (qC) 100 150 D005 VON ≤ VIL –40°C to +105°C Figure 5. ON Pin Threshold Figure 6. ON Pin Smart Pull Down (RPD) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 7 TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com 6.7.2 Typical Switching Characteristics The typical data in this section apply at 25°C with a load of CL = 1 μF, RL = 10 Ω, and QOD shorted to VOUT unless otherwise noted. 600 105°C 85°C 25°C 40°C 550 500 450 tON (V) 400 350 300 250 200 150 100 50 0 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 D009 Figure 8. Turn On at 5 V (CT = Open) Figure 7. Turn On Time (CT = Open) 300 105 °C 85 °C 25 °C 40 °C 250 tRISE (Ps) 200 150 100 50 0 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 D010 Figure 10. Turn On at 3.6 V (CT = Open) Figure 9. Rise Time (CT = Open) 40 35 SRON (mV/Ps) 30 25 20 15 10 105 qC 85 qC 25 qC -40 qC 5 0 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 D008 Figure 11. Slew Rate (CT = Open) 8 Submit Documentation Feedback Figure 12. Turn On at 1 V (CT = Open) Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 TPS22917 www.ti.com SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 Typical Switching Characteristics (continued) The typical data in this section apply at 25°C with a load of CL = 1 μF, RL = 10 Ω, and QOD shorted to VOUT unless otherwise noted. 5000 105°C 85°C 25°C 40°C 4500 tON (Ps) 4000 3500 3000 2500 2000 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 D013 Figure 14. Turn On at 5 V (CT = 1000 pF) Figure 13. Turn On Time (CT = 1000 pF) 1800 1500 tRISE (Ps) 1200 900 600 105 qC 85 qC 25 qC 40 qC 300 0 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 D014 Figure 16. Turn On at 3.6 V (CT = 1000 pF) Figure 15. Rise Time (CT = 1000 pF) 6 105 °C 85 °C 25 °C 40 °C SRON (mV/Ps) 5 4 3 2 1 0 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 D012 Figure 17. Slow Slew Rate (CT = 1000 pF) Figure 18. Turn On at 1 V (CT = 1000 pF) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 9 TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com Typical Switching Characteristics (continued) The typical data in this section apply at 25°C with a load of CL = 1 μF, RL = 10 Ω, and QOD shorted to VOUT unless otherwise noted. 29000 34000 28000 32000 30000 26000 tON (Ps) tON (Ps) 27000 25000 28000 26000 24000 220 µF 47 µF 1 µF 23000 24000 3: 10 : 22000 22000 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 1 1.5 2 2.5 D022 RL = 10 Ω 3 3.5 VIN (V) 4 4.5 5 5.5 D023 CL = 47 µF Figure 19. Turn On vs Load Capacitance (CT = 10000 pF) Figure 20. Turn On vs Load Resistance (CT = 10000 pF) 12000 3600 3: 10 : Open 3300 3000 10000 tR (Ps) tR (Ps) 2700 8000 2400 2100 1800 6000 1500 1200 4000 220 µF 47 µF 1 µF 900 600 2000 1 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 D024 RL = 10 Ω 2.5 0.6 0.5 0.5 0.4 0.4 0.3 0.2 220 µF 47 µF 1 µF 3 3.5 VIN (V) 4 4.5 5 5.5 D025 Figure 22. Rise Time vs Load Resistance (CT = 10000 pF) 0.6 3: 10 : 0.3 0.2 0.1 0 0 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 1 D026 RL = 10 Ω 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 D027 CL = 47 µF Figure 23. Slew Rate vs Load Capacitance (CT = 10000 pF) 10 2 CL = 47 µF SRON (mV/Ps) SRON (mV/Ps) Figure 21. Rise Time vs Load Capacitance (CT = 10000 pF) 0.1 1.5 5.5 Figure 24. Slew Rate vs Load Resistance (CT = 10000 pF) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 TPS22917 www.ti.com SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 Typical Switching Characteristics (continued) The typical data in this section apply at 25°C with a load of CL = 1 μF, RL = 10 Ω, and QOD shorted to VOUT unless otherwise noted. RL = Open Figure 25. Turn Off at 3.6 V Figure 26. Turn Off at 3.6 V (Open Load) 45 25000 105°C 85°C 25°C 40°C 40 35 10 PF 220 PF 20000 30 tOFF (Ps) tOFF (Ps) CL = 47 μF 25 20 15000 10000 15 5000 10 5 0 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 0 VIN = 1 V to 5.5 V 200 300 VIN = 1 V to 5.5 V Figure 27. Turn Off Time 400 500 600 RQOD (:) 700 800 900 1000 D032 RL = Open Figure 28. Turn Off Time (Open Load) 26 550000 105 qC 85 qC 25 qC 40 qC 25 24 10 uF 220 uF 500000 450000 400000 350000 23 tFALL (Ps) tFALL (Ps) 100 D011 22 21 300000 250000 200000 150000 20 100000 19 50000 18 0 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 VIN = 1 V to 5.5 V 5 5.5 0 100 200 D028 VIN = 1 V to 5.5 V Figure 29. Fall Time 300 400 500 600 RQOD (:) 700 800 900 1000 D030 RL = Open Figure 30. Fall Time (Open Load) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 11 TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com 7 Parameter Measurement Information 7.1 Test Circuit and Timing Waveforms Diagrams VIN VOUT CT + VIN ± RQOD CIN CL RL CT QOD H ON TPS22917 L Copyright © 2018, Texas Instruments Incorporated (1) Rise and fall times of the control signal are 100 ns (2) Turn-off times and fall times are dependent on the time constant at the load. For TPS22917, the internal pull-down resistance QOD is enabled when the switch is disabled. The time constant is (RQOD + QOD || RL) × CL. Figure 31. Test Circuit Figure 32. Timing Waveforms 12 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 TPS22917 www.ti.com SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 8 Detailed Description 8.1 Overview The TPS22917 device is a 5.5-V, 2-A load switch in a 6-pin SOT-23 package. To reduce voltage drop for low voltage and high current rails, the device implements a low resistance P-channel MOSFET which reduces the drop out voltage across the device. The TPS22917 device has a configurable slew rate which helps reduce or eliminate power supply droop because of large inrush currents. Furthermore, the device features a QOD pin, which allows the configuration of the discharge rate of VOUT once the switch is disabled. During shutdown, the device has very low leakage currents, thereby reducing unnecessary leakages for downstream modules during standby. Integrated control logic, driver, charge pump, and output discharge FET eliminates the need for any external components which reduces solution size and bill of materials (BOM) count. 8.2 Functional Block Diagram IN Reverse Current Blocking ON Control Logic OUT Timing Control Driver CT QOD GND Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 13 TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com 8.3 Feature Description 8.3.1 On and Off Control The ON pin controls the state of the switch. The ON pin is compatible with standard GPIO logic threshold so it can be used in a wide variety of applications. When power is first applied to VIN, a Smart Pull Down is used to keep the ON pin from floating until system sequencing is complete. Once the ON pin is deliberately driven high (≥VIH), the Smart Pull Down is disconnected to prevent unnecessary power loss. Table 1 shown then the ON Pin Smart Pull Down is active. Table 1. Smart-ON Pull Down VON Pull Down ≤ VIL Connected ≥ VIH Disconnected 8.3.2 Turn On Time (tON) and Adjustable Slew Rate (CT) A capacitor to VIN on the CT pin sets the slew rate of VOUT. The CT capacitor voltage will ramp until shortly after the switch is turned on and VOUT becomes stable. Leaving the CT pin open will result in the highest slew rate and fastest turn on time. These values can be found in the Switching Characteristics Table. For slower slew rates the required CT capacitor can be found using Equation 1: CT = (Slew Rate) ÷ SRON where • • • Slew Rate = Desired slew rate (mV/us) CT = The capacitance value on the CT pin (pF) SRON = Slew Rate Constant from Table ((mV/µs) × pF) (1) The total turn on time has a direct correlation to the output slew rate. The fastest turn on times (tON), with CT pin open, can be found in the Switching Characteristics. For slower slew rates, the resulting turn on time can be found with Equation 2: Turn On time = CT × tON where • • • Turn On Time = Total Time from Enable until VOUT rises to 90% of VIN (µs) CT = The capacitance value on the CT pin (pF) tON = Turn On Time Constant (µs/pF) (2) 8.3.3 Fall Time (tFALL) and Quick Output Discharge (QOD) The TPS22917 device includes a QOD pin that can be configured in one of three ways: • QOD pin shorted to VOUT pin. Using this method, the discharge rate after the switch becomes disabled is controlled with the value of the internal resistance QOD. • QOD pin connected to VOUT pin using an external resistor RQOD. After the switch becomes disabled, the discharge rate is controlled by the value of the total discharge resistance. To adjust the total discharge resistance, Equation 3 can be used: RDIS = QOD + RQOD Where: • • • • RDIS = Total output discharge resistance (Ω) QOD = Internal pulldown resistance (Ω) RQOD = External resistance placed between the VOUT and QOD pins (Ω) (3) QOD pin is unused and left floating. Using this method, there will be no quick output discharge functionality, and the output will remain floating after the switch is disabled. The fall times of the device depend on many factors including the total discharge resistance (RDIS) and the output capacitance (CL). To calculate the approximate fall time of VOUT use Equation 4. tFALL = 2.2 × (RDIS || RL) × CL 14 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 TPS22917 www.ti.com SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 Where: • • • • tFALL = Output Fall Time from 90% to 10% (μs) RDIS = Total QOD + RQOD Resistance (Ω) RL = Output Load Resistance (Ω) CL = Output Load Capacitance (μF) (4) 8.3.3.1 QOD when System Power is Removed The adjustable QOD can be used to control the power down sequencing of a system even when the system power supply is removed. When the power is removed, the input capacitor discharges at VIN. Past a certain VIN level, the strength of the RPD will be reduced. If there is still remaining charge on the output capacitor, this will result in longer fall times. For further information regarding this condition, see the Setting Fall Time for Shutdown Power Sequencing section. 8.4 Full-Time Reverse Current Blocking In a scenario where the device is enabled and VOUT is greater than VIN there is potential for reverse current to flow through the pass FET or the body diode. When the reverse current threshold (IRCB) is exceeded, the switch is disabled within tRCB. The Switch will remain off and block reverse current as long as the reverse voltage condition exists. Once VOUT has dropped below the VRCB release threshold the device will turn back on with slew rate control. 8.5 Device Functional Modes Table 2 describes the connection of the VOUT pin depending on the state of the ON pin as well as the various QOD pin configurations. Table 2. VOUT Connection ON QOD CONFIGURATION TPS22917 VOUT L QOD pin connected to VOUT with RQOD GND (via QOD + RQOD) L QOD pin tied to VOUT directly GND (via QOD) L QOD pin left open Floating H N/A VIN Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 15 TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information This section highlights some of the design considerations when implementing this device in various applications. 9.2 Typical Application This typical application demonstrates how the TPS22917 device can be used to power downstream modules. VIN VOUT CT + RQOD VIN CIN ± RL CL CT QOD ON H TPS22917 L Copyright © 2018, Texas Instruments Incorporated Figure 33. Typical Application Schematic 9.2.1 Design Requirements For this design example, use the values listed in Table 3 as the design parameters: Table 3. Design Parameters 16 DESIGN PARAMETER EXAMPLE VALUE Input Voltage (VIN ) 3.6 V Load Current / Resistance (RL) 1 kΩ Load Capacitance (CL) 47 µF Minimum Fall Time (tF) 40 ms Maximum Inrush Current (IRUSH) 150 mA Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 TPS22917 www.ti.com SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 9.2.2 Detailed Design Procedure 9.2.2.1 Limiting Inrush Current Use Equation 5 to find the maximum slew rate value to limit inrush current for a given capacitance: (Slew Rate) = IRUSH ÷ CL where • • • IINRUSH = maximum acceptable inrush current (mA) CL = capacitance on VOUT (μF) Slew Rate = Output Slew Rate during turn on (mV/μs) (5) Once the required slew rate shown in Equation 1 can be used to find the minimum CT capacitance CT = SRON ÷ (Slew Rate) CT = 1900 ÷ 3.2 = 594 pF (6) (7) To ensure an inrush current of less than 150 mA, choose a CT value greater than 594 pF. An appropriate value should be placed on such that the IMAX and IPLS specifications of the device are not violated. 9.2.2.2 Application Curves Figure 34. Inrush Current (CT = 470 pF) Figure 35. Inrush Current (CT = 1000 pF) 9.2.2.3 Setting Fall Time for Shutdown Power Sequencing Microcontrollers and processors often have a specific shutdown sequence in which power must be removed. Using the adjustable Quick Output Discharge function of the TPS22917, adding a load switch to each power rail can be used to manage the power down sequencing. To determine the QOD values for each load switch, first confirm the power down order of the device you wish to power sequence. Be sure to check if there are voltage or timing margins that must be maintained during power down. Once the required fall time is determined, the maximum external discharge resistance (RDIS) value can be found using Equation 4: tFALL = 2.2 × (RDIS || RL) × CL RDIS = 630 Ω (8) (9) Equation 3 can then be used to calculate the RQOD resistance needed to acheive a particular discharge value: RDIS = QOD + RQOD RQOD = 480 Ω (10) (11) To ensure a fall time greater than, choose an RQOD value greater than 480 Ω. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 17 TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com 9.2.2.4 Application Curves Figure 36. Fall Time (RQOD = 100 Ω) Figure 37. Fall Time (RQOD = 1 kΩ) 10 Power Supply Recommendations The device is designed to operate with a VIN range of 1 V to 5.5 V. The VIN power supply must be well regulated and placed as close to the device terminal as possible. The power supply must be able to withstand all transient load current steps. In most situations, using an input capacitance (CIN) of 1 μF is sufficient to prevent the supply voltage from dipping when the switch is turned on. In cases where the power supply is slow to respond to a large transient current or large load current step, additional bulk capacitance may be required on the input. 18 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 TPS22917 www.ti.com SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 11 Layout 11.1 Layout Guidelines For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects. 11.2 Layout Example Figure 38. Recommended Board Layout 11.3 Thermal Considerations The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use Equation 12: TJ(MAX) - TA PD(MAX) = qJA where • • • • PD(MAX) = maximum allowable power dissipation TJ(MAX) = maximum allowable junction temperature (125°C for the TPS22917) TA = ambient temperature of the device θJA = junction to air thermal impedance. Refer to the table. This parameter is highly dependent upon board layout. (12) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 19 TPS22917 SLVSDW8A – SEPTEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: TPS22917 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS22917DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1IAF TPS22917DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1IAF (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of