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TPS22949, TPS22949A
SLVS908D – FEBRUARY 2009 – REVISED JUNE 2015
TPS22949x Current-Limited Load Switch With Low Noise Regulation Capability
1 Features
3 Description
•
The TPS22949 and TPS22949A are devices that
provide protection to systems and loads in highcurrent conditions. The device contains a 500-mΩ
current-limited P-channel MOSFET that can operate
over an input voltage range of 1.62 V to 4.5 V as well
as a low-dropout (LDO) regulator with a fixed output
voltage of 1.8 V.
1
•
•
•
•
•
Integrated Current Limiter
– Input Voltage Range: 1.62 V to 4.5 V
– Low ON-Resistance
– rON = 300-mΩ at VIN = 4.5 V
– rON = 350-mΩ at VIN = 3.3 V
– rON = 400-mΩ at VIN = 2.5 V
– rON = 600-mΩ at VIN = 1.8 V
– Integrated 100-mA Minimum Current Limit
– Undervoltage Lockout
– Fast-Current Limit Response Time
– Integrated Fault Blanking and Auto Restart
Stable Without Current Limiter Output Capacitor
(TPS22949A Only)
Integrated Low-Noise RF LDO
– Input Voltage Range: 1.62 V to 4.5 V
– Low Noise: 50 μVrms (10 Hz to 100 kHz)
– 80-dB VIN PSRR (10 Hz to 10 kHz)
– Fast Start-Up Time: 130 μs
– Low Dropout 100 mV at Iload =100 mA
– Integrated Output Discharge
– Stable With 2.2-μF Output Capacitor
1.8-V Compatible Control Input Threshold
ESD Performance Tested Per JESD 22
– 3500 V Human Body Model
(A114-B, Class II)
– 1000 V Charged Device Model
(C101)
Tiny 8-Terminal YZP Package (1.9 mm × 0.9 mm,
0.5-mm Pitch, 0.5-mm Height) and WSON-8
(DRG) 3.0 mm × 3.0 mm
The switch is controlled by an on/off input (EN1),
which can interface directly with low-voltage control
signals. When the switch current reaches the
maximum limit, the TPS22949/TPS22949A operates
in a constant-current mode to prohibit excessive
currents from causing damage. If the constant current
condition persists after 12 ms, these devices shut off
the switch and pull the fault signal pin (OC) low. The
TPS22949/TPS22949A has an auto-restart feature
that turns the switch on again after 70 ms if the EN1
pin is still active.
The output of the current limiter is internally
connected to an RF low-dropout (LDO) regulator that
offers good AC performance with very low ground
current, good power supply rejection ratio (PSRR),
low noise, fast start-up, and excellent line and load
transient response. The output of the regulator is
stable with ceramic capacitors. This LDO uses a
precision voltage reference and feedback loop to
achieve overall accuracy of 2% over all load, line,
process, and temperature variations.
Device Information(1)
PART NUMBER
TPS22949
TPS22949A
Fingerprint Module Protection
Portable Consumer Electronics
Smart Phones
Notebooks
Control Access Systems
BODY SIZE (NOM)
DSBGA (8)
1.90 mm × 0.90 mm
DSBGA (8)
1.90 mm × 0.90 mm
WSON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
PACKAGE
Typical Application Schematic
TPS22949
TPS22949A
VIN
VIN
VOUTCL
VOUTCL
EN1
CIN
CCL
EN2
V+
V+
VOUTLDO
(1.8 V, 100 mA)
VOUTLDO
CLDO
GND
OC
OC
RPU
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS22949, TPS22949A
SLVS908D – FEBRUARY 2009 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
5
5
5
5
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Current Limiter Electrical Characteristics..................
Low-Noise LDO Regulator Electrical Characteristics
Current Limiter Switching Characteristics .................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 19
9.3 System Examples ................................................... 21
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 Device and Documentation Support ................. 23
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
Changes from Revision C (January 2010) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Dissipation Ratings table........................................................................................................................................... 5
2
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Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TPS22949 TPS22949A
TPS22949, TPS22949A
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SLVS908D – FEBRUARY 2009 – REVISED JUNE 2015
5 Description (continued)
The TPS22949A integrates additional internal circuitry that increases the current limit of the switch during the
power-up sequence. This feature allows the TPS22949A to operate without a storage capacitor at the input of
the LDO.
The TPS22949 and TPS22949A are available in a space-saving 8-terminal WCSP (YZP) or in an 8-pin WSON
package (DRG). Both devices are characterized for operation over the free-air temperature range of –40°C to
85°C.
Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TPS22949 TPS22949A
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TPS22949, TPS22949A
SLVS908D – FEBRUARY 2009 – REVISED JUNE 2015
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6 Pin Configuration and Functions
YZP Package
8-Pin DSBGA
Top View
D
D
C
C
B
B
A
A
2 1
Laser Marking View
1 2
Bump View
DRG Package
8-Pin WSON
Top View
EN2
1
GND
2
VIN
3
EN1
4
Exposed
Thermal
Die Pad
on
Underside
8
V+
7
VOUTLDO
6
VOUTCL
5
OC
The exposed center pad, if used, must be connected as a secondary GND or left electrically open.
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DSBGA
WSON
EN1
D2
4
I
Power switch control input. Active high. Do not leave floating.
EN2
A2
1
I
LDO control input. Active high. Do not leave floating.
GND
B2
2
—
Ground
OC
D1
5
O
Overcurrent output flag. Active low, open-drain output that indicates an overcurrent, supply
undervoltage, or overtemperature state.
V+
A1
8
I
Supply voltage
VIN
C2
3
I
Supply input. Input to the power switch; bypass this input with a ceramic capacitor to ground.
VOUTCL
C1
6
O
Switch output. Output of the power switch
VOUTLDO
B1
7
O
LDO output. Output of the RF LDO fixed to 1.8 V (1).
(1)
Output voltages from 0.9 V to 3.6 V in 50-mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
YZP Package Pin Assignments
D
4
EN1
OC
C
VIN
VOUTCL
B
GND
VOUTLDO
A
EN2
V+
2
1
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SLVS908D – FEBRUARY 2009 – REVISED JUNE 2015
7 Specifications
7.1 Absolute Maximum Ratings (1)
VI
Input voltage
VOUTCL
Current limiter output voltage
TJ
Operating junction temperature
Tstg
Storage temperature
(1)
VIN, EN1, EN2, V+
MIN
MAX
–0.3
6
UNIT
V
VIN + 0.3
V
–40
105
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±3500
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VIN
Input voltage (1)
VOUTCL
Current limiter output voltage
V+
Supply voltage
2.6
CIN
Input capacitor
1
TA
Ambient free-air temperature
NOM
MAX
1.62
UNIT
4.5
V
VIN
V
5.5
V
μF
–40
85
°C
1.4
5.5
V
0.4
V
CONTROL INPUTS (EN1, EN2)
VIH
High-level input voltage
VIL
Low-level input voltage
(1)
See the Application and Implementation.
7.4 Thermal Information
TPS22949x
THERMAL METRIC
(1)
YZP [DSBGA]
DRG [WSON]
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
105.8
51.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.6
65.4
°C/W
RθJB
Junction-to-board thermal resistance
10.8
25.9
°C/W
ψJT
Junction-to-top characterization parameter
3.1
1.3
°C/W
ψJB
Junction-to-board characterization parameter
10.8
26
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
6.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TPS22949 TPS22949A
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7.5 Electrical Characteristics
TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
IGND
Ground pin current
EN1 and EN2 = V+
V+ = VOUT + 1.4 V or 2.5, whichever > 5.5 V,
VOUTCL ≥ VOUTLDO + 0.5 V
IOUT2 = 0 mA
85
110
μA
IGNDCL
Ground pin current (current
limiter only)
EN1 = V+ and EN2 = 0
40
75
μA
IGND(OFF)
OFF-state ground pin current
EN1 and EN2 = GND,
VOUTCL = Open,
VOUTLDO = Open
IEN2
Enable pin 2 current, enabled
VEN2 = V+ =5.5 V, VIN = 4.5 V
1
μA
IEN1
Enable pin 1 current, enabled
VEN1 = V+ = 5.5 V, VIN = 4.5 V
1
μA
Shutdown threshold (TA)
Thermal
shutdown
Return from shutdown
Hysteresis
(1)
VIN = V+ = 3.3 V
2
VIN = 3.6 V, V+ = 5.5 V
6
TPS22949
122
TPS22949A
135
TPS22949
112
TPS22949A
120
TPS22949
10
TPS22949A
10
μA
°C
Typical values are at VIN = 3.3 V and TA = 25°C.
7.6 Current Limiter Electrical Characteristics
over operating free-air temperature range, V+ = 3.3 V, EN1 = V+, EN2 = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIN = 4.5 V
VIN = 3.3 V
rON
ON-state resistance
IOUT = 20 mA
VIN = 2.5 V
VIN = 1.8 V
ILIM
ILIM
(INRUSH)
UVLO-CL
TA
YZP PACKAGE
MIN
25°C
0.4
0.4
Full
0.6
Full
Full
Power-ON inrush
current limit
(TPS22949A only)
VOUT = 3 V
VIN = 3.3 V
Full
Undervoltage
shutdown
VIN increasing
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VIN = 1.8 V
0.45
100
150
0.7
0.5
0.7
Full
1
0.8
1.1
150
200
1.2
100
mA
750
1.59
Ω
1.1
1.0
750
1.49
0.8
0.9
0.9
200
0.7
0.8
1.1
1.39
VIN = 4.5 V
0.5
UNIT
0.6
0.6
30
ISINK = 10 mA
0.4
1.0
0.7
Full
VIN = 3.3 V
MAX
0.8
25°C
VOUT = 3 V
TYP
0.7
25°C
25°C
MIN
0.5
0.35
Undervoltage
shutdown hysteresis
6
0.3
Full
Current limit
OC output logic low
voltage
MAX
Full
25°C
VIN = 1.62
V
DRG PACKAGE
TYP
1.39
1.49
1.59
30
V
mV
0.1
0.3
0.1
0.3
0.2
0.4
0.2
0.4
V
Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TPS22949 TPS22949A
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SLVS908D – FEBRUARY 2009 – REVISED JUNE 2015
7.7 Low-Noise LDO Regulator Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOUTLDO
Output voltage
ΔVOUTLDO/ΔVIN
ΔVOUTLDO/ΔV+
ΔVOUTLDO/ΔIOUT2
VDO
VIN PSRR
V+ PSRR
TEST CONDITIONS
1.76
VIN line regulation
VIN = VOUTLDO + 0.5 V to 4.5 V, IOUT = 1 mA
VIN line transient
ΔVIN = 400 mV, tr = tf = 1 μs
V+ line regulation
VIN = VOUTLDO + 1.4 V or 2.5 V, whichever is > 5.5 V,
IOUT = 1 mA
V+ line transient
ΔVIN = 600 mV, tr = tf = 1 μs
Load regulation
IOUT2 = 0 to 100 mA (no load to full load)
Load transient
Dropout voltage
(VDO = VIN – VOUTLDO)
Power supply
rejection ratio
Power supply
rejection ratio
MAX
1.8
1.84
UNIT
V
±0.1
%/V
±2
mV
±0.1
%/V
±5
mV
%/V
IOUT2 = 0 to 100 mA, tr = tf = 1 μs
±35
mV
VIN = VOUTLDO(NOM) – 0.1 V, V+ – VOUTLDO(NOM) = 1.4 V,
IOUT = 100 mA
110
VOUTCL – VOUTLDO ≥ 0.5 V,
V+ = VOUTLDO + 1.4 V,
IOUT = 100 mA,
VOUTCL – VOUTLDO ≥ 0.5 V,
V+ = VOUTLDO + 1.4 V,
IOUT = 100 mA,
f = 10 Hz
75
f = 100 Hz
75
f = 1 kHz
80
f = 10 kHz
80
f = 100 kHz
85
f = 1 MHz
85
f = 10 Hz
80
f = 100 Hz
80
f = 1 kHz
75
f = 10 kHz
65
f = 100 kHz
55
f = 1 MHz
35
BW = 10 Hz to 100 kHz
50
VN
Output noise voltage
tSTR
Start-up time
VOUT = 95%,
VOUT(NOM), IOUT = 100 mA, COUT = 2.2 μF
Undervoltage lockout
V+ rising
Hysteresis
V+ falling
(1)
TYP
±0.01
V+ ≥2.5 V,
VOUTLDO = VOUTCL + 0.5 V
UVLO-V+
MIN
(1)
2.3
200
mV
dB
dB
μVrms
130
250
2.45
2.55
150
μs
V
mV
LDO output voltage is fixed at 1.8 V. However, output voltages from 0.9 V to 3.6 V in 50-mV increments are available through the use of
innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability.
7.8 Current Limiter Switching Characteristics
VIN = 3.3 V, TA = 25°C, RL = 500 Ω, CL = 0.1 μF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tON
Turnon time
RL = 500 Ω, CCL = 0.1 μF
95
μs
tOFF
Turnoff time
RL = 500 Ω, CCL = 0.1 μF
2
μs
tr
VOUT rise time
RL = 500 Ω, CCL = 0.1 μF
25
μs
tf
VOUT fall time
RL = 500 Ω, CCL = 0.1 μF
tBLANK
Overcurrent blanking time
tRSTRT
Auto-restart time
tINRUSH
Power-ON inrush current limit time
(TPS22949A only)
Short-circuit response time
RL = 500 Ω, CCL = 0.1 μF
VIN = VEN1 = 3.3 V, moderate overcurrent condition
VIN = VEN1 = 3.3 V, hard short
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μs
10
6
12
18
ms
40
80
120
ms
150
11
5
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μs
μs
7
TPS22949, TPS22949A
SLVS908D – FEBRUARY 2009 – REVISED JUNE 2015
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7.9 Typical Characteristics
0.9
V+ = 2.5 V
V+ = 3.3 V
V+ = 4.5 V
0.8
ON-State Resistance, rON (W)
ON-State Resistance, rON (W)
0.9
0.7
0.6
0.5
0.8
0.7
0.6
0.5
VIN = 1.8 V
VIN = 3.6 V
VIN = 4.5 V
VIN = 5 V
0.4
0.4
0.3
0.3
1.5
2.5
3.5
4.5
–40
5.5
–10
Input Voltage, VIN (V)
55
25
85
Temperature, TA (°C)
TA = 25°C
V+ = 5.5 V
Figure 1. ON-State Resistance vs Input Voltage
Figure 2. ON-State Resistance vs Temperature,
–30
–85
–86
–50
–87
–70
–89
IGND (mA)
IGND (mA)
–88
–90
–91
–90
–110
–92
–93
–130
–94
–95
2.0
–150
2.5
3.0
3.5
4.0
4.5
2.2
5.0
2.4
V+ = 5.5 V
3.0
3.2
3.4
Figure 4. Ground Pin Current vs Input Voltage
–80
-38.0
–85
-38.5
-39.0
–90
-39.5
–95
–100
VIN = 3.3 V
VIN = 4.5 V
–105
–110
IGND (mA)
IGND (mA)
2.8
V+ = 3.3 V
Figure 3. Ground Pin Current vs Input Voltage
-40.0
-40.5
-41.0
-41.5
–115
-42.0
–120
-42.5
–40
–10
25
55
85
1.5
2.0
V+ = 5.5 V
3.0
3.5
4.0
4.5
5.0
V+ = 5.5 V
Figure 5. Ground Pin Current vs Temperature
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2.5
Input Voltage, VIN (V)
Temperature, TA (°C)
8
2.6
Input Voltage, VIN (V)
Input Voltage, VIN (V)
Figure 6. Ground Pin Current vs Input Voltage
(Current Limiter Only)
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Typical Characteristics (continued)
0
-3.00
-5
-3.10
-3.15
IGND(OFF) (nA)
-15
IGND (mA)
-3.05
VIN = 1.8 V
VIN = 3.3 V
VIN = 4.5 V
-10
-20
-25
-30
-3.20
-3.25
-3.30
-35
-3.35
-40
-3.40
-45
-3.45
-3.50
-50
–40
–10
55
25
85
1.5
2.0
2.5
3.5
4.0
4.5
5.0
V+ = 5.5 V
V+ = 5.5 V
Figure 8. OFF-State Ground Current vs Input Voltage
Figure 7. Ground Pin Current vs Temperature
(Current Limiter Only)
0
0
-100
-0.5
-200
-1.0
-300
VIN = 3.6 V
VIN = 4.5 V
-1.5
IGND(OFF) (mA)
IGND(OFF) (nA)
3.0
Input Voltage, VIN (V)
Temperature, TA (°C)
-400
-500
-600
-700
-2.0
-2.5
-3.0
-3.5
-800
-4.0
-900
-4.5
-1000
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
–40
6.0
–10
Input Voltage, VIN (V)
55
25
85
Temperature, TA (°C)
VIN = V+
Figure 9. OFF-State Ground Current vs Input Voltage
1.795
0.16
IOUT = 0 mA
IOUT = 1 mA
IOUT = 100 mA
1.785
1.780
1.775
1.770
1.765
LDO Dropout Voltage, VLDO (V)
0.18
1.790
TA = –40°C
TA = –10°C
TA = 25°C
TA = 55°C
TA = 85°C
0.14
0.12
0.10
0.08
0.06
0.04
0.02
1
0.
00
2
.0
.0
4
.0
3
-0
-0
-0
5
.0
-0
.0
6
7
.0
-0
-0
.0
.0
8
LDO Output Current, IOUTLDO (A)
Temperature, TA (°C)
Figure 11. Output Voltage vs Temperature
-0
85
-0
55
25
.0
9
–10
-0
–40
.1
0
0.00
1.760
-0
VOUTLDO (V)
Figure 10. OFF-State Ground Current vs Temperature
1.800
Figure 12. LDO Dropout Voltage vs Output Current
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Typical Characteristics (continued)
1.82
1.797
1.796
1.80
VOUTLDO (V)
VOUTLDO (V)
1.795
TA = –40°C
TA = –10°C
TA = 25°C
TA = 55°C
TA = 85°C
1.794
1.793
1.78
1.76
TA = –40°C
TA = –10°C
TA = 25°C
TA = 55°C
TA = 85°C
1.74
1.792
1.791
2.0
2.5
3.0
3.5
4.0
4.5
1.72
5.0
2.0
2.5
3.0
3.5
4.0
Input Voltage, VIN (V)
Input Voltage, VIN (V)
IOUT = 0 mA
4.5
5.0
IOUT = 100 mA
Figure 13. Input Voltage, VIN, Line Regulation
Figure 14. Input Voltage, VIN, Line Regulation
1.779
1.797
1.796
1.778
VOUTLDO (V)
VOUTLDO (V)
1.795
TA = –40°C
TA = –10°C
TA = 25°C
TA = 55°C
TA = 85°C
1.794
1.793
1.777
TA = –40°C
TA = –10°C
TA = 25°C
TA = 55°C
TA = 85°C
1.776
1.775
1.792
1.791
1.774
3.0
3.5
4.5
4.0
5.0
5.5
3.0
6.0
3.5
4.5
4.0
Input Voltage, V+ (V)
5.0
5.5
6.0
Input Voltage, V+ (V)
IOUT = 0 mA
IOUT = 100 mA
Figure 15. Input Voltage, V+, Line Regulation
Figure 16. Input Voltage, V+, Line Regulation
1.797
1.800
1.796
1.795
1.795
VOUTLDO (V)
1.785
TA = –40°C
TA = –10°C
TA = 25°C
TA = 55°C
TA = 85°C
1.780
1.775
TA = –40°C
TA = –10°C
TA = 25°C
TA = 55°C
TA = 85°C
1.793
1.792
1.791
IOUTLDO (A)
1
00
0.
2
.0
3
.0
-0
-0
4
.0
.0
-0
5
-0
.0
-0
7
06
.0
-0
IOUTLDO (A)
IOUT = 100 mA
IOUT = 10 mA
Figure 17. Load Regulation
10
-0
.
8
9
.0
0
.0
-0
-0
.1
1
00
0.
2
.0
3
.0
-0
-0
4
.0
.0
-0
-0
5
.0
-0
7
06
.0
-0
.
8
-0
.0
.0
-0
-0
.1
9
1.790
0
1.770
-0
1.794
-0
VOUTLDO (V)
1.790
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Figure 18. Load Regulation Under Light Loads
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Load Transient Signal,LDO Output Response
50 mV/DIV
Load Transient Signal,LDO Output Response
50 mV/DIV
Typical Characteristics (continued)
Load Transient Signal
LDO Output Response
Load Transient Signal
LDO Output Response
100 µs/DIV
100 µs/DIV
Figure 19. Load Transient
Figure 20. VIN Load Transient
VOUTLDO
VIN
1 mV/div
VIN = 2.1 V to 2.5 V
VOUT = 1.8 V
V+ = 3.2 V
IOUTLDO = 100 mA
200 mV/div
Output Spectral Noise Density ( Vrms/RTHz)
1.41E-6
1.21E-6
1.01E-6
810E-9
610E-9
410E-9
210E-9
10E-9
100
1000
100 µs/DIV
10000
100000
Frequency (Hz)
Figure 21. V+ Load Transient
Figure 22. Output Spectral Noise Density vs Frequency
0
-10
-20
-30
-40
-50
PSRR
PSRR (dB)
-30
IOUTLDO = 1 mA
IOUTLDO = 100 mA
-10
IOUTLDO = 0 mA
IOUTLDO = 50 mA
IOUTLDO = 100 mA
-50
-60
-70
-70
-90
-80
-90
-110
10
100
1000
10000
100000
Frequency (Hz)
Figure 23. PSRR vs Frequency
1000000
-100
10
0
100
1000
10000
100000
Frequency (Hz)
1000000
Figure 24. V+ PSRR vs Frequency
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Typical Characteristics (continued)
80
180
Tfall
160
70
TON
140
trise /tfall (µs)
tON /tOFF (µs)
60
120
100
CL = 0.1 µF, RL = 330 Ω
ILOAD = 10 mA
VIN = V+ = 3.3 V
80
60
CL = 0.1 µF
RL = 330 Ω
ILOAD = 10 mA
50
40
30
40
20
TOFF
Trise
20
-50
-25
0
25
50
Temperature (°C)
75
10
100
-50
-25
Figure 25. tON/tOFF vs Temperature
25
50
Temperature (°C)
75
100
Figure 26. trise/tfall vs Temperature
2.0
5.5
5.0
1.8
Vin = 1.8VVin = 2.5VVin = 3.0VVin = 3.3VVin = 4.5VVin = 5.0V-
4.0
3.5
3.0
1.6
1.4
1.2
LDO_out (V)
4.5
Vout (V)
0
2.5
2.0
1.0
V+ = 2.5VV+ = 3VV+ = 3.3VV + = 3.6VV+ = 4.5VV+ = 5VV + = 5.5V-
0.8
0.6
1.5
1.0
0.4
0.5
0.2
0.0
0.0
-0.5
-0.2
0.0
0.5
1.0
1.5
2.0
0.0
0.5
Input Voltage, EN1 (V)
1.0
1.5
2.0
Input Voltage, EN2 (V)
V+ = 5.5 V
VIN = 3.3 V
Figure 27. EN1 (Current Limiter) Input Thresholds
Figure 28. EN2 (LDO) Input Thresholds
V DRV(*)
2V/DIV
V DRV(A)
2 V/DIV
V OUTCL
V OUTCL
2V/DIV
2 V/DIV
I OUTCL
100 mA/DIV
I OUTCL
100mA/DIV
V OC
2 V/DIV
V OC
2V/DIV
2 ms/DIV
VDRV signal forces the device to go into overcurrent mode.
Figure 29. tBLANK Response
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20 ms/DIV
VDRV signal forces the device to go into overcurrent mode.
Figure 30. tRESTART Response
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Typical Characteristics (continued)
COUTCL = 0.1uF
ROUTCL = 500-W
VIN = 3.3 V
IOUTCL
1 mA/DIV
IOUTCL 1mA/DIV
COUTCL = 0.1uF
ROUTCL = 500-!
VIN = 3.3-V
VEN1 1V/DIV
VEN1
1V/DIV
50uS/DIV
50 us/DIV
Figure 32. Current Limiter tOFF Response
Figure 31. Current Limiter tON Response
VIN
2V/DIV
VIN
2V/DIV
CIN = 10uF
COUTCL = 1uF
IOUTCL
400mA/DIV
IOUTLDO
400mA/DIV
VOUTLDO
2V/DIV
VOUTCL
2V/DIV
10uS/DIV
Figure 33. Short-Circuit Response Time
(VOUTCL Shorted to GND)
10uS/DIV
Figure 34. Short-Circuit Response Time
(VOUTLDO Shorted to GND)
VIN/VEN2
1V/DIV
VIN/VEN1
1V/DIV
IOUTCL
100mA/DIV
CIN = 10uF
COUTCL = 1uF
IOUTLDO
100mA/DIV
20uS/DIV
Figure 35. Short-Circuit Response Time (Switch Power Up
to Hard Short) (TPS22949)
20uS/DIV
Figure 36. Short-Circuit Response Time (LDO Power Up to
Hard Short) (TPS22949)
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Typical Characteristics (continued)
CIN = 10uF
COUTCL = 1uF
VIN
1V/DIV
V IN
1V/DIV
IOUTCL
200mA/DIV
IOUTLDO
200mA/DIV
CIN = 10uF
COUTCL = 0.1uF
CIN = 10uF
COUTCL = 0.1uF
20uS/DIV
20uS/DIV
Figure 37. Short-Circuit Response Time (Switch Power Up
to Hard Short) (TPS22949A)
VIN
2V/DIV
VIN
2V/DIV
CIN = 10uF
COUTCL = 1uF
VEN1
2V/DIV
IOUTCL
100mA/DIV
VOUTLDO
(Shorted to
Ground)
20uS/DIV
Figure 39. Current Limit Response Time (Current Limiter)
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VEN2
2V/DIV
IOUTLDO
100mA/DIV
VOUTCL
(Shorted to
Ground)
14
Figure 38. Short-Circuit Response Time (LDO Power Up to
Hard Short) (TPS22949A)
20uS/DIV
Figure 40. Current Limit Response Time (LDO)
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8 Detailed Description
8.1 Overview
The TPS22949 and TPS22949A are devices that provide protection to systems and loads in high-current
conditions. The device contains a 500-mΩ current-limited P-channel MOSFET that can operate over an input
voltage range of 1.62 V to 4.5 V. In addition, these devices feature a low-dropout regulator (LDO) with a fixed
output voltage of 1.8 V. When the switch current reaches the maximum limit, the TPS22949/TPS22949A
operates in a constant-current mode to prohibit excessive currents from causing damage. The fault signal pin
(OC) will signal the constant current condition if it persists after 12 ms. The output of the current limiter is
internally connected to the LDO.
8.2 Functional Block Diagram
V+, Supply bias
(2.5 V to 5.5 V)
OC, Over-current flag
Current Limiter
with
Auto-Restart Feature
VIN, Current limiter input
(1.62 V to 4.5 V)
VOUTCL, Current limiter output
EN1, Active high
Low-Noise LDO
VOUTLDO, LDO output
(Fixed, 1.8 V max, 100 mA)
EN2, Active high
GND
Figure 41. Simplified Block Diagram
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Functional Block Diagram (continued)
VIN
C2 (3)
UVLO
+
–
EN1
EN2
D2 (4)
A2 (1)
Control
Logic
Current
Limit
C1 (6)
VOUTCL
UVLO
V+
A1 (8)
Bandgap
+
–
output discharge
B1 (7)
Thermal
Shutdown
D1 (5)
VOUTLDO
OC
GND
Figure 42. Detailed Block Diagram
8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
The undervoltage lockout turns off the switch if the input voltage drops below the undervoltage lockout threshold.
With the ON pin active, the input voltage rising above the undervoltage lockout threshold causes a controlled
turnon of the switch, which limits current overshoots. The TPS22949 and TPS22949A also have a UVLO on the
V+ bias voltage and keep the output of the LDO shut off until the internal circuitry is operating properly.
8.3.2 Fault Reporting
When an overcurrent, input undervoltage, or overtemperature condition is detected, OC is set active low to signal
the fault mode. OC is an open-drain MOSFET and requires a pullup resistor between VIN and OC. During
shutdown, the pulldown on OC is disabled, thus reducing current draw from the supply.
8.3.3 Current Limiting
When the switch current reaches the maximum limit, the TPS22949/TPS22949A operates in a constant-current
mode to prohibit excessive currents from causing damage. TPS22949/TPS22949A has a minimum current limit
of 100 mA.
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8.4 Device Functional Modes
Table 1 summarizes the LDO state as determined by the EN1 and EN2 pins.
Table 1. Function Table
STATE OF THE DEVICE
EN1
EN2
Current limiter and LDO disabled
0
X
Current limiter enabled and LDO disabled
1
0
Current limiter and LDO enabled
1
1
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This application illustrates the TPS22949 and TPS22949A configured with a 100-mA sinking load with both
enables tied to the same input voltage.
9.1.1 Input Voltage
The input voltage (VIN) of the current limiter is set from 1.62 V to 4.5 V, however if both the current limiter and the
LDO are enabled, the user must be careful to keep the input voltage (VIN) greater than 1.8 V + (voltage drop
through the switch) + (voltage drop through the LDO); otherwise, the LDO does not have a high enough internal
input signal to operate properly.
A current limiter input voltage ramp time less than the blanking time (approximately 10 ms typical) is
recommended. If the ramp time extends beyond the blanking period, then the current limiter goes into recycle,
and the system may not start or operate properly.
9.1.2 Input/Output Capacitors
Although an input capacitor is not required for stability of on the input pin (VIN), it is good analog design practice
to connect a 0.1-μF to 1-μF low equivalent series resistance (ESR) capacitor across the IN pin input supply near
the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection,
and ripple rejection. A higher value capacitor may be necessary if large, fast rise time load transients are
anticipated, or if the device is located close to the power source. If source impedance is not sufficiently low, a
0.1-μF input capacitor may be necessary to ensure stability. The V+ bias pin does not require an input capacitor
because it does not source high currents. However, if source impedance is not sufficiently low, a small 0.1-μF
bypass capacitor is recommended.
A 0.1-μF capacitor CCL, must be placed between VOUTCL and GND. This capacitor prevents parasitic board
inductances from forcing VOUTCL below GND when the switch turns off.
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9.2 Typical Application
TPS22949
TPS22949A
VIN
VIN
VOUTCL
VOUTCL
EN1
CIN
CCL
EN2
V+
V+
VOUTLDO
(1.8 V, 100 mA)
VOUTLDO
CLDO
GND
OC
OC
RPU
Figure 43. TPS22949/TPS22949A Typical Application With Both Enable Pins Tied to the Input Voltage
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
3.3 V
V+
3.3 V
CIN
4.7 µF
CLDO
2.2 µF
9.2.2 Detailed Design Procedure
9.2.2.1 Start-Up Sequence
For the TPS22949, the total output capacitance must be kept below a maximum value, CCL(max), to prevent the
part from registering an overcurrent condition and turning off the switch. The maximum output capacitance can
be determined from Equation 1:
CCL = ILIM(MAX) × tBLANK(MIN) ÷ VIN
(1)
Due to the integral body diode in the PMOS switch, a CIN greater than CCL is highly recommended. A CCL greater
than CIN can cause VOUTCL to exceed VIN when the system supply is removed. This could result in current flow
through the body diode from VOUTCL to VIN.
On TPS22949, a storage capacitor (CCL) at the output of the current limiter is recommended to provide enough
current to the LDO during the start-up sequence. The storage capacitor is needed to reduce the amount of inrush
current supplied through the current-limited load switch to the LDO during the power-up sequence (see
Figure 44). If the CCL capacitor is too small, the inrush current needed to start the LDO and charge CLDO could be
interpreted by the current limiter as an overcurrent and, therefore, trigger the current-limiting feature of the
switch. The switch would then try to limit the current to the 100-mA limit, and the user would see an undesired
drop on the supply line (see Figure 45).
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On TPS22949A, the storage capacitor (CCL) is not required. TPS22949A integrates an additional internal circuitry
that increases the current limit of the switch to approximately 750 mA (that is, ILIM(INRUSH)) for about 250 μs (that
is, tINRUSH), initiated when the internal circuitry of the LDO is operating properly (that is, when the UVLO of the
LDO bias (V+) is disabled (V+ > 2.6 V). Because the current limit is increased during the power-up sequence, a
potential inrush current through the LDO is not interpreted by the current limiter as an overcurrent. The current
needed by the LDO is then be supplied by the input capacitor (CIN) of the current limiter (see Figure 45).
The TPS22949 LDO (VOUTLDO) is designed to be stable with standard ceramic capacitors with values of 2.2 μF or
larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and
ESR over temperature. Maximum ESR must be less than 250 mΩ. Figure 43, Figure 44, and Figure 45 illustrate
the behavior of the TPS22949 and TPS22949A with a 100-mA sinking load and different capacitor values for a
typical application where both enables are tied to the same input voltage (see Figure 43).
9.2.3 Application Curves
3.5
3.5
3.0
3.0
VIN
VOUTCL
VIN
VLDO
VOUTCL
VLDO
2.5
2.0
Voltage (V)
Voltage(V)
2.5
1.5
VIN = V+ = VEN1 = VEN2 = 3.3 V
2.0
1.5
VIN = V+ = VEN1 = VEN2 = 3.3 V
CIN = 4.7 mF, CCL = 0 mF
CIN = 4.7 mF, CCL = 2.2 mF
1.0
CLDO = 2.2 mF
CLDO = 2.2 mF
1.0
0.5
0.5
0.0
0
0.0005
0.001
0.0015
0.002
0.0025
0.0
Time (s)
0
0.0005
0.001
0.0015
0.002
0.0025
Time (s)
Figure 44. TPS22949 Power-Up Sequence
Figure 45. TPS22949 Power-Up Sequence
3.5
3.0
VIN
VOUTCL
VLDO
Voltage (V)
2.5
2.0
1.5
VIN = V+ = VEN1 = VEN2 = 3.3 V
CIN = 4.7 mF, CCL = 0 mF
1.0
CLDO = 2.2 mF
0.5
0.0
-0.5
0
0.0005
0.001
0.0015
Time (s)
0.002
0.0025
Figure 46. TPS22949A Power-Up Sequence
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9.3 System Examples
VIN
VIN
VOUTCL
VOUTCL
EN1
CIN = 4.7 µF
CCL = 4.7 µF
EN2
V+
V+
VOUTLDO
VOUTLDO
TPS22949
GND
CLDO = 2.2 µF
OC
OC
RPU
Figure 47. TPS22949 Typical Application Schematic
VIN
VIN
VOUTCL
VOUTCL
EN1
CIN = 4.7 µF
CCL = 0.1 µF
EN2
V+
V+
TPS22949A
GND
VOUTLDO
VOUTLDO
CLDO = 2.2 µF
OC
OC
RPU
Figure 48. TPS22949A Typical Application Schematic
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10 Power Supply Recommendations
The device is designed to operate from a V+ range of 2.6 V to 5.5 V and VIN range of 1.62 V to 4.5 V (without
using the LDO) or >1.8 V to 4.5 V (when using the LDO). This supply must be placed as close to the device pin
as possible with the recommended input bypass capacitor. If the supply is located more than a few inches from
the device pins, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. If
additional bulk capacitance is required, an electrolytic, tantalum, or ceramic capacitor of 10 μF may be sufficient.
11 Layout
11.1 Layout Guidelines
For best performance, all traces must be as short as possible. To be most effective, the input and output
capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for VIN, V+, VOUTLDO, VOUTCL, and GND helps minimize the parasitic
electrical effects along with minimizing the case to ambient thermal impedance.
11.2 Layout Example
VIA to Power Plane
VIA to GND
EN2
V+
GND
VOUTLDO
VIN
VOUTCL
EN1
OC
Exposed Thermal
Pad Area
Figure 49. Layout Schematic
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS22949
Click here
Click here
Click here
Click here
Click here
TPS22949A
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS22949ADRGR
ACTIVE
SON
DRG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZUG
TPS22949AYZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(4Z, 4Z2)
TPS22949YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(4Y, 4Y2)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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