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TPS22985
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SLVSBA9B – MARCH 2012 – REVISED JUNE 2012
Thunderbolt™ SUPPLY SELECTION IC
Check for Samples: TPS22985
FEATURES
1
•
•
•
•
•
•
•
2
2.8 V to 19.8 V
Auto Selects 3.3 V Supply
> 10-mA Low Power Switch
> 500-mA High Power Switch
Reverse Current Blocking From OUT to VDD
Wake on UART Input Activity
UART RX and TX Buffers
Thunderbolt™ Cables
Notebook Computers
Desktop Computers
Power Management Systems
VDD2
VDD1
Charge
Pump
RESETZ
FET 1
FET 3
Logic
Core
ENB
CFG/OE
FET 4
FET 2
Level
Shifter
RXC
In either mode, when a valid VDD is not available, the
TPS22985 opens all switches and the outputs OUTA
and OUTB become high impedance. When the
connected VDD exceeds a maximum voltage of 3.6V,
it is disconnected from the outputs. VDD2 will only
connect when it is in the valid range and VDD1 is
greater than 3.6V
The TPS22985 is available in a 1.6mm x 1.6mm
WCSP package.
TXC
GND
TXH
OUTA
RXH
TX
Level
Shifter
OUTB
RX
The TPS22985 has two modes of operation, Normal
and Control.
In Control Mode, OUTA functions the same as
Normal Mode and OUTB is controlled by a
combination of monitored inputs and valid supplies on
VDD1 and VDD2. When a valid VDD is available, the
device waits for a rising input on ENB and then
disconnects OUTB until the next falling RXH
transition. Once the next falling RXH transition
occurs, the device reconnects OUTB.
VDD2
VDD1
CPO
The TPS22985 is a supply selection device for active
Thunderbolt™ cables. The device selects a supply
that is at 3.3V from two supply inputs and connects
this to two non-current limited outputs OUTA and
OUTB. When 3.3V is not present at either supply, the
outputs become high impedance.
In Normal Mode, OUTA is always on when a valid
supply is present. OUTB is connected to a valid VDD
when the ENB input is high.
APPLICATIONS
•
•
•
•
DESCRIPTION
CFG2 (ThunderboltTM)
Cable uC and CDR Retimier
Figure 1. Typical Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Thunderbolt is a trademark of Intel Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
Not Recommended for New Designs
TPS22985
SLVSBA9B – MARCH 2012 – REVISED JUNE 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
PART NUMBER
PACKAGE MARKING (1)
PACKAGE
DEVICE SPECIFIC FEATURES
TPS22985YFP
YMD9US
YFP
WCSP
Y= Year, M = Month, D = Sequence Code, 9U = TPS22985 Device Code, S = Wafer Fab/Assembly Site Code
Top View
Footprint
Bump View
1
2
3
4
D
D1
D2
D3
D4
D
C
C
C1
C2
C3
C4
C
B1
B
B
B1
B2
B3
B4
B
A2
A1
A
A
A1
A2
A3
A4
A
2
1
1
2
4
3
2
1
D
D4
D3
D2
D1
D
C
C4
C3
C2
C1
B
B4
B3
B2
A
A4
A3
4
3
3
4
Die Size: 1.6mm x 1.6mm
Bump Size: 0.25mm
Bump Pitch: 0.4mm
Table 1. TPS22985 Pin Mapping (Top View)
4
3
2
1
D
VDD1
VDD1
VDD2
VDD2
C
OUTA
OUTB
OUTB
GND
B
RXH
TXH
RESETZ
CPO
A
RXC
TXC
ENB
CFG/OE
DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
THERMAL RESISTANCE
θJA
THERMAL
RESISTANCE (1)
θJB
POWER RATING
TA = 25°C
DERATING FACTOR
ABOVE (2)
TA = 25°C
YFP
95°C/W
63°C/W
1050 mW
10.5 mW/°C
Simulated with high-K board
Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / θJA.
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TPS22985
SLVSBA9B – MARCH 2012 – REVISED JUNE 2012
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Voltage range on VDD1, VDD2, OUTA, OUTB (3)
VI
Voltage range on RXC, TXC, RESETZ, CFG/OE, ENB
TA
TJ
(2)
(MAX)
Tstg
(3)
(VDD is the active 3.3V input)
V
–0.3 to 13
V
Voltage range on RXH, TXH
–0.3 to 4.0
V
Operating ambient temperature range
–40 to 85
°C
125
°C
–65 to 150
°C
Maximum operating junction temperature
Storage temperature range
Contact discharge on VDD1, VDD2 (IEC 61000-4-2) (4)
(3)
(4)
V
–0.3 to VDD+0.3
Charge Device Model (JESD 22 C101)
(2)
UNIT
Voltage range on CPO
Human Body Model (JESD 22 A114)
(1)
VALUE
–0.3 to 20
350
V
2
kV
4.4
kV
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max))
All voltage values are with respect to network ground terminal.
IEC tests are run with 0.1 µF on VDD1 and VDD2. IEC rating is non-destructive.
RECOMMENDED OPERATING CONDITIONS
MIN
VDD1
MAX
UNIT
2.8
19.8
2.8
19.8
FET1 and FET2 switch current range
0
10
mA
ILIM3/4
FET3 and FET4 switch current range
0
500
mA
VIH
Input logic high
RXH, TXC, CFG/OE, ENB
2
VIL
Input logic low
RXH, TXC, CFG/OE, ENB
0.8
V
VOH
Output logic high
RXC, TXH, RESETZ
VOL
Output logic low
RXC, TXH, RESETZ
0.4
V
VDD2
ILIM1/2
COUT
Supply voltage range
V
V
2.25
V
Output capacitance on OUTA
1
4
Output capacitance on OUTB
4
22
2
10
nF
–40
85
°C
CCPO
Output capacitance on CPO
TA
Operating temperature range
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ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies over the VDD range and operating junction temp –40°C ≤ TJ ≤ 85°C. Typical
values are for VDD = 3.3V and TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES AND CURRENTS
VDD1/2
Input voltage range
IDD-1
VDD1 Quiescent current
2.8
IDD-2
VDD2 Quiescent current
VDD1 = 2.5 to 15 V
250
VDD2 = 3.3 V, VDD1 = 3.3 V
20
VDD2 = 3.3 V, VDD1 = 15 V
20
19.8
V
500
µA
µA
IDDOFF-2
VDD2 Off current
VDD2 = 3.3 V, VDD1 = 0 V
1
µA
IIN-ENB
ENB Input current
VIN = 1.8 V to 3.6 V
1
µA
IIN-UART
RXH Input current
VIN = 1.8V to 3.6 V
1
µA
–5
µA
(1)
IIN-CFGOE
CFG/OE Input current
VPUCFGOE
CFG/OE pull-up voltage (1)
IIN-RESETZ
RESETZ Input current
VCFG/OE = 0 V
–1
–1.8
2.3
VRESETZ = 100 mV
0.8
6.7
2
3
V
mA
SWITCH AND RESISTANCE CHARACTERISTICSS
RF1
FET1 On resistance
RF2
FET2 On resistance
RF3
FET3 On resistance
RF4
FET4 On resistance
RPDRESETZ
RESETZ Pull-down resistance
RPUCFGOE
CFG/OE Pull-up resistance (1)
RPDUART
TXC Pull-down resistance
5
VDD = 3.3 V, IOUT = 10 mA
5
VDD = 3.3 V, IOUT = 350 mA
170
250
170
250
Ω
mΩ
33
50
100
Ω
1.2
2
2.6
MΩ
See the UART RX andTX Section
80
130
180
kΩ
3.3V Supply rising
3.5
3.55
3.6
V
20
40
60
mV
3.3V Supply rising
2.7
2.75
2.8
3.3V Supply falling
2.4
2.45
2.5
7
8
9
RESETZ asserted
VOLTAGE THESHOLDS AND AMPLITUDES
VHVLO
High voltage lockout
Hysteresis
VUVLO
Under voltage lockout
VCPO
Charge pump voltage
CCPO = 2 nF, ICPO = 0 µA
VOS
Voltage overshoot on OUTA/B
COUTB = 4 µF, IOUTB = 0 mA,
COUTA = 1 µF, IOUTA = 0 mA
VDD1 SR3.3→4V =10 mV/µs
(1)
4
200
V
V
mV
CFG/OE is pulled up to VPUCFGOE through the resistance RPUCFGOE.
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TPS22985
SLVSBA9B – MARCH 2012 – REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted the specification applies over the VDD range and operating junction temp –40°C ≤ TJ ≤ 85°C. Typical
values are for VDD = 3.3V and TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
130
°C
THERMAL SHUTDOWN
TSD
Shutdown temperature
TSDHYST
Shutdown hysteresis
110
15
°C
TRANSITION TIMING
td
UVLO to FETn open time
te
UVLO to FETn closed time
tdh
HVLO to FETn open time
teh
HVLO to FETn closed time
COUTB = 4 µF,
COUTA = 1 µF
200
µs
2
ms
20
µs
2
ms
200
µs
6
7
ms
2
10
µs
See The Supply Switch-Over During HVLO
Section
TRANSITION TIMING (NORMAL MODE)
teb
ENB to FET3/4 closed time
tdb
ENB to FET3/4 open time
COUTB = 4 µF,
COUTA = 1 µF
TRANSITION TIMING (CONTROL MODE)
tU2R
UVLO to RESETZ time
tE2R
ENB to RESETZ time
5
tE2O
ENB to FET3/4 open time
COUTB = 4 µF,
COUTA = 1 µF
100
200
µs
tRX2O
RX to FET3/4 closed time
COUTB = 4 µF,
COUTA = 1 µF
0.8
2
ms
tRX2R
RX to RESETZ Time
6
7
ms
tOE2TX
OE to TXH Valid Time
20
µs
tOE2TXZ
OE to TXH Hi-Z Time
20
µs
5
TXC/TXH I/O (CONTROL MODE)
VIH
TXC Input logic high
VIL
TXC Input logic low
VOH
TXH Output logic high
VOL
TXH Output logic low
TR / TF
TXH Rise and fall time
ZO
TXH Output impedance
fMAX
TX Input signal frequency
DC
TX Duty cycle
2
V
0.8
2.25
10-90% CL = 20 pF
V
5
0.4
V
70
ns
1
Mb/s
Ω
35
40%
V
60%
RXC/RXH I/O (CONTROL MODE)
VIH
RXH Input logic high
VIL
RXH Input logic low
VOH
RXC Output logic high
VOL
RXC Output logic low
TR / TF
RXC Rise and fall time
fMAX
RX Input signal frequency
DC
RX Duty cycle
2
V
0.8
2.25
V
0.4
10-90% CL = 20 pF
20
120
1
40%
Product Folder Link(s): TPS22985
V
ns
Mb/s
60%
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VDD1
VDD2
FUNCTIONAL BLOCK DIAGRAM
CPO
Charge
Pump
RESET Z
FET 1
FET 3
Logic
Core
ENB
FET 4
CFG/OE
FET 2
Level
Shifter
RXH
Level
Shifter
TXC
GND
OUTA
OUTB
TXH
RXC
Figure 2. Functional Bock Diagram
6
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TPS22985
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DEVICE INFORMATION
PIN FUNCTIONS
PIN NAME
TYPE
VDD1
Supply
Device Supply 1. 0V to 19.8-V Input.
VDD2
Supply
Device Supply 2. 0V to 19.8-V Input.
OUTA
Output
Output A. 10-mA capable output. Refer to the Supply Selection section for more information.
OUTB
Output
Output B. 500-mA capable output. Refer to the Normal Mode and Control Mode sections for more information.
CPO
Output
Charge Pump Output. This pin is the output of the internal charge pump. It drives the gates of the internal FET
switches. Connect a capacitor of at least 2nF to this pin.
CFG/OE
Input
Mode Configuration/Output Enable. When CFG is floating, the device is in Normal Mode. When CFG is
ground, the device is in Control Mode (see the APPLICATION INFORMATION section for more information).
The mode is latched at power-up. When the device enters Control Mode, this pin becomes an output enable for
the UART TXH output. See the UART RX and TX section for more information. A pull-down resistance between
this pin and GND is recommended when Control Mode is desired.
RXH
Input
UART RX Input. Monitored Input for data activity to enable outputs. In Control Mode, this pin is monitored for a
high to low transition to enable the outputs. This input is level shifted and driven on RXC. See the UART RX
and TX section for more information.
RXC
Output
UART RX Output. This output is a level shifted version of RXH. RXC is referenced to OUTA. See the UART
RX and TX section for more information.
TXC
Input
UART TX Input. This input is buffered and level shifted on TXH. See the UART RX and TX section for more
information.
TXH
Output
UART TX Output. This output is a buffered and level shifted version of TXC. TXH is referenced to OUTA. See
the UART RX and TX section for more information.
RESETZ
Output
Microcontroller Reset. This pin is a delayed reset signal indicating OUTB is connected to a valid VDD.
RESETZ in an open-drain pull-down. RESETZ is low when OUTB is high impedance.
ENB
Input
GND
Supply
DESCRIPTION
OUTB Enable. In Normal Mode, this pin is the active high OUTB enable. In Control Mode, this pin opens OUTB
when asserted high and resets the device until a new transition on RX occurs.
Device ground.
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APPLICATION INFORMATION
Supply Selection
The TPS22985 selects between two seperate power supplies, VDD1 or VDD2, and connects these to two
outputs (OUTA and OUTB) through non-current limited switches. When a valid VDD (VUVLO < VDD < VHVLO) is
present on VDD1, VDD1 will be connected to the outputs. When VDD1 > VHVLO, the TPS22985 will connect the
outputs to VDD2 when a valid VDD is present on this input. OUTB is also opened and closed by other digital
inputs, ENB and RXH, depending on the mode of the TPS22985. Refer to the Normal Mode and Control Mode
sections for more information on the control of OUTB. VDD1 and VDD2 can power up in any order; however,
VDD1 always takes priority over VDD2 and only allows VDD2 to connect when the VDD1 > VHVLO condition is
present. When the outputs are connected to VDD2, and VDD1 drops below VHVLO, the TPS22985 will disconnect
the outputs from VDD2. Figure 3 shows a flow diagram illustrating the selection of VDD1 or VDD2 as the
appropriate supply to connect to OUTA and OUTB. Note, this diagram does not show the enabling and disabling
of OUTB by ENB and RXH.
OPEN
no
UVLO <
VDD2
> HVLO
yes
Transition
VDD1
(VDD2 Open)
Transition
VDD2
(VDD1 Open)
VDD1
Open
VDD2
Open
OUT >
VDD1
OUT >
VDD2
no
no
VDD1
> HVLO
no
yes
VDD1
> UVLO
no
yes
UVLO <
VDD1
> HVLO
yes
Transition
VDD1
VDD1
Soft Start
yes
VDD1
> UVLO
VDD1
no
yes
VDD1
> HVLO
VDD2
Soft Start
OUT >
VDD1-VH
yes
OUT >
VDD2-VH
no
no
no
Exit
Exit
yes
VH < RSW(MIN) * ILIM(MIN)
UVLO <
VDD2
> HVLO
Soft start turns on limited number of legs when OUT is
less than VDD to prevent supply from current limiting.
Once OUT is within VH of VDD, all legs turn on to get
low resistance.
no
yes
Transition
VDD2
VDD2
yes
no
VDD1
> HVLO
yes
UVLO <
VDD2
> HVLO
no
Figure 3. Flow Diagram of Supply Selection and Switch-Over
8
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TPS22985
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Normal Mode
When the CFG/OE pin is floating at power-up, the device enters Normal Mode. In Normal Mode, the TPS22985
provides power via OUTA and OUTB.
OUTA is connected whenever a valid VDD is present on VDD1. OUTA may also be connected if VDD1 > VHVLO
and a valid VDD is connected to VDD2. When OUTA is connected it will supply ≥ 10 mA to a load. OUTB is
connected whenever a valid VDD is present on VDD1. OUTB may also be connected if VDD1 > VHVLO, a valid
VDD is connected to VDD2, and the control signal ENB is high. When OUTB is connected it will supply ≥ 500 mA
to a load.
When a valid VDD is not present, the TPS22985 enters into a shutdown mode and blocks current flow through
the switches.
VDD2
VDD1
VDD2
VDD1
CPO
Charge
Pump
RESET Z
FET 1
FET 3
Logic
Core
ENB
FET 4
CFG/OE
FET 2
Level
Shifter
RXH
Level
Shifter
Load
TXC
GND
OUTB
OUTA
TXH
RXC
microcontroller
Figure 4. Normal Mode Typical Application
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VHVLO
VUVLO
VDD1
VHVLO
VUVLO
VDD2
td
VOUTA
= VDD1
OUTA
VOUTA
= VDD1
VOUTA
= VDD2
td
ENB
VOUTB
= VDD1
OUTB
te
VOUTB
= VDD2
teb
tdb
Figure 5. Timing During Normal Mode
10
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Control Mode
When CFG/OE pin is grounded at power-up, the device latches into Control Mode. In Control Mode, the
TPS22985 provides power to a microcontroller/CDR device.
When a valid VDD is connected, OUTA and OUTB are connected to the VDD. OUTB remains connected to VDD
until ENB transitions high. OUTA remains connected to VDD as long as a valid VDD exists. RESETZ indicates
that a valid VDD is available at OUTB. When RESETZ is low, a valid VDD is not available, if RESETZ is high, a
valid VDD is available.
When ENB transitions high, RESETZ is asserted low and OUTB is opened until a falling edge on RXH is
detected, as illustrated in Figure 7 and Figure 8. When ENB transitions high, RESETZ will assert low after time
tE2R and OUTB will open after time tE2O. During the time tE2O, RXH is not monitored. After the time tE2O, the
TPS22985 starts monitoring RXH for a falling edge. When a falling edge occurs and a valid VDD is available,
RESETZ is transitioned from low to high and OUTB is connected to VDD until ENB transitions high again or until
no valid VDD is available. When a valid VDD is not available, RESETZ is asserted low and the TPS22985 blocks
current flow through the switches.
After the device is latched into Control Mode, the CFG/OE pin becomes the output enable for the TX buffer/levelshifter. Refer to the UART RX and TX section for more information.
OUTA can be used as a pull-up for the ThunderboltTM CFG2 connector pin as an indicator that power is available
to the cable active circuitry. Place a resistor greater than 1kΩ between OUTA and CFG2 in this case.
VDD2
VDD1
VDD2
VDD1
Charge
Pump
CPO
RESET Z
FET 1
FET 3
Logic
Core
ENB
FET 4
CFG/OE
FET 2
Level
Shifter
TXH
RXC
TXC
GND
OUTB
TX
Level
Shifter
RXH
OUTA
RX
TM
CFG2 (Thunderbolt )
Cable uC and CDR Retimier
Figure 6. Control Mode Typical Application
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VHVLO
VUVLO
VDD1
VHVLO
VUVLO
VDD2
VOUTA
= VDD1
OUTA
VOUTA
= VDD2
ENB Falls when
OUTB falls
(power removed)
ENB
VOUTB
= VDD1
OUTB
VOUTB
= VDD2
RESETZ
te
tE2R
tU2R
tE2O
Figure 7. Timing During Control Mode
RXC
OUTB
ENB
RESETZ
tE2R
tRX2O
tRX2R
tE2O
Figure 8. Timing During Control Mode Continued
12
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Typical Startup
12-15V
3.3V
VDD1
3.3V
VDD2
ENB
RXH
OUTA
OUTB
Figure 9. Typical Startup in Normal Mode
12-15V
3.3V
VDD1
3.3V
VDD2
RXH
OUTA
OUTB
ENB
Figure 10. Typical Startup Timing for Control Mode
Figure 10. Typical Startup Timing for Control Mode
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Soft Start
To prevent inrush current to the load, the TPS22985 soft starts OUTA and OUTB. When OUTA and OUTB are
first enabled, the resistance of the FET switches (FET1, FET2, FET3, and FET4) starts high and reduces every
250µs in four steps. Figure 11 shows the nominal resistance ramp profile for OUTB. The resistance shown in this
figure is the equivalent resistance through FET3 and FET4 in Figure 2.
W
12.7 W
5.9 W
1.6 W
0.17 W
0
250
500
750
ms
Figure 11. OUTB Soft Start Resistance vs Time Profile
14
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Product Folder Link(s): TPS22985
Not Recommended for New Designs
www.ti.com
TPS22985
SLVSBA9B – MARCH 2012 – REVISED JUNE 2012
Supply Switch-Over During HVLO
When OUTA and OUTB are connected to VDD1 and VDD1 crosses VHVLO, the TPS22985 will open the FET1/3
switches. Due to the delay tdh, the output will overshoot VHVLO by VOS. When a valid VDD is present on VDD2,
OUTA and OUTB will connect to VDD2 after time teh. Figure 12 illustrates this switch-over event.
The overshoot VOS will occur when the VDD (VDD1 or VDD2) that is connected to the output transitions above
VHVLO. VOS is set by the delay tdh and the slew rate of the connected VDD. However, the connection of the
outputs to VDD2 will only occur when VDD1 transitions above VHVLO and VDD2 is a valid VDD.
The following equation determines the overshoot VOS.
VOS = SRVDD × tDH
(1)
SRVDD is the slew rate of the supply that is transitioning above VHVLO. As an example, when SRVDD is 10mV/µs
and tdh is 20µs, VOS is 200mV.
When switching to VDD2 due to an HVLO event on VDD1, the outputs OUTA and OUTB are discharged by their
respective loads until they reach the VDD2 voltage. This prevents in-rush current when charging the output caps.
The discharge time teh is variable and is determined by the following equation.
teh = tdh + (VHVLO + VOS – VDD2) × CLOAD/ILOAD
(2)
In this equation, VOS is determined by Equation 1, CLOAD is the load capacitance at the respective output, and
ILOAD is load current flowing out of the same output. As an example, when VDD2 is 3.3V, tdh is 20µs, VOS is
200mV, CLOAD is 4µF, and ILOAD is 350mA, the resulting teh is 25.7µs.
Note, when VDD1 transitions above VHVLO and a valid VDD is not present on VDD2, the outputs will open and
will discharge through each respective load.
VHVLO
VDD1
VOS
OUTA/B
FET1/3 ENABLE
(Internal)
FET2/4 ENABLE
(Internal)
tdh
Connected to VDD1
Connected to VDD2
teh
Figure 12. VDD switch-over at VDD1 rising above VHVLO
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): TPS22985
15
Not Recommended for New Designs
TPS22985
SLVSBA9B – MARCH 2012 – REVISED JUNE 2012
www.ti.com
UART RX and TX
The TPS22985 provides failsafe buffers for digital UART RX and TX lines. The failsafe mechanism prevents the
RX and TX lines from being loaded when power is removed from the device. The RX line is divided into a host
side RXH input and a cable side RXC output. The TX line is divided into host side TXH output and a cable side
TXC input.
The RXH and TXC inputs are used in Control Mode only and must be pulled low when the device is in Normal
Mode. In Normal Mode, leave the RXH and TXC pins disconnected from the UART signal lines and pull low
through a > 1kΩ resistance.
In Control Mode, when the TPS22985 is unpowered or when RESETZ is asserted low, the TXH output is high
impedance. This prevents loading the system TX line and allowing other devices on the UART bus to
communicate. The RXC output is pulled low through the output driver during this same condition.
Figure 13 illustrates the RXC and TXH control when in Control Mode. When RESETZ is high, CFG/OE controls
TXH. When CFG/OE is low, TXH is high impedance. When CFG/OE is high, TXH is a buffered and level-shifted
TXC. The CFG/OE, ENB, and TXC inputs are ignored when RESETZ is asserted low. Figure 14 shows the delay
from CFG/OE to TXH.
RESETZ
CFG/OE
RXC
GND (0V)
TXH
Hi-Z
RXH
TXC
GND (0V)
Hi-Z
TXC
Hi-Z
Figure 13. UART RX and TX Buffer Control During Control Mode
CFG/OE
TXH
Hi-Z
tOE2TX
TXC
Hi-Z
tOE2TXZ
Figure 14. CFG/OE to TXH Timing During Control Mode
16
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): TPS22985
Not Recommended for New Designs
www.ti.com
TPS22985
SLVSBA9B – MARCH 2012 – REVISED JUNE 2012
THUNDERBOLTTM SYSTEM WITH TPS22980/TPS22985
EN_HV
Host uC
LSTX
RSTX
EN
LSTX
TBT
Connector
(miniDP)
TBT
Cable Plug
(miniDP)
TBT
Cable Plug
(miniDP)
OUT
TBT
Connector
(miniDP)
Host uC
RSTX
EN_HV
EN
OUT
TPS22980
TPS22980
VHV
V3P3
VHV
V3P3
Cable
VDD1 VDD2
Host
TPS22985
VDD2 VDD1
TXH
TXH
RXH
RXH
TXC
TXC
RXC
RXC
OUTA OUTB
Cable uC
CDR
Cable Connector
Device
TPS22985
OUTB OUTA
Cable uC
CDR
Cable Connector
Figure 15. Thunderbolt System with TPS22980/TPS22985
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): TPS22985
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS22985YFPR
NRND
DSBGA
YFP
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
9U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
